1 /* $NetBSD: vega20_ppt.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __VEGA20_PPT_H__ 26 #define __VEGA20_PPT_H__ 27 28 #define VEGA20_UMD_PSTATE_GFXCLK_LEVEL 0x3 29 #define VEGA20_UMD_PSTATE_SOCCLK_LEVEL 0x3 30 #define VEGA20_UMD_PSTATE_MCLK_LEVEL 0x2 31 #define VEGA20_UMD_PSTATE_UVDCLK_LEVEL 0x3 32 #define VEGA20_UMD_PSTATE_VCEMCLK_LEVEL 0x3 33 34 #define MAX_REGULAR_DPM_NUMBER 16 35 #define MAX_PCIE_CONF 2 36 37 #define VOLTAGE_SCALE 4 38 #define AVFS_CURVE 0 39 #define OD8_HOTCURVE_TEMPERATURE 85 40 41 #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF 42 #define SMU_FEATURES_LOW_SHIFT 0 43 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000 44 #define SMU_FEATURES_HIGH_SHIFT 32 45 46 enum { 47 GNLD_DPM_PREFETCHER = 0, 48 GNLD_DPM_GFXCLK, 49 GNLD_DPM_UCLK, 50 GNLD_DPM_SOCCLK, 51 GNLD_DPM_UVD, 52 GNLD_DPM_VCE, 53 GNLD_ULV, 54 GNLD_DPM_MP0CLK, 55 GNLD_DPM_LINK, 56 GNLD_DPM_DCEFCLK, 57 GNLD_DS_GFXCLK, 58 GNLD_DS_SOCCLK, 59 GNLD_DS_LCLK, 60 GNLD_PPT, 61 GNLD_TDC, 62 GNLD_THERMAL, 63 GNLD_GFX_PER_CU_CG, 64 GNLD_RM, 65 GNLD_DS_DCEFCLK, 66 GNLD_ACDC, 67 GNLD_VR0HOT, 68 GNLD_VR1HOT, 69 GNLD_FW_CTF, 70 GNLD_LED_DISPLAY, 71 GNLD_FAN_CONTROL, 72 GNLD_DIDT, 73 GNLD_GFXOFF, 74 GNLD_CG, 75 GNLD_DPM_FCLK, 76 GNLD_DS_FCLK, 77 GNLD_DS_MP1CLK, 78 GNLD_DS_MP0CLK, 79 GNLD_XGMI, 80 GNLD_ECC, 81 82 GNLD_FEATURES_MAX 83 }; 84 85 struct vega20_dpm_level { 86 bool enabled; 87 uint32_t value; 88 uint32_t param1; 89 }; 90 91 struct vega20_dpm_state { 92 uint32_t soft_min_level; 93 uint32_t soft_max_level; 94 uint32_t hard_min_level; 95 uint32_t hard_max_level; 96 }; 97 98 struct vega20_single_dpm_table { 99 uint32_t count; 100 struct vega20_dpm_state dpm_state; 101 struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 102 }; 103 104 struct vega20_pcie_table { 105 uint16_t count; 106 uint8_t pcie_gen[MAX_PCIE_CONF]; 107 uint8_t pcie_lane[MAX_PCIE_CONF]; 108 uint32_t lclk[MAX_PCIE_CONF]; 109 }; 110 111 struct vega20_dpm_table { 112 struct vega20_single_dpm_table soc_table; 113 struct vega20_single_dpm_table gfx_table; 114 struct vega20_single_dpm_table mem_table; 115 struct vega20_single_dpm_table eclk_table; 116 struct vega20_single_dpm_table vclk_table; 117 struct vega20_single_dpm_table dclk_table; 118 struct vega20_single_dpm_table dcef_table; 119 struct vega20_single_dpm_table pixel_table; 120 struct vega20_single_dpm_table display_table; 121 struct vega20_single_dpm_table phy_table; 122 struct vega20_single_dpm_table fclk_table; 123 struct vega20_pcie_table pcie_table; 124 }; 125 126 enum OD8_FEATURE_ID 127 { 128 OD8_GFXCLK_LIMITS = 1 << 0, 129 OD8_GFXCLK_CURVE = 1 << 1, 130 OD8_UCLK_MAX = 1 << 2, 131 OD8_POWER_LIMIT = 1 << 3, 132 OD8_ACOUSTIC_LIMIT_SCLK = 1 << 4, //FanMaximumRpm 133 OD8_FAN_SPEED_MIN = 1 << 5, //FanMinimumPwm 134 OD8_TEMPERATURE_FAN = 1 << 6, //FanTargetTemperature 135 OD8_TEMPERATURE_SYSTEM = 1 << 7, //MaxOpTemp 136 OD8_MEMORY_TIMING_TUNE = 1 << 8, 137 OD8_FAN_ZERO_RPM_CONTROL = 1 << 9 138 }; 139 140 enum OD8_SETTING_ID 141 { 142 OD8_SETTING_GFXCLK_FMIN = 0, 143 OD8_SETTING_GFXCLK_FMAX, 144 OD8_SETTING_GFXCLK_FREQ1, 145 OD8_SETTING_GFXCLK_VOLTAGE1, 146 OD8_SETTING_GFXCLK_FREQ2, 147 OD8_SETTING_GFXCLK_VOLTAGE2, 148 OD8_SETTING_GFXCLK_FREQ3, 149 OD8_SETTING_GFXCLK_VOLTAGE3, 150 OD8_SETTING_UCLK_FMAX, 151 OD8_SETTING_POWER_PERCENTAGE, 152 OD8_SETTING_FAN_ACOUSTIC_LIMIT, 153 OD8_SETTING_FAN_MIN_SPEED, 154 OD8_SETTING_FAN_TARGET_TEMP, 155 OD8_SETTING_OPERATING_TEMP_MAX, 156 OD8_SETTING_AC_TIMING, 157 OD8_SETTING_FAN_ZERO_RPM_CONTROL, 158 OD8_SETTING_COUNT 159 }; 160 161 struct vega20_od8_single_setting { 162 uint32_t feature_id; 163 int32_t min_value; 164 int32_t max_value; 165 int32_t current_value; 166 int32_t default_value; 167 }; 168 169 struct vega20_od8_settings { 170 struct vega20_od8_single_setting od8_settings_array[OD8_SETTING_COUNT]; 171 uint8_t *od_feature_capabilities; 172 uint32_t *od_settings_max; 173 uint32_t *od_settings_min; 174 void *od8_settings; 175 bool od_gfxclk_update; 176 bool od_memclk_update; 177 }; 178 179 extern void vega20_set_ppt_funcs(struct smu_context *smu); 180 181 #endif 182
Indexes created Tue Sep 23 01:09:51 GMT 2025