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      1 /*	$NetBSD: pccreg.h,v 1.11 2011/02/01 20:19:31 chuck Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1995 Charles D. Cranor
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 /*
     29  * peripheral channel controller on mvme147
     30  */
     31 #ifndef __MVME68K_PCCREG_H
     32 #define __MVME68K_PCCREG_H
     33 
     34 /*
     35  * Offsets to the MVME147's onboard device registers.
     36  * (Relative to the bus_space_tag_t passed in from 'mainbus')
     37  */
     38 #define PCC_LE_OFF	0x0800		/* offset of LANCE ethernet chip */
     39 #define PCC_VME_OFF	0x1000		/* offset of VME chip */
     40 #define PCC_LPT_OFF	0x1800		/* offset of parallel port register */
     41 #define PCC_ZS0_OFF	0x2000		/* offset of first 8530 UART */
     42 #define PCC_ZS1_OFF	0x2800		/* offset of second 8530 UART */
     43 #define PCC_WDSC_OFF	0x3000		/* offset of 33c93 SCSI chip */
     44 
     45 /*
     46  * This is needed to figure out the boot device.
     47  * (The physical address of the boot device's registers are passed in
     48  * from the Boot ROM)
     49  */
     50 #define PCC_PADDR(off) ((void *)(0xfffe0000u + (off)))
     51 
     52 /*
     53  * The PCC chip's own registers. These are 8-bits wide, unless
     54  * otherwise indicated.
     55  */
     56 #define PCCREG_DMA_TABLE_ADDR	0x00 /* DMA table address (32-bit) */
     57 #define PCCREG_DMA_DATA_ADDR	0x04 /* DMA data address (32-bit) */
     58 #define PCCREG_DMA_BYTE_COUNT	0x08 /* DMA byte count (32-bit) */
     59 #define PCCREG_DMA_DATA_HOLD	0x0c /* DMA data hold register (32-bit) */
     60 #define PCCREG_TMR1_PRELOAD	0x10 /* Timer1 preload (16-bit) */
     61 #define PCCREG_TMR1_COUNT	0x12 /* Timer1 count (16-bit) */
     62 #define PCCREG_TMR2_PRELOAD	0x14 /* Timer2 preload (16-bit) */
     63 #define PCCREG_TMR2_COUNT	0x16 /* Timer2 count (16-bit) */
     64 #define PCCREG_TMR1_INTR_CTRL	0x18 /* Timer1 interrupt ctrl */
     65 #define PCCREG_TMR1_CONTROL	0x19 /* Timer1 ctrl reg */
     66 #define PCCREG_TMR2_INTR_CTRL	0x1a /* Timer2 interrupt ctrl */
     67 #define PCCREG_TMR2_CONTROL	0x1b /* Timer2 ctrl reg */
     68 #define PCCREG_ACFAIL_INTR_CTRL	0x1c /* ACFAIL intr reg */
     69 #define PCCREG_WDOG_INTR_CTRL	0x1d /* Watchdog intr reg */
     70 #define PCCREG_PRNT_INTR_CTRL	0x1e /* Printer intr reg */
     71 #define PCCREG_PRNT_CONTROL	0x1f /* Printer ctrl */
     72 #define PCCREG_DMA_INTR_CTRL	0x20 /* DMA interrupt control */
     73 #define PCCREG_DMA_CONTROL	0x21 /* DMA csr */
     74 #define PCCREG_BUSERR_INTR_CTRL	0x22 /* Bus error interrupt */
     75 #define PCCREG_DMA_STATUS	0x23 /* DMA status register */
     76 #define PCCREG_ABORT_INTR_CTRL	0x24 /* ABORT interrupt control reg */
     77 #define PCCREG_TABLE_ADDR_FC	0x25 /* Table address function code reg */
     78 #define PCCREG_SERIAL_INTR_CTRL	0x26 /* Serial interrupt reg */
     79 #define PCCREG_GENERAL_CONTROL	0x27 /* General control register */
     80 #define PCCREG_LANCE_INTR_CTRL	0x28 /* Ethernet interrupt */
     81 #define PCCREG_GENERAL_STATUS	0x29 /* General status */
     82 #define PCCREG_SCSI_INTR_CTRL	0x2a /* SCSI interrupt reg */
     83 #define PCCREG_SLAVE_BASE_ADDR	0x2b /* Slave base addr reg */
     84 #define PCCREG_SOFT1_INTR_CTRL	0x2c /* Software interrupt #1 cr */
     85 #define PCCREG_VECTOR_BASE	0x2d /* Interrupt base vector register */
     86 #define PCCREG_SOFT2_INTR_CTRL	0x2e /* Software interrupt #2 cr */
     87 #define PCCREG_REVISION		0x2f /* Revision level */
     88 
     89 #define PCCREG_SIZE		0x30
     90 
     91 /*
     92  * Convenience macros for reading the PCC chip's registers
     93  * through bus_space.
     94  */
     95 #define	pcc_reg_read(sc,r)	\
     96 		bus_space_read_1((sc)->sc_bust, (sc)->sc_bush, (r))
     97 #define	pcc_reg_read16(sc,r)	\
     98 		bus_space_read_2((sc)->sc_bust, (sc)->sc_bush, (r))
     99 #define	pcc_reg_read32(sc,r)	\
    100 		bus_space_read_4((sc)->sc_bust, (sc)->sc_bush, (r))
    101 #define	pcc_reg_write(sc,r,v)	\
    102 		bus_space_write_1((sc)->sc_bust, (sc)->sc_bush, (r), (v))
    103 #define	pcc_reg_write16(sc,r,v)	\
    104 		bus_space_write_2((sc)->sc_bust, (sc)->sc_bush, (r), (v))
    105 #define	pcc_reg_write32(sc,r,v)	\
    106 		bus_space_write_4((sc)->sc_bust, (sc)->sc_bush, (r), (v))
    107 
    108 
    109 /*
    110  * we lock off our interrupt vector at 0x40.
    111  */
    112 
    113 #define PCC_VECBASE	0x40
    114 #define PCC_NVEC	12
    115 
    116 /*
    117  * vectors we use
    118  */
    119 
    120 #define PCCV_ACFAIL	0
    121 #define PCCV_BERR	1
    122 #define PCCV_ABORT	2
    123 #define PCCV_ZS		3
    124 #define PCCV_LE		4
    125 #define PCCV_SCSI	5
    126 #define PCCV_DMA	6
    127 #define PCCV_PRINTER	7
    128 #define PCCV_TIMER1	8
    129 #define PCCV_TIMER2	9
    130 #define PCCV_SOFT1	10
    131 #define PCCV_SOFT2	11
    132 
    133 /*
    134  * enable interrupt
    135  */
    136 
    137 #define PCC_ICLEAR  0x80
    138 #define PCC_IENABLE 0x08
    139 
    140 /*
    141  * interrupt mask
    142  */
    143 
    144 #define PCC_IMASK 0x7
    145 
    146 /*
    147  * clock/timer
    148  */
    149 
    150 #define PCC_TIMERACK		0x80	/* ack intr */
    151 #define PCC_TIMERCLEAR		0x0	/* reset and clear timer */
    152 #define PCC_TIMERENABLE		0x1	/* Enable clock */
    153 #define PCC_TIMERSTOP		0x3	/* stop clock, but don't clear it */
    154 #define PCC_TIMERSTART		0x7	/* start timer */
    155 #define PCC_TIMEROVFLSHIFT	4
    156 
    157 #define PCC_TIMERFREQ		160000
    158 #define pcc_timer_hz2lim(hz)	(0x10000 - (PCC_TIMERFREQ/(hz)))
    159 #define pcc_timer_us2lim(us)	(0x10000 - (PCC_TIMERFREQ/(1000000/(us))))
    160 
    161 /*
    162  * serial control
    163  */
    164 
    165 #define PCC_ZSEXTERN 0x10	/* let PCC supply vector */
    166 
    167 /*
    168  * abort switch
    169  */
    170 
    171 #define PCC_ABORT_IEN	0x08	/* enable interrupt */
    172 #define PCC_ABORT_ABS	0x40	/* current state of switch */
    173 #define PCC_ABORT_ACK	0x80	/* interrupt active; write to ack */
    174 
    175 /*
    176  * general control register
    177  */
    178 
    179 #define PCC_GENCR_IEN	0x10	/* global interrupt enable */
    180 
    181 /*
    182  * slave base address register
    183  */
    184 #define PCC_SLAVE_BASE_MASK	(0x01fu)
    185 
    186 #endif /* __MVME68K_PCCREG_H */
    187