| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/microchip/ |
| mpfs-m100pfs-fabric.dtsi | 17 pcie: pcie@2000000000 { label
18 compatible = "microchip,pcie-host-1.0";
36 msi-parent = <&pcie>;
|
| mpfs-polarberry-fabric.dtsi | 17 pcie: pcie@2000000000 { label
18 compatible = "microchip,pcie-host-1.0";
36 msi-parent = <&pcie>;
|
| mpfs-icicle-kit-fabric.dtsi | 29 pcie: pcie@3000000000 { label
30 compatible = "microchip,pcie-host-1.0";
49 msi-parent = <&pcie>;
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pci/ |
| priv.h | 29 } pcie; member in struct:nvkm_pci_func
41 /* pcie functions */
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx7d.dtsi | 120 pcie_phy: pcie-phy@306d0000 {
121 compatible = "fsl,imx7d-pcie-phy";
166 pcie: pcie@33800000 { label
167 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
194 clock-names = "pcie", "pcie_bus", "pcie_phy";
206 fsl,imx7d-pcie-phy = <&pcie_phy>;
|
| artpec6.dtsi | 162 pcie: pcie@f8050000 { label
163 compatible = "axis,artpec6-pcie", "snps,dw-pcie";
185 axis,syscon-pcie = <&syscon>;
190 compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
199 axis,syscon-pcie = <&syscon>;
|
| mt7629.dtsi | 364 pcie: pcie@1a140000 { label
365 compatible = "mediatek,mt7629-pcie";
390 phy-names = "pcie-phy1";
395 pcie1: pcie@1,0 {
425 pcieport1: pcie-phy@0 {
|
| dove.dtsi | 84 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
85 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
93 pcie: pcie { label
94 compatible = "marvell,dove-pcie";
110 pcie0: pcie@1 {
116 marvell,pcie-port = <0>;
129 pcie1: pcie@2 {
135 marvell,pcie-port = <1>;
|
| mt7623.dtsi | 722 pcie: pcie@1a140000 { label
723 compatible = "mediatek,mt7623-pcie";
725 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
745 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
749 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"
[all...] |
| imx6qdl.dtsi | 266 pcie: pcie@1ffc000 { label
267 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
290 clock-names = "pcie", "pcie_bus", "pcie_phy";
|
| imx6sx.dtsi | 1397 pcie: pcie@8ffc000 { label
1398 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1420 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1422 power-domain-names = "pcie", "pcie_phy";
|
| qcom-apq8064.dtsi | 1376 pcie: pci@1b500000 { label
1377 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/ |
| pci.h | 38 } pcie; member in struct:nvkm_pci
61 /* pcie functions */
|
| /src/sys/arch/arm/apple/ |
| apple_platform.c | 169 const int pcie = of_find_bycompat(OF_finddevice("/"), "apple,pcie"); local in function:apple_platform_get_mac_address
170 if (pcie == -1) {
178 for (bridge = OF_child(pcie); bridge; bridge = OF_peer(bridge)) {
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/hisilicon/ |
| hi3798cv200.dtsi | 557 pcie: pcie@9860000 { label in label:soc
558 compatible = "hisilicon,hi3798cv200-pcie";
|
| /src/sys/arch/arm/acpi/ |
| acpi_pci_layerscape_gen4.c | 33 * NXP Layerscape PCIe Gen4 controller (not ECAM compliant)
85 acpi_pci_layerscape_gen4_ccsr_setpage(struct acpi_pci_layerscape_gen4 *pcie, u_int page_index)
89 val = bus_space_read_4(pcie->bst, pcie->bsh, PAB_CTRL);
92 bus_space_write_4(pcie->bst, pcie->bsh, PAB_CTRL, val);
96 acpi_pci_layerscape_gen4_ccsr_read4(struct acpi_pci_layerscape_gen4 *pcie, bus_size_t reg)
102 acpi_pci_layerscape_gen4_ccsr_setpage(pcie, page_index);
103 return bus_space_read_4(pcie->bst, pcie->bsh, page_addr)
154 struct acpi_pci_layerscape_gen4 *pcie = ap->ap_conf_priv; local in function:acpi_pci_layerscape_gen4_conf_read
188 struct acpi_pci_layerscape_gen4 *pcie = ap->ap_conf_priv; local in function:acpi_pci_layerscape_gen4_conf_write
241 struct acpi_pci_layerscape_gen4 *pcie; local in function:acpi_pci_layerscape_gen4_map
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/ |
| mt7622.dtsi | 784 pcie: pcie@1a140000 { label
785 compatible = "mediatek,mt7622-pcie";
815 pcie0: pcie@0,0 {
835 pcie1: pcie@1,0 {
|
| mt2712e.dtsi | 918 pcie: pcie@11700000 { label
919 compatible = "mediatek,mt2712-pcie";
934 phy-names = "pcie-phy0", "pcie-phy1";
938 pcie0: pcie@0,0 {
958 pcie1: pcie@1,0 {
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/socionext/ |
| uniphier-pxs3.dtsi | 794 pcie: pcie@66000000 { label
795 compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
821 phy-names = "pcie-phy";
833 compatible = "socionext,uniphier-pxs3-pcie-phy";
|
| uniphier-ld20.dtsi | 897 pcie: pcie@66000000 { label
898 compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
924 phy-names = "pcie-phy";
936 compatible = "socionext,uniphier-ld20-pcie-phy";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/xilinx/ |
| zynqmp.dtsi | 604 pcie: pcie@fd0e0000 { label
605 compatible = "xlnx,nwl-pcie-2.11";
620 msi-parent = <&pcie>;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| power_state.h | 159 struct PP_StatePcieBlock pcie; member in struct:pp_power_state
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/exynos/ |
| exynos5433.dtsi | 1940 pcie_phy: pcie-phy@15680000 {
1941 compatible = "samsung,exynos5433-pcie-phy";
1949 pcie: pcie@15700000 { label
1950 compatible = "samsung,exynos5433-pcie";
1961 clock-names = "pcie", "pcie_bus";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/ |
| qcs404.dtsi | 1277 pcie: pci@10000000 { label
1278 compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/ |
| meson-g12-common.dtsi | 129 pcie: pcie@fc000000 { label
130 compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
158 phy-names = "pcie";
1697 compatible = "amlogic,g12a-usb3-pcie-phy";
|
