1 /* $NetBSD: arn9003.c,v 1.17 2024/07/05 04:31:50 rin Exp $ */ 2 /* $OpenBSD: ar9003.c,v 1.25 2012/10/20 09:53:32 stsp Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 * Routines for AR9003 family. 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: arn9003.c,v 1.17 2024/07/05 04:31:50 rin Exp $"); 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/queue.h> 37 #include <sys/callout.h> 38 #include <sys/conf.h> 39 #include <sys/device.h> 40 41 #include <sys/bus.h> 42 #include <sys/endian.h> 43 #include <sys/intr.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/if_dl.h> 49 #include <net/if_ether.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <netinet/in.h> 54 #include <netinet/in_systm.h> 55 #include <netinet/in_var.h> 56 #include <netinet/ip.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_amrr.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <dev/ic/athnreg.h> 63 #include <dev/ic/athnvar.h> 64 #include <dev/ic/arn9003reg.h> 65 #include <dev/ic/arn9003.h> 66 67 #define Static static 68 69 Static void ar9003_calib_iq(struct athn_softc *); 70 Static int ar9003_calib_tx_iq(struct athn_softc *); 71 Static int ar9003_compute_predistortion(struct athn_softc *, 72 const uint32_t *, const uint32_t *); 73 Static void ar9003_disable_ofdm_weak_signal(struct athn_softc *); 74 Static void ar9003_disable_phy(struct athn_softc *); 75 Static int ar9003_dma_alloc(struct athn_softc *); 76 Static void ar9003_dma_free(struct athn_softc *); 77 Static void ar9003_do_calib(struct athn_softc *); 78 Static void ar9003_do_noisefloor_calib(struct athn_softc *); 79 Static void ar9003_enable_antenna_diversity(struct athn_softc *); 80 Static void ar9003_enable_ofdm_weak_signal(struct athn_softc *); 81 Static void ar9003_enable_predistorter(struct athn_softc *, int); 82 Static int ar9003_find_rom(struct athn_softc *); 83 Static void ar9003_force_txgain(struct athn_softc *, uint32_t); 84 Static int ar9003_get_desired_txgain(struct athn_softc *, int, int); 85 Static int ar9003_get_iq_corr(struct athn_softc *, int32_t[6], int32_t[2]); 86 Static void ar9003_gpio_config_input(struct athn_softc *, int); 87 Static void ar9003_gpio_config_output(struct athn_softc *, int, int); 88 Static int ar9003_gpio_read(struct athn_softc *, int); 89 Static void ar9003_gpio_write(struct athn_softc *, int, int); 90 Static void ar9003_hw_init(struct athn_softc *, struct ieee80211_channel *, 91 struct ieee80211_channel *); 92 Static void ar9003_init_baseband(struct athn_softc *); 93 Static void ar9003_init_chains(struct athn_softc *); 94 Static int ar9003_intr_status(struct athn_softc *); 95 Static int ar9003_intr(struct athn_softc *); 96 Static void ar9003_next_calib(struct athn_softc *); 97 Static void ar9003_paprd_enable(struct athn_softc *); 98 Static int ar9003_paprd_tx_tone(struct athn_softc *); 99 Static void ar9003_paprd_tx_tone_done(struct athn_softc *); 100 Static int ar9003_read_eep_data(struct athn_softc *, uint32_t, void *, 101 int); 102 Static int ar9003_read_eep_word(struct athn_softc *, uint32_t, 103 uint16_t *); 104 Static int ar9003_read_otp_data(struct athn_softc *, uint32_t, void *, 105 int); 106 Static int ar9003_read_otp_word(struct athn_softc *, uint32_t, 107 uint32_t *); 108 Static int ar9003_read_rom(struct athn_softc *); 109 Static void ar9003_reset_rx_gain(struct athn_softc *, 110 struct ieee80211_channel *); 111 Static void ar9003_reset_tx_gain(struct athn_softc *, 112 struct ieee80211_channel *); 113 Static int ar9003_restore_rom_block(struct athn_softc *, uint8_t, 114 uint8_t, const uint8_t *, size_t); 115 Static void ar9003_rf_bus_release(struct athn_softc *); 116 Static int ar9003_rf_bus_request(struct athn_softc *); 117 Static void ar9003_rfsilent_init(struct athn_softc *); 118 Static int ar9003_rx_alloc(struct athn_softc *, int, int); 119 Static void ar9003_rx_enable(struct athn_softc *); 120 Static void ar9003_rx_free(struct athn_softc *, int); 121 Static void ar9003_rx_intr(struct athn_softc *, int); 122 Static int ar9003_rx_process(struct athn_softc *, int); 123 Static void ar9003_rx_radiotap(struct athn_softc *, struct mbuf *, 124 struct ar_rx_status *); 125 Static void ar9003_set_cck_weak_signal(struct athn_softc *, int); 126 Static void ar9003_set_delta_slope(struct athn_softc *, 127 struct ieee80211_channel *, struct ieee80211_channel *); 128 Static void ar9003_set_firstep_level(struct athn_softc *, int); 129 Static void ar9003_set_noise_immunity_level(struct athn_softc *, int); 130 Static void ar9003_set_phy(struct athn_softc *, struct ieee80211_channel *, 131 struct ieee80211_channel *); 132 Static void ar9003_set_rf_mode(struct athn_softc *, 133 struct ieee80211_channel *); 134 Static void ar9003_set_rxchains(struct athn_softc *); 135 Static void ar9003_set_spur_immunity_level(struct athn_softc *, int); 136 Static void ar9003_set_training_gain(struct athn_softc *, int); 137 Static int ar9003_swba_intr(struct athn_softc *); 138 Static int ar9003_tx(struct athn_softc *, struct mbuf *, 139 struct ieee80211_node *, int); 140 Static int ar9003_tx_alloc(struct athn_softc *); 141 Static void ar9003_tx_free(struct athn_softc *); 142 Static void ar9003_tx_intr(struct athn_softc *); 143 Static int ar9003_tx_process(struct athn_softc *); 144 145 #ifdef notused 146 Static void ar9003_bb_load_noisefloor(struct athn_softc *); 147 Static void ar9003_get_noisefloor(struct athn_softc *, 148 struct ieee80211_channel *); 149 Static void ar9003_paprd_calib(struct athn_softc *, 150 struct ieee80211_channel *); 151 Static void ar9003_read_noisefloor(struct athn_softc *, int16_t *, 152 int16_t *); 153 Static void ar9003_write_noisefloor(struct athn_softc *, int16_t *, 154 int16_t *); 155 Static void ar9300_noisefloor_calib(struct athn_softc *); 156 #endif /* notused */ 157 158 /* 159 * XXX: See if_iwn.c:MCLGETIalt() for a better solution. 160 * XXX: Put this in a header or in athn.c so it can be shared between 161 * ar5008.c and ar9003.c? 162 */ 163 static struct mbuf * 164 MCLGETI(struct athn_softc *sc __unused, int how, 165 struct ifnet *ifp __unused, u_int size) 166 { 167 struct mbuf *m; 168 169 MGETHDR(m, how, MT_DATA); 170 if (m == NULL) 171 return NULL; 172 173 MEXTMALLOC(m, size, how); 174 if ((m->m_flags & M_EXT) == 0) { 175 m_freem(m); 176 return NULL; 177 } 178 return m; 179 } 180 181 PUBLIC int 182 ar9003_attach(struct athn_softc *sc) 183 { 184 struct athn_ops *ops = &sc->sc_ops; 185 int error; 186 187 /* Set callbacks for AR9003 family. */ 188 ops->gpio_read = ar9003_gpio_read; 189 ops->gpio_write = ar9003_gpio_write; 190 ops->gpio_config_input = ar9003_gpio_config_input; 191 ops->gpio_config_output = ar9003_gpio_config_output; 192 ops->rfsilent_init = ar9003_rfsilent_init; 193 194 ops->dma_alloc = ar9003_dma_alloc; 195 ops->dma_free = ar9003_dma_free; 196 ops->rx_enable = ar9003_rx_enable; 197 ops->intr_status = ar9003_intr_status; 198 ops->intr = ar9003_intr; 199 ops->tx = ar9003_tx; 200 201 ops->set_rf_mode = ar9003_set_rf_mode; 202 ops->rf_bus_request = ar9003_rf_bus_request; 203 ops->rf_bus_release = ar9003_rf_bus_release; 204 ops->set_phy = ar9003_set_phy; 205 ops->set_delta_slope = ar9003_set_delta_slope; 206 ops->enable_antenna_diversity = ar9003_enable_antenna_diversity; 207 ops->init_baseband = ar9003_init_baseband; 208 ops->disable_phy = ar9003_disable_phy; 209 ops->set_rxchains = ar9003_set_rxchains; 210 ops->noisefloor_calib = ar9003_do_noisefloor_calib; 211 ops->do_calib = ar9003_do_calib; 212 ops->next_calib = ar9003_next_calib; 213 ops->hw_init = ar9003_hw_init; 214 215 ops->set_noise_immunity_level = ar9003_set_noise_immunity_level; 216 ops->enable_ofdm_weak_signal = ar9003_enable_ofdm_weak_signal; 217 ops->disable_ofdm_weak_signal = ar9003_disable_ofdm_weak_signal; 218 ops->set_cck_weak_signal = ar9003_set_cck_weak_signal; 219 ops->set_firstep_level = ar9003_set_firstep_level; 220 ops->set_spur_immunity_level = ar9003_set_spur_immunity_level; 221 222 /* Set MAC registers offsets. */ 223 sc->sc_obs_off = AR_OBS; 224 sc->sc_gpio_input_en_off = AR_GPIO_INPUT_EN_VAL; 225 226 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 227 athn_config_nonpcie(sc); 228 else 229 athn_config_pcie(sc); 230 231 /* Determine ROM type and location. */ 232 if ((error = ar9003_find_rom(sc)) != 0) { 233 aprint_error_dev(sc->sc_dev, "could not find ROM\n"); 234 return error; 235 } 236 /* Read entire ROM content in memory. */ 237 if ((error = ar9003_read_rom(sc)) != 0) { 238 aprint_error_dev(sc->sc_dev, "could not read ROM\n"); 239 return error; 240 } 241 242 /* Determine if it is a non-enterprise AR9003 card. */ 243 if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_MPSD) 244 sc->sc_flags |= ATHN_FLAG_NON_ENTERPRISE; 245 246 ops->setup(sc); 247 return 0; 248 } 249 250 /* 251 * Read 16-bit word from EEPROM. 252 */ 253 Static int 254 ar9003_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val) 255 { 256 uint32_t reg; 257 int ntries; 258 259 reg = AR_READ(sc, AR_EEPROM_OFFSET(addr)); 260 for (ntries = 0; ntries < 1000; ntries++) { 261 reg = AR_READ(sc, AR_EEPROM_STATUS_DATA); 262 if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY | 263 AR_EEPROM_STATUS_DATA_PROT_ACCESS))) { 264 *val = MS(reg, AR_EEPROM_STATUS_DATA_VAL); 265 return 0; 266 } 267 DELAY(10); 268 } 269 *val = 0xffff; 270 return ETIMEDOUT; 271 } 272 273 /* 274 * Read an arbitrary number of bytes at a specified address in EEPROM. 275 * NB: The address may not be 16-bit aligned. 276 */ 277 Static int 278 ar9003_read_eep_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) 279 { 280 uint8_t *dst = buf; 281 uint16_t val; 282 int error; 283 284 if (len > 0 && (addr & 1)) { 285 /* Deal with non-aligned reads. */ 286 addr >>= 1; 287 error = ar9003_read_eep_word(sc, addr, &val); 288 if (error != 0) 289 return error; 290 *dst++ = val & 0xff; 291 addr--; 292 len--; 293 } 294 else 295 addr >>= 1; 296 for (; len >= 2; addr--, len -= 2) { 297 error = ar9003_read_eep_word(sc, addr, &val); 298 if (error != 0) 299 return error; 300 *dst++ = val >> 8; 301 *dst++ = val & 0xff; 302 } 303 if (len > 0) { 304 error = ar9003_read_eep_word(sc, addr, &val); 305 if (error != 0) 306 return error; 307 *dst++ = val >> 8; 308 } 309 return 0; 310 } 311 312 /* 313 * Read 32-bit word from OTPROM. 314 */ 315 Static int 316 ar9003_read_otp_word(struct athn_softc *sc, uint32_t addr, uint32_t *val) 317 { 318 uint32_t reg; 319 int ntries; 320 321 reg = AR_READ(sc, AR_OTP_BASE(addr)); 322 for (ntries = 0; ntries < 1000; ntries++) { 323 reg = AR_READ(sc, AR_OTP_STATUS); 324 if (MS(reg, AR_OTP_STATUS_TYPE) == AR_OTP_STATUS_VALID) { 325 *val = AR_READ(sc, AR_OTP_READ_DATA); 326 return 0; 327 } 328 DELAY(10); 329 } 330 return ETIMEDOUT; 331 } 332 333 /* 334 * Read an arbitrary number of bytes at a specified address in OTPROM. 335 * NB: The address may not be 32-bit aligned. 336 */ 337 Static int 338 ar9003_read_otp_data(struct athn_softc *sc, uint32_t addr, void *buf, int len) 339 { 340 uint8_t *dst = buf; 341 uint32_t val; 342 int error; 343 344 /* NB: not optimal for non-aligned reads, but correct. */ 345 for (; len > 0; addr--, len--) { 346 error = ar9003_read_otp_word(sc, addr >> 2, &val); 347 if (error != 0) 348 return error; 349 *dst++ = (val >> ((addr & 3) * 8)) & 0xff; 350 } 351 return 0; 352 } 353 354 /* 355 * Determine if the chip has an external EEPROM or an OTPROM and its size. 356 */ 357 Static int 358 ar9003_find_rom(struct athn_softc *sc) 359 { 360 struct athn_ops *ops = &sc->sc_ops; 361 uint32_t hdr; 362 int error; 363 364 /* Try EEPROM. */ 365 ops->read_rom_data = ar9003_read_eep_data; 366 367 sc->sc_eep_size = AR_SREV_9485(sc) ? 4096 : 1024; 368 sc->sc_eep_base = sc->sc_eep_size - 1; 369 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 370 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 371 return 0; 372 373 sc->sc_eep_size = 512; 374 sc->sc_eep_base = sc->sc_eep_size - 1; 375 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 376 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 377 return 0; 378 379 /* Try OTPROM. */ 380 ops->read_rom_data = ar9003_read_otp_data; 381 382 sc->sc_eep_size = 1024; 383 sc->sc_eep_base = sc->sc_eep_size - 1; 384 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 385 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 386 return 0; 387 388 sc->sc_eep_size = 512; 389 sc->sc_eep_base = sc->sc_eep_size - 1; 390 error = ops->read_rom_data(sc, sc->sc_eep_base, &hdr, sizeof(hdr)); 391 if (error == 0 && hdr != 0 && hdr != 0xffffffff) 392 return 0; 393 394 return EIO; /* Not found. */ 395 } 396 397 Static int 398 ar9003_restore_rom_block(struct athn_softc *sc, uint8_t alg, uint8_t ref, 399 const uint8_t *buf, size_t len) 400 { 401 const uint8_t *def, *ptr, *end; 402 uint8_t *eep = sc->sc_eep; 403 size_t off, clen; 404 405 if (alg == AR_EEP_COMPRESS_BLOCK) { 406 /* Block contains chunks that shadow ROM template. */ 407 def = sc->sc_ops.get_rom_template(sc, ref); 408 if (def == NULL) { 409 DPRINTFN(DBG_INIT, sc, "unknown template image %d\n", 410 ref); 411 return EINVAL; 412 } 413 /* Start with template. */ 414 memcpy(eep, def, sc->sc_eep_size); 415 /* Shadow template with chunks. */ 416 off = 0; /* Offset in ROM image. */ 417 ptr = buf; /* Offset in block. */ 418 end = buf + len; 419 /* Process chunks. */ 420 while (ptr + 2 <= end) { 421 off += *ptr++; /* Gap with previous chunk. */ 422 clen = *ptr++; /* Chunk length. */ 423 /* Make sure block is large enough. */ 424 if (ptr + clen > end) 425 return EINVAL; 426 /* Make sure chunk fits in ROM image. */ 427 if (off + clen > sc->sc_eep_size) 428 return EINVAL; 429 /* Restore chunk. */ 430 DPRINTFN(DBG_INIT, sc, "ROM chunk @%zd/%zd\n", 431 off, clen); 432 memcpy(&eep[off], ptr, clen); 433 ptr += clen; 434 off += clen; 435 } 436 } 437 else if (alg == AR_EEP_COMPRESS_NONE) { 438 /* Block contains full ROM image. */ 439 if (len != sc->sc_eep_size) { 440 DPRINTFN(DBG_INIT, sc, "block length mismatch %zd\n", 441 len); 442 return EINVAL; 443 } 444 memcpy(eep, buf, len); 445 } 446 return 0; 447 } 448 449 Static int 450 ar9003_read_rom(struct athn_softc *sc) 451 { 452 struct athn_ops *ops = &sc->sc_ops; 453 uint8_t *buf, *ptr, alg, ref; 454 uint16_t sum, rsum; 455 uint32_t hdr; 456 int error, addr; 457 size_t len, i, j; 458 459 /* Allocate space to store ROM in host memory. */ 460 sc->sc_eep = malloc(sc->sc_eep_size, M_DEVBUF, M_WAITOK); 461 462 /* Allocate temporary buffer to store ROM blocks. */ 463 buf = malloc(2048, M_DEVBUF, M_WAITOK); 464 465 /* Restore vendor-specified ROM blocks. */ 466 addr = sc->sc_eep_base; 467 for (i = 0; i < 100; i++) { 468 /* Read block header. */ 469 error = ops->read_rom_data(sc, addr, &hdr, sizeof(hdr)); 470 if (error != 0) 471 break; 472 if (hdr == 0 || hdr == 0xffffffff) 473 break; 474 addr -= sizeof(hdr); 475 476 /* Extract bits from header. */ 477 ptr = (uint8_t *)&hdr; 478 alg = (ptr[0] & 0xe0) >> 5; 479 ref = (ptr[1] & 0x80) >> 2 | (ptr[0] & 0x1f); 480 len = (ptr[1] & 0x7f) << 4 | (ptr[2] & 0xf0) >> 4; 481 DPRINTFN(DBG_INIT, sc, 482 "ROM block %zd: alg=%d ref=%d len=%zd\n", 483 i, alg, ref, len); 484 485 /* Read block data (len <= 0x7ff). */ 486 error = ops->read_rom_data(sc, addr, buf, len); 487 if (error != 0) 488 break; 489 addr -= len; 490 491 /* Read block checksum. */ 492 error = ops->read_rom_data(sc, addr, &sum, sizeof(sum)); 493 if (error != 0) 494 break; 495 addr -= sizeof(sum); 496 497 /* Compute block checksum. */ 498 rsum = 0; 499 for (j = 0; j < len; j++) 500 rsum += buf[j]; 501 /* Compare to that in ROM. */ 502 if (le16toh(sum) != rsum) { 503 DPRINTFN(DBG_INIT, sc, 504 "bad block checksum 0x%x/0x%x\n", 505 le16toh(sum), rsum); 506 continue; /* Skip bad block. */ 507 } 508 /* Checksum is correct, restore block. */ 509 ar9003_restore_rom_block(sc, alg, ref, buf, len); 510 } 511 #if BYTE_ORDER == BIG_ENDIAN 512 /* NB: ROM is always little endian. */ 513 if (error == 0) 514 ops->swap_rom(sc); 515 #endif 516 free(buf, M_DEVBUF); 517 return error; 518 } 519 520 /* 521 * Access to General Purpose Input/Output ports. 522 */ 523 Static int 524 ar9003_gpio_read(struct athn_softc *sc, int pin) 525 { 526 527 KASSERT(pin < sc->sc_ngpiopins); 528 return ((AR_READ(sc, AR_GPIO_IN) & AR9300_GPIO_IN_VAL) & 529 (1 << pin)) != 0; 530 } 531 532 Static void 533 ar9003_gpio_write(struct athn_softc *sc, int pin, int set) 534 { 535 uint32_t reg; 536 537 KASSERT(pin < sc->sc_ngpiopins); 538 reg = AR_READ(sc, AR_GPIO_IN_OUT); 539 if (set) 540 reg |= 1 << pin; 541 else 542 reg &= ~(1 << pin); 543 AR_WRITE(sc, AR_GPIO_IN_OUT, reg); 544 AR_WRITE_BARRIER(sc); 545 } 546 547 Static void 548 ar9003_gpio_config_input(struct athn_softc *sc, int pin) 549 { 550 uint32_t reg; 551 552 reg = AR_READ(sc, AR_GPIO_OE_OUT); 553 reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); 554 reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2); 555 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); 556 AR_WRITE_BARRIER(sc); 557 } 558 559 Static void 560 ar9003_gpio_config_output(struct athn_softc *sc, int pin, int type) 561 { 562 uint32_t reg; 563 int mux, off; 564 565 mux = pin / 6; 566 off = pin % 6; 567 568 reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux)); 569 reg &= ~(0x1f << (off * 5)); 570 reg |= (type & 0x1f) << (off * 5); 571 AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg); 572 573 reg = AR_READ(sc, AR_GPIO_OE_OUT); 574 reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2)); 575 reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2); 576 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); 577 AR_WRITE_BARRIER(sc); 578 } 579 580 Static void 581 ar9003_rfsilent_init(struct athn_softc *sc) 582 { 583 uint32_t reg; 584 585 /* Configure hardware radio switch. */ 586 AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 587 reg = AR_READ(sc, AR_GPIO_INPUT_MUX2); 588 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); 589 AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg); 590 ar9003_gpio_config_input(sc, sc->sc_rfsilent_pin); 591 AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB); 592 if (!(sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED)) { 593 AR_SETBITS(sc, AR_GPIO_INTR_POL, 594 AR_GPIO_INTR_POL_PIN(sc->sc_rfsilent_pin)); 595 } 596 AR_WRITE_BARRIER(sc); 597 } 598 599 Static int 600 ar9003_dma_alloc(struct athn_softc *sc) 601 { 602 int error; 603 604 error = ar9003_tx_alloc(sc); 605 if (error != 0) 606 return error; 607 608 error = ar9003_rx_alloc(sc, ATHN_QID_LP, AR9003_RX_LP_QDEPTH); 609 if (error != 0) 610 return error; 611 612 error = ar9003_rx_alloc(sc, ATHN_QID_HP, AR9003_RX_HP_QDEPTH); 613 if (error != 0) 614 return error; 615 616 return 0; 617 } 618 619 Static void 620 ar9003_dma_free(struct athn_softc *sc) 621 { 622 623 ar9003_tx_free(sc); 624 ar9003_rx_free(sc, ATHN_QID_LP); 625 ar9003_rx_free(sc, ATHN_QID_HP); 626 } 627 628 Static int 629 ar9003_tx_alloc(struct athn_softc *sc) 630 { 631 struct athn_tx_buf *bf; 632 bus_size_t size; 633 int error, nsegs, i; 634 635 /* 636 * Allocate Tx status ring. 637 */ 638 size = AR9003_NTXSTATUS * sizeof(struct ar_tx_status); 639 640 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 641 BUS_DMA_NOWAIT, &sc->sc_txsmap); 642 if (error != 0) 643 goto fail; 644 645 error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_txsseg, 1, 646 // XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 647 &nsegs, BUS_DMA_NOWAIT); 648 if (error != 0) 649 goto fail; 650 651 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_txsseg, 1, size, 652 (void **)&sc->sc_txsring, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 653 if (error != 0) 654 goto fail; 655 656 error = bus_dmamap_load(sc->sc_dmat, sc->sc_txsmap, sc->sc_txsring, 657 size, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 658 if (error != 0) 659 goto fail; 660 661 /* 662 * Allocate a pool of Tx descriptors shared between all Tx queues. 663 */ 664 size = ATHN_NTXBUFS * sizeof(struct ar_tx_desc); 665 666 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 667 BUS_DMA_NOWAIT, &sc->sc_map); 668 if (error != 0) 669 goto fail; 670 671 error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->sc_seg, 1, 672 // XXX &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 673 &nsegs, BUS_DMA_NOWAIT); 674 if (error != 0) 675 goto fail; 676 677 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, 1, size, 678 (void **)&sc->sc_descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 679 if (error != 0) 680 goto fail; 681 682 error = bus_dmamap_load(sc->sc_dmat, sc->sc_map, sc->sc_descs, size, 683 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 684 if (error != 0) 685 goto fail; 686 687 SIMPLEQ_INIT(&sc->sc_txbufs); 688 for (i = 0; i < ATHN_NTXBUFS; i++) { 689 bf = &sc->sc_txpool[i]; 690 691 error = bus_dmamap_create(sc->sc_dmat, ATHN_TXBUFSZ, 692 AR9003_MAX_SCATTER, ATHN_TXBUFSZ, 0, BUS_DMA_NOWAIT, 693 &bf->bf_map); 694 if (error != 0) { 695 aprint_error_dev(sc->sc_dev, 696 "could not create Tx buf DMA map\n"); 697 goto fail; 698 } 699 700 bf->bf_descs = &((struct ar_tx_desc *)sc->sc_descs)[i]; 701 bf->bf_daddr = sc->sc_map->dm_segs[0].ds_addr + 702 i * sizeof(struct ar_tx_desc); 703 704 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 705 } 706 return 0; 707 fail: 708 ar9003_tx_free(sc); 709 return error; 710 } 711 712 Static void 713 ar9003_tx_free(struct athn_softc *sc) 714 { 715 struct athn_tx_buf *bf; 716 int i; 717 718 for (i = 0; i < ATHN_NTXBUFS; i++) { 719 bf = &sc->sc_txpool[i]; 720 721 if (bf->bf_map != NULL) 722 bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); 723 } 724 /* Free Tx descriptors. */ 725 if (sc->sc_map != NULL) { 726 if (sc->sc_descs != NULL) { 727 bus_dmamap_unload(sc->sc_dmat, sc->sc_map); 728 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs, 729 ATHN_NTXBUFS * sizeof(struct ar_tx_desc)); 730 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 731 } 732 bus_dmamap_destroy(sc->sc_dmat, sc->sc_map); 733 } 734 /* Free Tx status ring. */ 735 if (sc->sc_txsmap != NULL) { 736 if (sc->sc_txsring != NULL) { 737 bus_dmamap_unload(sc->sc_dmat, sc->sc_txsmap); 738 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_txsring, 739 AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); 740 bus_dmamem_free(sc->sc_dmat, &sc->sc_txsseg, 1); 741 } 742 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsmap); 743 } 744 } 745 746 Static int 747 ar9003_rx_alloc(struct athn_softc *sc, int qid, int count) 748 { 749 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 750 struct athn_rx_buf *bf; 751 struct ar_rx_status *ds; 752 int error, i; 753 754 rxq->bf = malloc(count * sizeof(*bf), M_DEVBUF, M_WAITOK | M_ZERO); 755 rxq->count = count; 756 757 for (i = 0; i < rxq->count; i++) { 758 bf = &rxq->bf[i]; 759 760 error = bus_dmamap_create(sc->sc_dmat, ATHN_RXBUFSZ, 1, 761 ATHN_RXBUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 762 &bf->bf_map); 763 if (error != 0) { 764 aprint_error_dev(sc->sc_dev, 765 "could not create Rx buf DMA map\n"); 766 goto fail; 767 } 768 /* 769 * Assumes MCLGETI returns cache-line-size aligned buffers. 770 */ 771 bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); 772 if (bf->bf_m == NULL) { 773 aprint_error_dev(sc->sc_dev, 774 "could not allocate Rx mbuf\n"); 775 error = ENOBUFS; 776 goto fail; 777 } 778 779 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, 780 mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, 781 BUS_DMA_NOWAIT); 782 if (error != 0) { 783 aprint_error_dev(sc->sc_dev, 784 "could not DMA map Rx buffer\n"); 785 goto fail; 786 } 787 788 ds = mtod(bf->bf_m, struct ar_rx_status *); 789 memset(ds, 0, sizeof(*ds)); 790 bf->bf_desc = ds; 791 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 792 793 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 794 BUS_DMASYNC_PREREAD); 795 } 796 return 0; 797 fail: 798 ar9003_rx_free(sc, qid); 799 return error; 800 } 801 802 Static void 803 ar9003_rx_free(struct athn_softc *sc, int qid) 804 { 805 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 806 struct athn_rx_buf *bf; 807 int i; 808 809 if (rxq->bf == NULL) 810 return; 811 for (i = 0; i < rxq->count; i++) { 812 bf = &rxq->bf[i]; 813 814 if (bf->bf_map != NULL) 815 bus_dmamap_destroy(sc->sc_dmat, bf->bf_map); 816 m_freem(bf->bf_m); 817 } 818 free(rxq->bf, M_DEVBUF); 819 } 820 821 PUBLIC void 822 ar9003_reset_txsring(struct athn_softc *sc) 823 { 824 825 sc->sc_txscur = 0; 826 memset(sc->sc_txsring, 0, AR9003_NTXSTATUS * sizeof(struct ar_tx_status)); 827 AR_WRITE(sc, AR_Q_STATUS_RING_START, 828 sc->sc_txsmap->dm_segs[0].ds_addr); 829 AR_WRITE(sc, AR_Q_STATUS_RING_END, 830 sc->sc_txsmap->dm_segs[0].ds_addr + sc->sc_txsmap->dm_segs[0].ds_len); 831 AR_WRITE_BARRIER(sc); 832 } 833 834 Static void 835 ar9003_rx_enable(struct athn_softc *sc) 836 { 837 struct athn_rxq *rxq; 838 struct athn_rx_buf *bf; 839 struct ar_rx_status *ds; 840 uint32_t reg; 841 int qid, i; 842 843 reg = AR_READ(sc, AR_RXBP_THRESH); 844 reg = RW(reg, AR_RXBP_THRESH_HP, 1); 845 reg = RW(reg, AR_RXBP_THRESH_LP, 1); 846 AR_WRITE(sc, AR_RXBP_THRESH, reg); 847 848 /* Set Rx buffer size. */ 849 AR_WRITE(sc, AR_DATABUF_SIZE, ATHN_RXBUFSZ - sizeof(*ds)); 850 851 for (qid = 0; qid < 2; qid++) { 852 rxq = &sc->sc_rxq[qid]; 853 854 /* Setup Rx status descriptors. */ 855 SIMPLEQ_INIT(&rxq->head); 856 for (i = 0; i < rxq->count; i++) { 857 bf = &rxq->bf[i]; 858 ds = bf->bf_desc; 859 860 memset(ds, 0, sizeof(*ds)); 861 if (qid == ATHN_QID_LP) 862 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); 863 else 864 AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); 865 AR_WRITE_BARRIER(sc); 866 SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); 867 } 868 } 869 /* Enable Rx. */ 870 AR_WRITE(sc, AR_CR, 0); 871 AR_WRITE_BARRIER(sc); 872 } 873 874 Static void 875 ar9003_rx_radiotap(struct athn_softc *sc, struct mbuf *m, 876 struct ar_rx_status *ds) 877 { 878 struct athn_rx_radiotap_header *tap = &sc->sc_rxtap; 879 struct ieee80211com *ic = &sc->sc_ic; 880 uint64_t tsf; 881 uint32_t tstamp; 882 uint8_t rate; 883 884 /* Extend the 15-bit timestamp from Rx status to 64-bit TSF. */ 885 tstamp = ds->ds_status3; 886 tsf = AR_READ(sc, AR_TSF_U32); 887 tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32); 888 if ((tsf & 0x7fff) < tstamp) 889 tsf -= 0x8000; 890 tsf = (tsf & ~0x7fff) | tstamp; 891 892 tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 893 tap->wr_tsft = htole64(tsf); 894 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 895 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 896 tap->wr_dbm_antsignal = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); 897 /* XXX noise. */ 898 tap->wr_antenna = MS(ds->ds_status4, AR_RXS4_ANTENNA); 899 tap->wr_rate = 0; /* In case it can't be found below. */ 900 rate = MS(ds->ds_status1, AR_RXS1_RATE); 901 if (rate & 0x80) { /* HT. */ 902 /* Bit 7 set means HT MCS instead of rate. */ 903 tap->wr_rate = rate; 904 if (!(ds->ds_status4 & AR_RXS4_GI)) 905 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 906 907 } 908 else if (rate & 0x10) { /* CCK. */ 909 if (rate & 0x04) 910 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 911 switch (rate & ~0x14) { 912 case 0xb: tap->wr_rate = 2; break; 913 case 0xa: tap->wr_rate = 4; break; 914 case 0x9: tap->wr_rate = 11; break; 915 case 0x8: tap->wr_rate = 22; break; 916 } 917 } 918 else { /* OFDM. */ 919 switch (rate) { 920 case 0xb: tap->wr_rate = 12; break; 921 case 0xf: tap->wr_rate = 18; break; 922 case 0xa: tap->wr_rate = 24; break; 923 case 0xe: tap->wr_rate = 36; break; 924 case 0x9: tap->wr_rate = 48; break; 925 case 0xd: tap->wr_rate = 72; break; 926 case 0x8: tap->wr_rate = 96; break; 927 case 0xc: tap->wr_rate = 108; break; 928 } 929 } 930 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 931 } 932 933 Static int 934 ar9003_rx_process(struct athn_softc *sc, int qid) 935 { 936 struct ieee80211com *ic = &sc->sc_ic; 937 struct ifnet *ifp = &sc->sc_if; 938 struct athn_rxq *rxq = &sc->sc_rxq[qid]; 939 struct athn_rx_buf *bf; 940 struct ar_rx_status *ds; 941 struct ieee80211_frame *wh; 942 struct ieee80211_node *ni; 943 struct mbuf *m, *m1; 944 size_t len; 945 u_int32_t rstamp; 946 int error, rssi, s; 947 948 bf = SIMPLEQ_FIRST(&rxq->head); 949 if (__predict_false(bf == NULL)) { /* Should not happen. */ 950 aprint_error_dev(sc->sc_dev, "Rx queue is empty!\n"); 951 return ENOENT; 952 } 953 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 954 BUS_DMASYNC_POSTREAD); 955 956 ds = mtod(bf->bf_m, struct ar_rx_status *); 957 if (!(ds->ds_status1 & AR_RXS1_DONE)) 958 return EBUSY; 959 960 /* Check that it is a valid Rx status descriptor. */ 961 if ((ds->ds_info & (AR_RXI_DESC_ID_M | AR_RXI_DESC_TX | 962 AR_RXI_CTRL_STAT)) != SM(AR_RXI_DESC_ID, AR_VENDOR_ATHEROS)) 963 goto skip; 964 965 if (!(ds->ds_status11 & AR_RXS11_FRAME_OK)) { 966 if (ds->ds_status11 & AR_RXS11_CRC_ERR) 967 DPRINTFN(DBG_RX, sc, "CRC error\n"); 968 else if (ds->ds_status11 & AR_RXS11_PHY_ERR) 969 DPRINTFN(DBG_RX, sc, "PHY error=0x%x\n", 970 MS(ds->ds_status11, AR_RXS11_PHY_ERR_CODE)); 971 else if (ds->ds_status11 & AR_RXS11_DECRYPT_CRC_ERR) 972 DPRINTFN(DBG_RX, sc, "Decryption CRC error\n"); 973 else if (ds->ds_status11 & AR_RXS11_MICHAEL_ERR) { 974 DPRINTFN(DBG_RX, sc, "Michael MIC failure\n"); 975 /* Report Michael MIC failures to net80211. */ 976 977 len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); 978 m = bf->bf_m; 979 m_set_rcvif(m, ifp); 980 m->m_data = (void *)&ds[1]; 981 m->m_pkthdr.len = m->m_len = len; 982 wh = mtod(m, struct ieee80211_frame *); 983 984 ieee80211_notify_michael_failure(ic, wh, 985 0 /* XXX: keyix */); 986 } 987 if_statinc(ifp, if_ierrors); 988 goto skip; 989 } 990 991 len = MS(ds->ds_status2, AR_RXS2_DATA_LEN); 992 if (__predict_false(len < IEEE80211_MIN_LEN || 993 len > ATHN_RXBUFSZ - sizeof(*ds))) { 994 DPRINTFN(DBG_RX, sc, "corrupted descriptor length=%zd\n", 995 len); 996 if_statinc(ifp, if_ierrors); 997 goto skip; 998 } 999 1000 /* Allocate a new Rx buffer. */ 1001 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ); 1002 if (__predict_false(m1 == NULL)) { 1003 ic->ic_stats.is_rx_nobuf++; 1004 if_statinc(ifp, if_ierrors); 1005 goto skip; 1006 } 1007 1008 /* Unmap the old Rx buffer. */ 1009 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1010 1011 /* Map the new Rx buffer. */ 1012 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, mtod(m1, void *), 1013 ATHN_RXBUFSZ, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1014 if (__predict_false(error != 0)) { 1015 m_freem(m1); 1016 1017 /* Remap the old Rx buffer or panic. */ 1018 error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, 1019 mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL, 1020 BUS_DMA_NOWAIT | BUS_DMA_READ); 1021 KASSERT(error != 0); 1022 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 1023 if_statinc(ifp, if_ierrors); 1024 goto skip; 1025 } 1026 bf->bf_desc = mtod(m1, struct ar_rx_status *); 1027 bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr; 1028 1029 m = bf->bf_m; 1030 bf->bf_m = m1; 1031 1032 /* Finalize mbuf. */ 1033 m_set_rcvif(m, ifp); 1034 /* Strip Rx status descriptor from head. */ 1035 m->m_data = (void *)&ds[1]; 1036 m->m_pkthdr.len = m->m_len = len; 1037 1038 s = splnet(); 1039 1040 /* Grab a reference to the source node. */ 1041 wh = mtod(m, struct ieee80211_frame *); 1042 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1043 1044 /* Remove any HW padding after the 802.11 header. */ 1045 if (!(wh->i_fc[0] & IEEE80211_FC0_TYPE_CTL)) { 1046 u_int hdrlen = ieee80211_anyhdrsize(wh); 1047 if (hdrlen & 3) { 1048 memmove((uint8_t *)wh + 2, wh, hdrlen); 1049 m_adj(m, 2); 1050 } 1051 } 1052 if (__predict_false(sc->sc_drvbpf != NULL)) 1053 ar9003_rx_radiotap(sc, m, ds); 1054 /* Trim 802.11 FCS after radiotap. */ 1055 m_adj(m, -IEEE80211_CRC_LEN); 1056 1057 /* Send the frame to the 802.11 layer. */ 1058 rssi = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED); 1059 rstamp = ds->ds_status3; 1060 ieee80211_input(ic, m, ni, rssi, rstamp); 1061 1062 /* Node is no longer needed. */ 1063 ieee80211_free_node(ni); 1064 1065 splx(s); 1066 1067 skip: 1068 /* Unlink this descriptor from head. */ 1069 SIMPLEQ_REMOVE_HEAD(&rxq->head, bf_list); 1070 memset(bf->bf_desc, 0, sizeof(*ds)); 1071 1072 /* Re-use this descriptor and link it to tail. */ 1073 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ, 1074 BUS_DMASYNC_PREREAD); 1075 1076 if (qid == ATHN_QID_LP) 1077 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); 1078 else 1079 AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr); 1080 AR_WRITE_BARRIER(sc); 1081 SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list); 1082 1083 /* Re-enable Rx. */ 1084 AR_WRITE(sc, AR_CR, 0); 1085 AR_WRITE_BARRIER(sc); 1086 return 0; 1087 } 1088 1089 Static void 1090 ar9003_rx_intr(struct athn_softc *sc, int qid) 1091 { 1092 1093 while (ar9003_rx_process(sc, qid) == 0) 1094 continue; 1095 } 1096 1097 Static int 1098 ar9003_tx_process(struct athn_softc *sc) 1099 { 1100 struct ifnet *ifp = &sc->sc_if; 1101 struct athn_txq *txq; 1102 struct athn_node *an; 1103 struct athn_tx_buf *bf; 1104 struct ar_tx_status *ds; 1105 uint8_t qid, failcnt; 1106 1107 ds = &((struct ar_tx_status *)sc->sc_txsring)[sc->sc_txscur]; 1108 if (!(ds->ds_status8 & AR_TXS8_DONE)) 1109 return EBUSY; 1110 1111 sc->sc_txscur = (sc->sc_txscur + 1) % AR9003_NTXSTATUS; 1112 1113 /* Check that it is a valid Tx status descriptor. */ 1114 if ((ds->ds_info & (AR_TXI_DESC_ID_M | AR_TXI_DESC_TX)) != 1115 (SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | AR_TXI_DESC_TX)) { 1116 memset(ds, 0, sizeof(*ds)); 1117 return 0; 1118 } 1119 /* Retrieve the queue that was used to send this PDU. */ 1120 qid = MS(ds->ds_info, AR_TXI_QCU_NUM); 1121 txq = &sc->sc_txq[qid]; 1122 1123 bf = SIMPLEQ_FIRST(&txq->head); 1124 if (bf == NULL || bf == txq->wait) { 1125 memset(ds, 0, sizeof(*ds)); 1126 return 0; 1127 } 1128 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1129 if_statinc(ifp, if_opackets); 1130 1131 sc->sc_tx_timer = 0; 1132 1133 if (ds->ds_status3 & AR_TXS3_EXCESSIVE_RETRIES) 1134 if_statinc(ifp, if_oerrors); 1135 1136 if (ds->ds_status3 & AR_TXS3_UNDERRUN) 1137 athn_inc_tx_trigger_level(sc); 1138 1139 /* Wakeup PA predistortion state machine. */ 1140 if (bf->bf_txflags & ATHN_TXFLAG_PAPRD) 1141 ar9003_paprd_tx_tone_done(sc); 1142 1143 an = (struct athn_node *)bf->bf_ni; 1144 /* 1145 * NB: the data fail count contains the number of un-acked tries 1146 * for the final series used. We must add the number of tries for 1147 * each series that was fully processed. 1148 */ 1149 failcnt = MS(ds->ds_status3, AR_TXS3_DATA_FAIL_CNT); 1150 /* NB: Assume two tries per series. */ 1151 failcnt += MS(ds->ds_status8, AR_TXS8_FINAL_IDX) * 2; 1152 1153 /* Update rate control statistics. */ 1154 an->amn.amn_txcnt++; 1155 if (failcnt > 0) 1156 an->amn.amn_retrycnt++; 1157 1158 DPRINTFN(DBG_TX, sc, "Tx done qid=%d status3=%d fail count=%d\n", 1159 qid, ds->ds_status3, failcnt); 1160 1161 /* Reset Tx status descriptor. */ 1162 memset(ds, 0, sizeof(*ds)); 1163 1164 /* Unmap Tx buffer. */ 1165 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1166 BUS_DMASYNC_POSTWRITE); 1167 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1168 1169 m_freem(bf->bf_m); 1170 bf->bf_m = NULL; 1171 ieee80211_free_node(bf->bf_ni); 1172 bf->bf_ni = NULL; 1173 1174 /* Link Tx buffer back to global free list. */ 1175 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1176 1177 /* Queue buffers that are waiting if there is new room. */ 1178 if (--txq->queued < AR9003_TX_QDEPTH && txq->wait != NULL) { 1179 AR_WRITE(sc, AR_QTXDP(qid), txq->wait->bf_daddr); 1180 AR_WRITE_BARRIER(sc); 1181 txq->wait = SIMPLEQ_NEXT(txq->wait, bf_list); 1182 } 1183 return 0; 1184 } 1185 1186 Static void 1187 ar9003_tx_intr(struct athn_softc *sc) 1188 { 1189 struct ifnet *ifp = &sc->sc_if; 1190 int s; 1191 1192 s = splnet(); 1193 1194 while (ar9003_tx_process(sc) == 0) 1195 continue; 1196 1197 if (!SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 1198 ifp->if_flags &= ~IFF_OACTIVE; 1199 ifp->if_start(ifp); /* in softint */ 1200 } 1201 1202 splx(s); 1203 } 1204 1205 #ifndef IEEE80211_STA_ONLY 1206 /* 1207 * Process Software Beacon Alert interrupts. 1208 */ 1209 Static int 1210 ar9003_swba_intr(struct athn_softc *sc) 1211 { 1212 struct ieee80211com *ic = &sc->sc_ic; 1213 struct ifnet *ifp = &sc->sc_if; 1214 struct ieee80211_node *ni = ic->ic_bss; 1215 struct athn_tx_buf *bf = sc->sc_bcnbuf; 1216 struct ieee80211_frame *wh; 1217 struct ieee80211_beacon_offsets bo; 1218 struct ar_tx_desc *ds; 1219 struct mbuf *m; 1220 uint32_t sum; 1221 uint8_t ridx, hwrate; 1222 int error, totlen; 1223 1224 #if notyet 1225 if (ic->ic_tim_mcast_pending && 1226 IF_IS_EMPTY(&ni->ni_savedq) && 1227 SIMPLEQ_EMPTY(&sc->sc_txq[ATHN_QID_CAB].head)) 1228 ic->ic_tim_mcast_pending = 0; 1229 #endif 1230 if (ic->ic_dtim_count == 0) 1231 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1232 else 1233 ic->ic_dtim_count--; 1234 1235 /* Make sure previous beacon has been sent. */ 1236 if (athn_tx_pending(sc, ATHN_QID_BEACON)) { 1237 DPRINTFN(DBG_INTR, sc, "beacon stuck\n"); 1238 return EBUSY; 1239 } 1240 /* Get new beacon. */ 1241 m = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 1242 if (__predict_false(m == NULL)) 1243 return ENOBUFS; 1244 /* Assign sequence number. */ 1245 /* XXX: use non-QoS tid? */ 1246 wh = mtod(m, struct ieee80211_frame *); 1247 *(uint16_t *)&wh->i_seq[0] = 1248 htole16(ic->ic_bss->ni_txseqs[0] << IEEE80211_SEQ_SEQ_SHIFT); 1249 ic->ic_bss->ni_txseqs[0]++; 1250 1251 /* Unmap and free old beacon if any. */ 1252 if (__predict_true(bf->bf_m != NULL)) { 1253 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1254 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1255 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1256 m_freem(bf->bf_m); 1257 bf->bf_m = NULL; 1258 } 1259 /* DMA map new beacon. */ 1260 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1261 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1262 if (__predict_false(error != 0)) { 1263 m_freem(m); 1264 return error; 1265 } 1266 bf->bf_m = m; 1267 1268 /* Setup Tx descriptor (simplified ar9003_tx()). */ 1269 ds = bf->bf_descs; 1270 memset(ds, 0, sizeof(*ds)); 1271 1272 ds->ds_info = 1273 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | 1274 SM(AR_TXI_DESC_NDWORDS, 23) | 1275 SM(AR_TXI_QCU_NUM, ATHN_QID_BEACON) | 1276 AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; 1277 1278 totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1279 ds->ds_ctl11 = SM(AR_TXC11_FRAME_LEN, totlen); 1280 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, AR_MAX_RATE_POWER); 1281 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, AR_FRAME_TYPE_BEACON); 1282 ds->ds_ctl12 |= AR_TXC12_NO_ACK; 1283 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, AR_ENCR_TYPE_CLEAR); 1284 1285 /* Write number of tries. */ 1286 ds->ds_ctl13 = SM(AR_TXC13_XMIT_DATA_TRIES0, 1); 1287 1288 /* Write Tx rate. */ 1289 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1290 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; 1291 hwrate = athn_rates[ridx].hwrate; 1292 ds->ds_ctl14 = SM(AR_TXC14_XMIT_RATE0, hwrate); 1293 1294 /* Write Tx chains. */ 1295 ds->ds_ctl18 = SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask); 1296 1297 ds->ds_segs[0].ds_data = bf->bf_map->dm_segs[0].ds_addr; 1298 /* Segment length must be a multiple of 4. */ 1299 ds->ds_segs[0].ds_ctl |= SM(AR_TXC_BUF_LEN, 1300 (bf->bf_map->dm_segs[0].ds_len + 3) & ~3); 1301 /* Compute Tx descriptor checksum. */ 1302 sum = ds->ds_info; 1303 sum += ds->ds_segs[0].ds_data; 1304 sum += ds->ds_segs[0].ds_ctl; 1305 sum = (sum >> 16) + (sum & 0xffff); 1306 ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); 1307 1308 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1309 BUS_DMASYNC_PREWRITE); 1310 1311 /* Stop Tx DMA before putting the new beacon on the queue. */ 1312 athn_stop_tx_dma(sc, ATHN_QID_BEACON); 1313 1314 AR_WRITE(sc, AR_QTXDP(ATHN_QID_BEACON), bf->bf_daddr); 1315 1316 for(;;) { 1317 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) 1318 break; 1319 1320 IF_DEQUEUE(&ni->ni_savedq, m); 1321 if (m == NULL) 1322 break; 1323 if (!IF_IS_EMPTY(&ni->ni_savedq)) { 1324 /* more queued frames, set the more data bit */ 1325 wh = mtod(m, struct ieee80211_frame *); 1326 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 1327 } 1328 1329 if (sc->sc_ops.tx(sc, m, ni, ATHN_TXFLAG_CAB) != 0) { 1330 ieee80211_free_node(ni); 1331 if_statinc(ifp, if_oerrors); 1332 break; 1333 } 1334 } 1335 1336 /* Kick Tx. */ 1337 AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON); 1338 AR_WRITE_BARRIER(sc); 1339 return 0; 1340 } 1341 #endif 1342 1343 static int 1344 ar9003_get_intr_status(struct athn_softc *sc, uint32_t *intrp, uint32_t *syncp) 1345 { 1346 uint32_t intr, sync; 1347 1348 /* Get pending interrupts. */ 1349 intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE); 1350 if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) { 1351 intr = AR_READ(sc, AR_INTR_SYNC_CAUSE); 1352 if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0) 1353 return 0; /* Not for us. */ 1354 } 1355 1356 if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && 1357 (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) 1358 intr = AR_READ(sc, AR_ISR); 1359 else 1360 intr = 0; 1361 sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync; 1362 if (intr == 0 && sync == 0) 1363 return 0; /* Not for us. */ 1364 1365 *intrp = intr; 1366 *syncp = sync; 1367 return 1; 1368 } 1369 1370 Static int 1371 ar9003_intr_status(struct athn_softc *sc) 1372 { 1373 uint32_t intr, sync; 1374 1375 return ar9003_get_intr_status(sc, &intr, &sync); 1376 } 1377 1378 Static int 1379 ar9003_intr(struct athn_softc *sc) 1380 { 1381 uint32_t intr, sync; 1382 #ifndef IEEE80211_STA_ONLY 1383 int s; 1384 #endif 1385 1386 if (!ar9003_get_intr_status(sc, &intr, &sync)) 1387 return 0; 1388 1389 if (intr != 0) { 1390 if (intr & AR_ISR_BCNMISC) { 1391 uint32_t intr2 = AR_READ(sc, AR_ISR_S2); 1392 #ifdef notyet 1393 if (intr2 & AR_ISR_S2_TIM) 1394 /* TBD */; 1395 if (intr2 & AR_ISR_S2_TSFOOR) 1396 /* TBD */; 1397 if (intr2 & AR_ISR_S2_BB_WATCHDOG) 1398 /* TBD */; 1399 #else 1400 __USE(intr2); 1401 #endif 1402 } 1403 intr = AR_READ(sc, AR_ISR_RAC); 1404 if (intr == AR_INTR_SPURIOUS) 1405 return 1; 1406 1407 #ifndef IEEE80211_STA_ONLY 1408 if (intr & AR_ISR_SWBA) { 1409 s = splnet(); 1410 ar9003_swba_intr(sc); 1411 splx(s); 1412 } 1413 #endif 1414 if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 1415 ar9003_rx_intr(sc, ATHN_QID_LP); 1416 if (intr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) 1417 ar9003_rx_intr(sc, ATHN_QID_LP); 1418 if (intr & AR_ISR_HP_RXOK) 1419 ar9003_rx_intr(sc, ATHN_QID_HP); 1420 1421 if (intr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 1422 ar9003_tx_intr(sc); 1423 if (intr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) 1424 ar9003_tx_intr(sc); 1425 1426 if (intr & AR_ISR_GENTMR) { 1427 uint32_t intr5 = AR_READ(sc, AR_ISR_S5_S); 1428 #ifdef ATHN_DEBUG 1429 DPRINTFN(DBG_INTR, sc, 1430 "GENTMR trigger=%d thresh=%d\n", 1431 MS(intr5, AR_ISR_S5_GENTIMER_TRIG), 1432 MS(intr5, AR_ISR_S5_GENTIMER_THRESH)); 1433 #else 1434 __USE(intr5); 1435 #endif 1436 } 1437 } 1438 if (sync != 0) { 1439 if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 1440 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF); 1441 AR_WRITE(sc, AR_RC, 0); 1442 } 1443 1444 if ((sc->sc_flags & ATHN_FLAG_RFSILENT) && 1445 (sync & AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin))) { 1446 pmf_event_inject(sc->sc_dev, PMFE_RADIO_OFF); 1447 return 1; 1448 } 1449 1450 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync); 1451 (void)AR_READ(sc, AR_INTR_SYNC_CAUSE); 1452 } 1453 return 1; 1454 } 1455 1456 Static int 1457 ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 1458 int txflags) 1459 { 1460 struct ieee80211com *ic = &sc->sc_ic; 1461 struct ieee80211_key *k = NULL; 1462 struct ieee80211_frame *wh; 1463 struct athn_series series[4]; 1464 struct ar_tx_desc *ds; 1465 struct athn_txq *txq; 1466 struct athn_tx_buf *bf; 1467 struct athn_node *an = (void *)ni; 1468 struct mbuf *m1; 1469 uint32_t sum; 1470 uint16_t qos; 1471 uint8_t txpower, type, encrtype, ridx[4]; 1472 int i, error, totlen, hasqos, qid; 1473 1474 /* Grab a Tx buffer from our global free list. */ 1475 bf = SIMPLEQ_FIRST(&sc->sc_txbufs); 1476 KASSERT(bf != NULL); 1477 1478 /* Map 802.11 frame type to hardware frame type. */ 1479 wh = mtod(m, struct ieee80211_frame *); 1480 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1481 IEEE80211_FC0_TYPE_MGT) { 1482 /* NB: Beacons do not use ar9003_tx(). */ 1483 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1484 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1485 type = AR_FRAME_TYPE_PROBE_RESP; 1486 else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1487 IEEE80211_FC0_SUBTYPE_ATIM) 1488 type = AR_FRAME_TYPE_ATIM; 1489 else 1490 type = AR_FRAME_TYPE_NORMAL; 1491 } 1492 else if ((wh->i_fc[0] & 1493 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1494 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_PS_POLL)) { 1495 type = AR_FRAME_TYPE_PSPOLL; 1496 } 1497 else 1498 type = AR_FRAME_TYPE_NORMAL; 1499 1500 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1501 k = ieee80211_crypto_encap(ic, ni, m); 1502 if (k == NULL) 1503 return ENOBUFS; 1504 1505 /* packet header may have moved, reset our local pointer */ 1506 wh = mtod(m, struct ieee80211_frame *); 1507 } 1508 1509 /* XXX 2-byte padding for QoS and 4-addr headers. */ 1510 1511 /* Select the HW Tx queue to use for this frame. */ 1512 if ((hasqos = ieee80211_has_qos(wh))) { 1513 #ifdef notyet_edca 1514 uint8_t tid; 1515 1516 qos = ieee80211_get_qos(wh); 1517 tid = qos & IEEE80211_QOS_TID; 1518 qid = athn_ac2qid[ieee80211_up_to_ac(ic, tid)]; 1519 #else 1520 qos = ieee80211_get_qos(wh); 1521 qid = ATHN_QID_AC_BE; 1522 #endif /* notyet_edca */ 1523 } 1524 else if (type == AR_FRAME_TYPE_PSPOLL) { 1525 qos = 0; 1526 qid = ATHN_QID_PSPOLL; 1527 } 1528 else if (txflags & ATHN_TXFLAG_CAB) { 1529 qos = 0; 1530 qid = ATHN_QID_CAB; 1531 } 1532 else { 1533 qos = 0; 1534 qid = ATHN_QID_AC_BE; 1535 } 1536 txq = &sc->sc_txq[qid]; 1537 1538 /* Select the transmit rates to use for this frame. */ 1539 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1540 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 1541 IEEE80211_FC0_TYPE_DATA) { 1542 /* Use lowest rate for all tries. */ 1543 ridx[0] = ridx[1] = ridx[2] = ridx[3] = 1544 (ic->ic_curmode == IEEE80211_MODE_11A) ? 1545 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1; 1546 } 1547 else if (ic->ic_fixed_rate != -1) { 1548 /* Use same fixed rate for all tries. */ 1549 ridx[0] = ridx[1] = ridx[2] = ridx[3] = 1550 sc->sc_fixed_ridx; 1551 } 1552 else { 1553 int txrate = ni->ni_txrate; 1554 /* Use fallback table of the node. */ 1555 for (i = 0; i < 4; i++) { 1556 ridx[i] = an->ridx[txrate]; 1557 txrate = an->fallback[txrate]; 1558 } 1559 } 1560 1561 if (__predict_false(sc->sc_drvbpf != NULL)) { 1562 struct athn_tx_radiotap_header *tap = &sc->sc_txtap; 1563 1564 tap->wt_flags = 0; 1565 /* Use initial transmit rate. */ 1566 tap->wt_rate = athn_rates[ridx[0]].rate; 1567 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1568 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1569 // XXX tap->wt_hwqueue = qid; 1570 if (ridx[0] != ATHN_RIDX_CCK1 && 1571 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1572 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1573 1574 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 1575 } 1576 1577 /* DMA map mbuf. */ 1578 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1579 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1580 if (__predict_false(error != 0)) { 1581 if (error != EFBIG) { 1582 aprint_error_dev(sc->sc_dev, 1583 "can't map mbuf (error %d)\n", error); 1584 m_freem(m); 1585 return error; 1586 } 1587 /* 1588 * DMA mapping requires too many DMA segments; linearize 1589 * mbuf in kernel virtual address space and retry. 1590 */ 1591 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1592 if (m1 == NULL) { 1593 m_freem(m); 1594 return ENOBUFS; 1595 } 1596 if (m->m_pkthdr.len > (int)MHLEN) { 1597 MCLGET(m1, M_DONTWAIT); 1598 if (!(m1->m_flags & M_EXT)) { 1599 m_freem(m); 1600 m_freem(m1); 1601 return ENOBUFS; 1602 } 1603 } 1604 m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, void *)); 1605 m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len; 1606 m_freem(m); 1607 m = m1; 1608 1609 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m, 1610 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1611 if (error != 0) { 1612 aprint_error_dev(sc->sc_dev, 1613 "can't map mbuf (error %d)\n", error); 1614 m_freem(m); 1615 return error; 1616 } 1617 } 1618 bf->bf_m = m; 1619 bf->bf_ni = ni; 1620 bf->bf_txflags = txflags; 1621 1622 wh = mtod(m, struct ieee80211_frame *); 1623 1624 totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1625 1626 /* Setup Tx descriptor. */ 1627 ds = bf->bf_descs; 1628 memset(ds, 0, sizeof(*ds)); 1629 1630 ds->ds_info = 1631 SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | 1632 SM(AR_TXI_DESC_NDWORDS, 23) | 1633 SM(AR_TXI_QCU_NUM, qid) | 1634 AR_TXI_DESC_TX | AR_TXI_CTRL_STAT; 1635 1636 ds->ds_ctl11 = AR_TXC11_CLR_DEST_MASK; 1637 txpower = AR_MAX_RATE_POWER; /* Get from per-rate registers. */ 1638 ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, txpower); 1639 1640 ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, type); 1641 1642 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1643 (hasqos && (qos & IEEE80211_QOS_ACKPOLICY_MASK) == 1644 IEEE80211_QOS_ACKPOLICY_NOACK)) 1645 ds->ds_ctl12 |= AR_TXC12_NO_ACK; 1646 1647 #if notyet 1648 if (0 && k != NULL) { 1649 uintptr_t entry; 1650 1651 /* 1652 * Map 802.11 cipher to hardware encryption type and 1653 * compute MIC+ICV overhead. 1654 */ 1655 switch (k->k_cipher) { 1656 case IEEE80211_CIPHER_WEP40: 1657 case IEEE80211_CIPHER_WEP104: 1658 encrtype = AR_ENCR_TYPE_WEP; 1659 totlen += 4; 1660 break; 1661 case IEEE80211_CIPHER_TKIP: 1662 encrtype = AR_ENCR_TYPE_TKIP; 1663 totlen += 12; 1664 break; 1665 case IEEE80211_CIPHER_CCMP: 1666 encrtype = AR_ENCR_TYPE_AES; 1667 totlen += 8; 1668 break; 1669 default: 1670 panic("unsupported cipher"); 1671 } 1672 /* 1673 * NB: The key cache entry index is stored in the key 1674 * private field when the key is installed. 1675 */ 1676 entry = (uintptr_t)k->k_priv; 1677 ds->ds_ctl12 |= SM(AR_TXC12_DEST_IDX, entry); 1678 ds->ds_ctl11 |= AR_TXC11_DEST_IDX_VALID; 1679 } 1680 else 1681 #endif 1682 encrtype = AR_ENCR_TYPE_CLEAR; 1683 ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, encrtype); 1684 1685 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 1686 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1687 /* NB: Group frames are sent using CCK in 802.11b/g. */ 1688 if (totlen > ic->ic_rtsthreshold) { 1689 ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; 1690 } 1691 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1692 athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) { 1693 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 1694 ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE; 1695 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 1696 ds->ds_ctl11 |= AR_TXC11_CTS_ENABLE; 1697 } 1698 } 1699 if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { 1700 /* Disable multi-rate retries when protection is used. */ 1701 ridx[1] = ridx[2] = ridx[3] = ridx[0]; 1702 } 1703 /* Setup multi-rate retries. */ 1704 for (i = 0; i < 4; i++) { 1705 series[i].hwrate = athn_rates[ridx[i]].hwrate; 1706 if (athn_rates[ridx[i]].phy == IEEE80211_T_DS && 1707 ridx[i] != ATHN_RIDX_CCK1 && 1708 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1709 series[i].hwrate |= 0x04; 1710 series[i].dur = 0; 1711 } 1712 if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { 1713 /* Compute duration for each series. */ 1714 for (i = 0; i < 4; i++) { 1715 series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN, 1716 athn_rates[ridx[i]].rspridx, ic->ic_flags); 1717 } 1718 } 1719 /* If this is a PA training frame, select the Tx chain to use. */ 1720 if (__predict_false(txflags & ATHN_TXFLAG_PAPRD)) { 1721 ds->ds_ctl12 |= SM(AR_TXC12_PAPRD_CHAIN_MASK, 1722 1 << sc->sc_paprd_curchain); 1723 } 1724 1725 /* Write number of tries for each series. */ 1726 ds->ds_ctl13 = 1727 SM(AR_TXC13_XMIT_DATA_TRIES0, 2) | 1728 SM(AR_TXC13_XMIT_DATA_TRIES1, 2) | 1729 SM(AR_TXC13_XMIT_DATA_TRIES2, 2) | 1730 SM(AR_TXC13_XMIT_DATA_TRIES3, 4); 1731 1732 /* Tell HW to update duration field in 802.11 header. */ 1733 if (type != AR_FRAME_TYPE_PSPOLL) 1734 ds->ds_ctl13 |= AR_TXC13_DUR_UPDATE_ENA; 1735 1736 /* Write Tx rate for each series. */ 1737 ds->ds_ctl14 = 1738 SM(AR_TXC14_XMIT_RATE0, series[0].hwrate) | 1739 SM(AR_TXC14_XMIT_RATE1, series[1].hwrate) | 1740 SM(AR_TXC14_XMIT_RATE2, series[2].hwrate) | 1741 SM(AR_TXC14_XMIT_RATE3, series[3].hwrate); 1742 1743 /* Write duration for each series. */ 1744 ds->ds_ctl15 = 1745 SM(AR_TXC15_PACKET_DUR0, series[0].dur) | 1746 SM(AR_TXC15_PACKET_DUR1, series[1].dur); 1747 ds->ds_ctl16 = 1748 SM(AR_TXC16_PACKET_DUR2, series[2].dur) | 1749 SM(AR_TXC16_PACKET_DUR3, series[3].dur); 1750 1751 if ((sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) && 1752 ic->ic_curmode == IEEE80211_MODE_11A) { 1753 /* 1754 * In order to not exceed PCIe power requirements, we only 1755 * use two Tx chains for MCS0~15 on 5GHz band on these chips. 1756 */ 1757 ds->ds_ctl18 = 1758 SM(AR_TXC18_CHAIN_SEL0, 1759 (ridx[0] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1760 SM(AR_TXC18_CHAIN_SEL1, 1761 (ridx[1] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1762 SM(AR_TXC18_CHAIN_SEL2, 1763 (ridx[2] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask) | 1764 SM(AR_TXC18_CHAIN_SEL3, 1765 (ridx[3] <= ATHN_RIDX_MCS15) ? 0x3 : sc->sc_txchainmask); 1766 } 1767 else { 1768 /* Use the same Tx chains for all tries. */ 1769 ds->ds_ctl18 = 1770 SM(AR_TXC18_CHAIN_SEL0, sc->sc_txchainmask) | 1771 SM(AR_TXC18_CHAIN_SEL1, sc->sc_txchainmask) | 1772 SM(AR_TXC18_CHAIN_SEL2, sc->sc_txchainmask) | 1773 SM(AR_TXC18_CHAIN_SEL3, sc->sc_txchainmask); 1774 } 1775 #ifdef notyet 1776 #ifndef IEEE80211_NO_HT 1777 /* Use the same short GI setting for all tries. */ 1778 if (ic->ic_flags & IEEE80211_F_SHGI) 1779 ds->ds_ctl18 |= AR_TXC18_GI0123; 1780 /* Use the same channel width for all tries. */ 1781 if (ic->ic_flags & IEEE80211_F_CBW40) 1782 ds->ds_ctl18 |= AR_TXC18_2040_0123; 1783 #endif 1784 #endif 1785 1786 if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) { 1787 uint8_t protridx, hwrate; 1788 uint16_t dur = 0; 1789 1790 /* Use the same protection mode for all tries. */ 1791 if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { 1792 ds->ds_ctl15 |= AR_TXC15_RTSCTS_QUAL01; 1793 ds->ds_ctl16 |= AR_TXC16_RTSCTS_QUAL23; 1794 } 1795 /* Select protection rate (suboptimal but ok). */ 1796 protridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1797 ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK2; 1798 if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) { 1799 /* Account for CTS duration. */ 1800 dur += athn_txtime(sc, IEEE80211_ACK_LEN, 1801 athn_rates[protridx].rspridx, ic->ic_flags); 1802 } 1803 dur += athn_txtime(sc, totlen, ridx[0], ic->ic_flags); 1804 if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) { 1805 /* Account for ACK duration. */ 1806 dur += athn_txtime(sc, IEEE80211_ACK_LEN, 1807 athn_rates[ridx[0]].rspridx, ic->ic_flags); 1808 } 1809 /* Write protection frame duration and rate. */ 1810 ds->ds_ctl13 |= SM(AR_TXC13_BURST_DUR, dur); 1811 hwrate = athn_rates[protridx].hwrate; 1812 if (protridx == ATHN_RIDX_CCK2 && 1813 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1814 hwrate |= 0x04; 1815 ds->ds_ctl18 |= SM(AR_TXC18_RTSCTS_RATE, hwrate); 1816 } 1817 1818 ds->ds_ctl11 |= SM(AR_TXC11_FRAME_LEN, totlen); 1819 ds->ds_ctl19 = AR_TXC19_NOT_SOUNDING; 1820 1821 for (i = 0; i < bf->bf_map->dm_nsegs; i++) { 1822 ds->ds_segs[i].ds_data = bf->bf_map->dm_segs[i].ds_addr; 1823 ds->ds_segs[i].ds_ctl = SM(AR_TXC_BUF_LEN, 1824 bf->bf_map->dm_segs[i].ds_len); 1825 } 1826 /* Compute Tx descriptor checksum. */ 1827 sum = ds->ds_info + ds->ds_link; 1828 for (i = 0; i < 4; i++) { 1829 sum += ds->ds_segs[i].ds_data; 1830 sum += ds->ds_segs[i].ds_ctl; 1831 } 1832 sum = (sum >> 16) + (sum & 0xffff); 1833 ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum); 1834 1835 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize, 1836 BUS_DMASYNC_PREWRITE); 1837 1838 DPRINTFN(DBG_TX, sc, 1839 "Tx qid=%d nsegs=%d ctl11=0x%x ctl12=0x%x ctl14=0x%x\n", 1840 qid, bf->bf_map->dm_nsegs, ds->ds_ctl11, ds->ds_ctl12, 1841 ds->ds_ctl14); 1842 1843 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 1844 SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list); 1845 1846 /* Queue buffer unless hardware FIFO is already full. */ 1847 if (++txq->queued <= AR9003_TX_QDEPTH) { 1848 AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr); 1849 AR_WRITE_BARRIER(sc); 1850 } 1851 else if (txq->wait == NULL) 1852 txq->wait = bf; 1853 return 0; 1854 } 1855 1856 Static void 1857 ar9003_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c) 1858 { 1859 uint32_t reg; 1860 1861 reg = IEEE80211_IS_CHAN_2GHZ(c) ? 1862 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 1863 if (IEEE80211_IS_CHAN_5GHZ(c) && 1864 (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) { 1865 reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE; 1866 } 1867 AR_WRITE(sc, AR_PHY_MODE, reg); 1868 AR_WRITE_BARRIER(sc); 1869 } 1870 1871 static __inline uint32_t 1872 ar9003_synth_delay(struct athn_softc *sc) 1873 { 1874 uint32_t synth_delay; 1875 1876 synth_delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY); 1877 if (sc->sc_ic.ic_curmode == IEEE80211_MODE_11B) 1878 synth_delay = (synth_delay * 4) / 22; 1879 else 1880 synth_delay = synth_delay / 10; /* in 100ns steps */ 1881 return synth_delay; 1882 } 1883 1884 Static int 1885 ar9003_rf_bus_request(struct athn_softc *sc) 1886 { 1887 int ntries; 1888 1889 /* Request RF Bus grant. */ 1890 AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1891 for (ntries = 0; ntries < 10000; ntries++) { 1892 if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN) 1893 return 0; 1894 DELAY(10); 1895 } 1896 DPRINTFN(DBG_RF, sc, "could not kill baseband Rx"); 1897 return ETIMEDOUT; 1898 } 1899 1900 Static void 1901 ar9003_rf_bus_release(struct athn_softc *sc) 1902 { 1903 /* Wait for the synthesizer to settle. */ 1904 DELAY(AR_BASE_PHY_ACTIVE_DELAY + ar9003_synth_delay(sc)); 1905 1906 /* Release the RF Bus grant. */ 1907 AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0); 1908 AR_WRITE_BARRIER(sc); 1909 } 1910 1911 Static void 1912 ar9003_set_phy(struct athn_softc *sc, struct ieee80211_channel *c, 1913 struct ieee80211_channel *extc) 1914 { 1915 uint32_t phy; 1916 1917 phy = AR_READ(sc, AR_PHY_GEN_CTRL); 1918 phy |= AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | 1919 AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH; 1920 #ifndef IEEE80211_NO_HT 1921 if (extc != NULL) { 1922 phy |= AR_PHY_GC_DYN2040_EN; 1923 if (extc > c) /* XXX */ 1924 phy |= AR_PHY_GC_DYN2040_PRI_CH; 1925 } 1926 #endif 1927 /* Turn off Green Field detection for now. */ 1928 phy &= ~AR_PHY_GC_GF_DETECT_EN; 1929 AR_WRITE(sc, AR_PHY_GEN_CTRL, phy); 1930 1931 AR_WRITE(sc, AR_2040_MODE, 1932 (extc != NULL) ? AR_2040_JOINED_RX_CLEAR : 0); 1933 1934 /* Set global transmit timeout. */ 1935 AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25)); 1936 /* Set carrier sense timeout. */ 1937 AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15)); 1938 AR_WRITE_BARRIER(sc); 1939 } 1940 1941 Static void 1942 ar9003_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c, 1943 struct ieee80211_channel *extc) 1944 { 1945 uint32_t coeff, exp, man, reg; 1946 1947 /* Set Delta Slope (exponent and mantissa). */ 1948 coeff = (100 << 24) / c->ic_freq; 1949 athn_get_delta_slope(coeff, &exp, &man); 1950 DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n", exp, man); 1951 1952 reg = AR_READ(sc, AR_PHY_TIMING3); 1953 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); 1954 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); 1955 AR_WRITE(sc, AR_PHY_TIMING3, reg); 1956 1957 /* For Short GI, coeff is 9/10 that of normal coeff. */ 1958 coeff = (9 * coeff) / 10; 1959 athn_get_delta_slope(coeff, &exp, &man); 1960 DPRINTFN(DBG_RF, sc, "delta slope coeff exp=%u man=%u\n", exp, man); 1961 1962 reg = AR_READ(sc, AR_PHY_SGI_DELTA); 1963 reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp); 1964 reg = RW(reg, AR_PHY_SGI_DSC_MAN, man); 1965 AR_WRITE(sc, AR_PHY_SGI_DELTA, reg); 1966 AR_WRITE_BARRIER(sc); 1967 } 1968 1969 Static void 1970 ar9003_enable_antenna_diversity(struct athn_softc *sc) 1971 { 1972 AR_SETBITS(sc, AR_PHY_CCK_DETECT, 1973 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1974 AR_WRITE_BARRIER(sc); 1975 } 1976 1977 Static void 1978 ar9003_init_baseband(struct athn_softc *sc) 1979 { 1980 uint32_t synth_delay; 1981 1982 synth_delay = ar9003_synth_delay(sc); 1983 /* Activate the PHY (includes baseband activate and synthesizer on). */ 1984 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 1985 AR_WRITE_BARRIER(sc); 1986 DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay); 1987 } 1988 1989 Static void 1990 ar9003_disable_phy(struct athn_softc *sc) 1991 { 1992 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1993 AR_WRITE_BARRIER(sc); 1994 } 1995 1996 Static void 1997 ar9003_init_chains(struct athn_softc *sc) 1998 { 1999 if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5) 2000 AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 2001 2002 /* Setup chain masks. */ 2003 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask); 2004 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask); 2005 2006 if (sc->sc_flags & ATHN_FLAG_3TREDUCE_CHAIN) { 2007 /* 2008 * All self-generated frames are sent using two Tx chains 2009 * on these chips to not exceed PCIe power requirements. 2010 */ 2011 AR_WRITE(sc, AR_SELFGEN_MASK, 0x3); 2012 } 2013 else 2014 AR_WRITE(sc, AR_SELFGEN_MASK, sc->sc_txchainmask); 2015 AR_WRITE_BARRIER(sc); 2016 } 2017 2018 Static void 2019 ar9003_set_rxchains(struct athn_softc *sc) 2020 { 2021 if (sc->sc_rxchainmask == 0x3 || sc->sc_rxchainmask == 0x5) { 2022 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask); 2023 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask); 2024 AR_WRITE_BARRIER(sc); 2025 } 2026 } 2027 2028 #ifdef notused 2029 Static void 2030 ar9003_read_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) 2031 { 2032 /* Sign-extends 9-bit value (assumes upper bits are zeroes). */ 2033 #define SIGN_EXT(v) (((v) ^ 0x100) - 0x100) 2034 uint32_t reg; 2035 int i; 2036 2037 for (i = 0; i < sc->sc_nrxchains; i++) { 2038 reg = AR_READ(sc, AR_PHY_CCA(i)); 2039 nf[i] = MS(reg, AR_PHY_MINCCA_PWR); 2040 nf[i] = SIGN_EXT(nf[i]); 2041 2042 reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); 2043 nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR); 2044 nf_ext[i] = SIGN_EXT(nf_ext[i]); 2045 } 2046 #undef SIGN_EXT 2047 } 2048 #endif /* notused */ 2049 2050 #ifdef notused 2051 Static void 2052 ar9003_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext) 2053 { 2054 uint32_t reg; 2055 int i; 2056 2057 for (i = 0; i < sc->sc_nrxchains; i++) { 2058 reg = AR_READ(sc, AR_PHY_CCA(i)); 2059 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); 2060 AR_WRITE(sc, AR_PHY_CCA(i), reg); 2061 2062 reg = AR_READ(sc, AR_PHY_EXT_CCA(i)); 2063 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); 2064 AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg); 2065 } 2066 AR_WRITE_BARRIER(sc); 2067 } 2068 #endif /* notused */ 2069 2070 #ifdef notused 2071 Static void 2072 ar9003_get_noisefloor(struct athn_softc *sc, struct ieee80211_channel *c) 2073 { 2074 int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; 2075 int16_t cca_min, cca_max; 2076 int i; 2077 2078 if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 2079 /* Noisefloor calibration not finished. */ 2080 return; 2081 } 2082 /* Noisefloor calibration is finished. */ 2083 ar9003_read_noisefloor(sc, nf, nf_ext); 2084 2085 if (IEEE80211_IS_CHAN_2GHZ(c)) { 2086 cca_min = sc->sc_cca_min_2g; 2087 cca_max = sc->sc_cca_max_2g; 2088 } 2089 else { 2090 cca_min = sc->sc_cca_min_5g; 2091 cca_max = sc->sc_cca_max_5g; 2092 } 2093 /* Update noisefloor history. */ 2094 for (i = 0; i < sc->sc_nrxchains; i++) { 2095 if (nf[i] < cca_min) 2096 nf[i] = cca_min; 2097 else if (nf[i] > cca_max) 2098 nf[i] = cca_max; 2099 if (nf_ext[i] < cca_min) 2100 nf_ext[i] = cca_min; 2101 else if (nf_ext[i] > cca_max) 2102 nf_ext[i] = cca_max; 2103 2104 sc->sc_nf_hist[sc->sc_nf_hist_cur].nf[i] = nf[i]; 2105 sc->sc_nf_hist[sc->sc_nf_hist_cur].nf_ext[i] = nf_ext[i]; 2106 } 2107 if (++sc->sc_nf_hist_cur >= ATHN_NF_CAL_HIST_MAX) 2108 sc->sc_nf_hist_cur = 0; 2109 } 2110 #endif /* notused */ 2111 2112 #ifdef notused 2113 Static void 2114 ar9003_bb_load_noisefloor(struct athn_softc *sc) 2115 { 2116 int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS]; 2117 int i, ntries; 2118 2119 /* Write filtered noisefloor values. */ 2120 for (i = 0; i < sc->sc_nrxchains; i++) { 2121 nf[i] = sc->sc_nf_priv[i] * 2; 2122 nf_ext[i] = sc->sc_nf_ext_priv[i] * 2; 2123 } 2124 ar9003_write_noisefloor(sc, nf, nf_ext); 2125 2126 /* Load filtered noisefloor values into baseband. */ 2127 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 2128 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 2129 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2130 /* Wait for load to complete. */ 2131 for (ntries = 0; ntries < 1000; ntries++) { 2132 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)) 2133 break; 2134 DELAY(10); 2135 } 2136 if (ntries == 1000) { 2137 DPRINTFN(DBG_RF, sc, "failed to load noisefloor values\n"); 2138 return; 2139 } 2140 2141 /* Restore noisefloor values to initial (max) values. */ 2142 for (i = 0; i < AR_MAX_CHAINS; i++) 2143 nf[i] = nf_ext[i] = -50 * 2; 2144 ar9003_write_noisefloor(sc, nf, nf_ext); 2145 } 2146 #endif /* notused */ 2147 2148 #ifdef notused 2149 Static void 2150 ar9300_noisefloor_calib(struct athn_softc *sc) 2151 { 2152 2153 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 2154 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 2155 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2156 } 2157 #endif /* notused */ 2158 2159 Static void 2160 ar9003_do_noisefloor_calib(struct athn_softc *sc) 2161 { 2162 2163 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 2164 } 2165 2166 PUBLIC int 2167 ar9003_init_calib(struct athn_softc *sc) 2168 { 2169 uint8_t txchainmask, rxchainmask; 2170 uint32_t reg; 2171 int ntries; 2172 2173 /* Save chains masks. */ 2174 txchainmask = sc->sc_txchainmask; 2175 rxchainmask = sc->sc_rxchainmask; 2176 /* Configure hardware before calibration. */ 2177 if (AR_READ(sc, AR_ENT_OTP) & AR_ENT_OTP_CHAIN2_DISABLE) 2178 txchainmask = rxchainmask = 0x3; 2179 else 2180 txchainmask = rxchainmask = 0x7; 2181 ar9003_init_chains(sc); 2182 2183 /* Perform Tx IQ calibration. */ 2184 ar9003_calib_tx_iq(sc); 2185 /* Disable and re-enable the PHY chips. */ 2186 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2187 AR_WRITE_BARRIER(sc); 2188 DELAY(5); 2189 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 2190 2191 /* Calibrate the AGC. */ 2192 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 2193 /* Poll for offset calibration completion. */ 2194 for (ntries = 0; ntries < 10000; ntries++) { 2195 reg = AR_READ(sc, AR_PHY_AGC_CONTROL); 2196 if (!(reg & AR_PHY_AGC_CONTROL_CAL)) 2197 break; 2198 DELAY(10); 2199 } 2200 if (ntries == 10000) 2201 return ETIMEDOUT; 2202 2203 /* Restore chains masks. */ 2204 sc->sc_txchainmask = txchainmask; 2205 sc->sc_rxchainmask = rxchainmask; 2206 ar9003_init_chains(sc); 2207 2208 return 0; 2209 } 2210 2211 Static void 2212 ar9003_do_calib(struct athn_softc *sc) 2213 { 2214 uint32_t reg; 2215 2216 if (sc->sc_cur_calib_mask & ATHN_CAL_IQ) { 2217 reg = AR_READ(sc, AR_PHY_TIMING4); 2218 reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10); 2219 AR_WRITE(sc, AR_PHY_TIMING4, reg); 2220 AR_WRITE(sc, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 2221 AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); 2222 AR_WRITE_BARRIER(sc); 2223 } 2224 else if (sc->sc_cur_calib_mask & ATHN_CAL_TEMP) { 2225 AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, 2226 AR_PHY_65NM_CH0_THERM_LOCAL); 2227 AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM, 2228 AR_PHY_65NM_CH0_THERM_START); 2229 AR_WRITE_BARRIER(sc); 2230 } 2231 } 2232 2233 Static void 2234 ar9003_next_calib(struct athn_softc *sc) 2235 { 2236 /* Check if we have any calibration in progress. */ 2237 if (sc->sc_cur_calib_mask != 0) { 2238 if (!(AR_READ(sc, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { 2239 /* Calibration completed for current sample. */ 2240 ar9003_calib_iq(sc); 2241 } 2242 } 2243 } 2244 2245 Static void 2246 ar9003_calib_iq(struct athn_softc *sc) 2247 { 2248 struct athn_iq_cal *cal; 2249 uint32_t reg, i_coff_denom, q_coff_denom; 2250 int32_t i_coff, q_coff; 2251 int i, iq_corr_neg; 2252 2253 for (i = 0; i < AR_MAX_CHAINS; i++) { 2254 cal = &sc->sc_calib.iq[i]; 2255 2256 /* Read IQ calibration measures (clear on read). */ 2257 cal->pwr_meas_i = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_0_B(i)); 2258 cal->pwr_meas_q = AR_READ(sc, AR_PHY_IQ_ADC_MEAS_1_B(i)); 2259 cal->iq_corr_meas = 2260 (int32_t)AR_READ(sc, AR_PHY_IQ_ADC_MEAS_2_B(i)); 2261 } 2262 2263 for (i = 0; i < sc->sc_nrxchains; i++) { 2264 cal = &sc->sc_calib.iq[i]; 2265 2266 if (cal->pwr_meas_q == 0) 2267 continue; 2268 2269 if ((iq_corr_neg = cal->iq_corr_meas) < 0) 2270 cal->iq_corr_meas = -cal->iq_corr_meas; 2271 2272 i_coff_denom = 2273 (cal->pwr_meas_i / 2 + cal->pwr_meas_q / 2) / 256; 2274 q_coff_denom = cal->pwr_meas_q / 64; 2275 2276 if (i_coff_denom == 0 || q_coff_denom == 0) 2277 continue; /* Prevents division by zero. */ 2278 2279 i_coff = cal->iq_corr_meas / i_coff_denom; 2280 q_coff = (cal->pwr_meas_i / q_coff_denom) - 64; 2281 2282 if (i_coff > 63) 2283 i_coff = 63; 2284 else if (i_coff < -63) 2285 i_coff = -63; 2286 /* Negate i_coff if iq_corr_meas is positive. */ 2287 if (!iq_corr_neg) 2288 i_coff = -i_coff; 2289 if (q_coff > 63) 2290 q_coff = 63; 2291 else if (q_coff < -63) 2292 q_coff = -63; 2293 2294 DPRINTFN(DBG_RF, sc, "IQ calibration for chain %d\n", i); 2295 reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); 2296 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff); 2297 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff); 2298 AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); 2299 } 2300 2301 /* Apply new settings. */ 2302 AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), 2303 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); 2304 AR_WRITE_BARRIER(sc); 2305 2306 /* IQ calibration done. */ 2307 sc->sc_cur_calib_mask &= ~ATHN_CAL_IQ; 2308 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2309 } 2310 2311 #define DELPT 32 2312 Static int 2313 ar9003_get_iq_corr(struct athn_softc *sc, int32_t res[6], int32_t coeff[2]) 2314 { 2315 /* Sign-extends 12-bit value (assumes upper bits are zeroes). */ 2316 #define SIGN_EXT(v) (((v) ^ 0x800) - 0x800) 2317 #define SCALE (1 << 15) 2318 #define SHIFT (1 << 8) 2319 struct { 2320 int32_t m, p, c; 2321 } val[2][2]; 2322 int32_t mag[2][2], phs[2][2], cos[2], sin[2]; 2323 int32_t div, f1, f2, f3, m, p, c; 2324 int32_t txmag, txphs, rxmag, rxphs; 2325 int32_t q_coff, i_coff; 2326 int i, j; 2327 2328 /* Extract our twelve signed 12-bit values from res[] array. */ 2329 val[0][0].m = res[0] & 0xfff; 2330 val[0][0].p = (res[0] >> 12) & 0xfff; 2331 val[0][0].c = ((res[0] >> 24) & 0xff) | (res[1] & 0xf) << 8; 2332 2333 val[0][1].m = (res[1] >> 4) & 0xfff; 2334 val[0][1].p = res[2] & 0xfff; 2335 val[0][1].c = (res[2] >> 12) & 0xfff; 2336 2337 val[1][0].m = ((res[2] >> 24) & 0xff) | (res[3] & 0xf) << 8; 2338 val[1][0].p = (res[3] >> 4) & 0xfff; 2339 val[1][0].c = res[4] & 0xfff; 2340 2341 val[1][1].m = (res[4] >> 12) & 0xfff; 2342 val[1][1].p = ((res[4] >> 24) & 0xff) | (res[5] & 0xf) << 8; 2343 val[1][1].c = (res[5] >> 4) & 0xfff; 2344 2345 for (i = 0; i < 2; i++) { 2346 int32_t ymin, ymax; 2347 for (j = 0; j < 2; j++) { 2348 m = SIGN_EXT(val[i][j].m); 2349 p = SIGN_EXT(val[i][j].p); 2350 c = SIGN_EXT(val[i][j].c); 2351 2352 if (p == 0) 2353 return 1; /* Prevent division by 0. */ 2354 2355 mag[i][j] = (m * SCALE) / p; 2356 phs[i][j] = (c * SCALE) / p; 2357 } 2358 sin[i] = ((mag[i][0] - mag[i][1]) * SHIFT) / DELPT; 2359 cos[i] = ((phs[i][0] - phs[i][1]) * SHIFT) / DELPT; 2360 /* Find magnitude by approximation. */ 2361 ymin = MIN(abs(sin[i]), abs(cos[i])); 2362 ymax = MAX(abs(sin[i]), abs(cos[i])); 2363 div = ymax - (ymax / 32) + (ymin / 8) + (ymin / 4); 2364 if (div == 0) 2365 return 1; /* Prevent division by 0. */ 2366 /* Normalize sin and cos by magnitude. */ 2367 sin[i] = (sin[i] * SCALE) / div; 2368 cos[i] = (cos[i] * SCALE) / div; 2369 } 2370 2371 /* Compute IQ mismatch (solve 4x4 linear equation). */ 2372 f1 = cos[0] - cos[1]; 2373 f3 = sin[0] - sin[1]; 2374 f2 = (f1 * f1 + f3 * f3) / SCALE; 2375 if (f2 == 0) 2376 return 1; /* Prevent division by 0. */ 2377 2378 /* Compute Tx magnitude mismatch. */ 2379 txmag = (f1 * ( mag[0][0] - mag[1][0]) + 2380 f3 * ( phs[0][0] - phs[1][0])) / f2; 2381 /* Compute Tx phase mismatch. */ 2382 txphs = (f3 * (-mag[0][0] + mag[1][0]) + 2383 f1 * ( phs[0][0] - phs[1][0])) / f2; 2384 2385 if (txmag == SCALE) 2386 return 1; /* Prevent division by 0. */ 2387 2388 /* Compute Rx magnitude mismatch. */ 2389 rxmag = mag[0][0] - (cos[0] * txmag + sin[0] * txphs) / SCALE; 2390 /* Compute Rx phase mismatch. */ 2391 rxphs = phs[0][0] + (sin[0] * txmag - cos[0] * txphs) / SCALE; 2392 2393 if (-rxmag == SCALE) 2394 return 1; /* Prevent division by 0. */ 2395 2396 txmag = (txmag * SCALE) / (SCALE - txmag); 2397 txphs = -txphs; 2398 2399 q_coff = (txmag * 128) / SCALE; 2400 if (q_coff < -63) 2401 q_coff = -63; 2402 else if (q_coff > 63) 2403 q_coff = 63; 2404 i_coff = (txphs * 256) / SCALE; 2405 if (i_coff < -63) 2406 i_coff = -63; 2407 else if (i_coff > 63) 2408 i_coff = 63; 2409 coeff[0] = q_coff * 128 + i_coff; 2410 2411 rxmag = (-rxmag * SCALE) / (SCALE + rxmag); 2412 rxphs = -rxphs; 2413 2414 q_coff = (rxmag * 128) / SCALE; 2415 if (q_coff < -63) 2416 q_coff = -63; 2417 else if (q_coff > 63) 2418 q_coff = 63; 2419 i_coff = (rxphs * 256) / SCALE; 2420 if (i_coff < -63) 2421 i_coff = -63; 2422 else if (i_coff > 63) 2423 i_coff = 63; 2424 coeff[1] = q_coff * 128 + i_coff; 2425 2426 return 0; 2427 #undef SHIFT 2428 #undef SCALE 2429 #undef SIGN_EXT 2430 } 2431 2432 Static int 2433 ar9003_calib_tx_iq(struct athn_softc *sc) 2434 { 2435 uint32_t reg; 2436 int32_t res[6], coeff[2]; 2437 int i, j, ntries; 2438 2439 reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1); 2440 reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT); 2441 AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg); 2442 2443 /* Start Tx IQ calibration. */ 2444 AR_SETBITS(sc, AR_PHY_TX_IQCAL_START, AR_PHY_TX_IQCAL_START_DO_CAL); 2445 /* Wait for completion. */ 2446 for (ntries = 0; ntries < 10000; ntries++) { 2447 reg = AR_READ(sc, AR_PHY_TX_IQCAL_START); 2448 if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL)) 2449 break; 2450 DELAY(10); 2451 } 2452 if (ntries == 10000) 2453 return ETIMEDOUT; 2454 2455 for (i = 0; i < sc->sc_ntxchains; i++) { 2456 /* Read Tx IQ calibration status for this chain. */ 2457 reg = AR_READ(sc, AR_PHY_TX_IQCAL_STATUS_B(i)); 2458 if (reg & AR_PHY_TX_IQCAL_STATUS_FAILED) 2459 return EIO; 2460 /* 2461 * Read Tx IQ calibration results for this chain. 2462 * This consists in twelve signed 12-bit values. 2463 */ 2464 for (j = 0; j < 3; j++) { 2465 AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, 2466 AR_PHY_CHAN_INFO_TAB_S2_READ); 2467 reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); 2468 res[j * 2 + 0] = reg; 2469 2470 AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, 2471 AR_PHY_CHAN_INFO_TAB_S2_READ); 2472 reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j)); 2473 res[j * 2 + 1] = reg & 0xffff; 2474 } 2475 2476 /* Compute Tx IQ correction. */ 2477 if (ar9003_get_iq_corr(sc, res, coeff) != 0) 2478 return EIO; 2479 2480 /* Write Tx IQ correction coefficients. */ 2481 reg = AR_READ(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i)); 2482 reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, 2483 coeff[0]); 2484 AR_WRITE(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i), reg); 2485 2486 reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i)); 2487 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF, 2488 coeff[1] >> 7); 2489 reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF, 2490 coeff[1]); 2491 AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg); 2492 AR_WRITE_BARRIER(sc); 2493 } 2494 2495 /* Enable Tx IQ correction. */ 2496 AR_SETBITS(sc, AR_PHY_TX_IQCAL_CONTROL_3, 2497 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN); 2498 AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0), 2499 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN); 2500 AR_WRITE_BARRIER(sc); 2501 return 0; 2502 } 2503 #undef DELPT 2504 2505 /*- 2506 * The power amplifier predistortion state machine works as follows: 2507 * 1) Disable digital predistorters for all Tx chains 2508 * 2) Repeat steps 3~7 for all Tx chains 2509 * 3) Force Tx gain to that of training signal 2510 * 4) Send training signal (asynchronous) 2511 * 5) Wait for training signal to complete (asynchronous) 2512 * 6) Read PA measurements (input power, output power, output phase) 2513 * 7) Compute the predistortion function that linearizes PA output 2514 * 8) Write predistortion functions to hardware tables for all Tx chains 2515 * 9) Enable digital predistorters for all Tx chains 2516 */ 2517 #ifdef notused 2518 Static void 2519 ar9003_paprd_calib(struct athn_softc *sc, struct ieee80211_channel *c) 2520 { 2521 static const int scaling[] = { 2522 261376, 248079, 233759, 220464, 2523 208194, 196949, 185706, 175487 2524 }; 2525 struct athn_ops *ops = &sc->sc_ops; 2526 uint32_t reg, ht20mask, ht40mask; 2527 int i; 2528 2529 /* Read PA predistortion masks from ROM. */ 2530 ops->get_paprd_masks(sc, c, &ht20mask, &ht40mask); 2531 2532 /* AM-to-AM: amplifier's amplitude characteristic. */ 2533 reg = AR_READ(sc, AR_PHY_PAPRD_AM2AM); 2534 reg = RW(reg, AR_PHY_PAPRD_AM2AM_MASK, ht20mask); 2535 AR_WRITE(sc, AR_PHY_PAPRD_AM2AM, reg); 2536 2537 /* AM-to-PM: amplifier's phase transfer characteristic. */ 2538 reg = AR_READ(sc, AR_PHY_PAPRD_AM2PM); 2539 reg = RW(reg, AR_PHY_PAPRD_AM2PM_MASK, ht20mask); 2540 AR_WRITE(sc, AR_PHY_PAPRD_AM2PM, reg); 2541 2542 reg = AR_READ(sc, AR_PHY_PAPRD_HT40); 2543 reg = RW(reg, AR_PHY_PAPRD_HT40_MASK, ht40mask); 2544 AR_WRITE(sc, AR_PHY_PAPRD_HT40, reg); 2545 2546 for (i = 0; i < AR9003_MAX_CHAINS; i++) { 2547 AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), 2548 AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE); 2549 2550 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(i)); 2551 reg = RW(reg, AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT, 181); 2552 reg = RW(reg, AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT, 361); 2553 reg &= ~AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA; 2554 reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA; 2555 reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA; 2556 AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(i), reg); 2557 2558 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL0_B(i)); 2559 reg = RW(reg, AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3); 2560 AR_WRITE(sc, AR_PHY_PAPRD_CTRL0_B(i), reg); 2561 } 2562 2563 /* Disable all digital predistorters during calibration. */ 2564 for (i = 0; i < AR9003_MAX_CHAINS; i++) { 2565 AR_CLRBITS(sc, AR_PHY_PAPRD_CTRL0_B(i), 2566 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); 2567 } 2568 AR_WRITE_BARRIER(sc); 2569 2570 /* 2571 * Configure training signal. 2572 */ 2573 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL1); 2574 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING, 28); 2575 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP, 0x30); 2576 reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE; 2577 reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE; 2578 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE; 2579 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE; 2580 reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE; 2581 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL1, reg); 2582 2583 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL2, 147); 2584 2585 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL3); 2586 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN, 4); 2587 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN, 4); 2588 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES, 7); 2589 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL, 1); 2590 if (AR_SREV_9485(sc)) 2591 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -3); 2592 else 2593 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -6); 2594 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE, -15); 2595 reg |= AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE; 2596 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL3, reg); 2597 2598 reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL4); 2599 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA, 0); 2600 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR, 400); 2601 reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES, 100); 2602 AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL4, reg); 2603 2604 for (i = 0; i < __arraycount(scaling); i++) { 2605 reg = AR_READ(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i)); 2606 reg = RW(reg, AR_PHY_PAPRD_PRE_POST_SCALING, scaling[i]); 2607 AR_WRITE(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i), reg); 2608 } 2609 2610 /* Save Tx gain table. */ 2611 for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE; i++) 2612 sc->sc_txgain[i] = AR_READ(sc, AR_PHY_TXGAIN_TABLE(i)); 2613 2614 /* Set Tx power of training signal (use setting for MCS0). */ 2615 sc->sc_trainpow = MS(AR_READ(sc, AR_PHY_PWRTX_RATE5), 2616 AR_PHY_PWRTX_RATE5_POWERTXHT20_0) - 4; 2617 2618 /* 2619 * Start PA predistortion calibration state machine. 2620 */ 2621 /* Find first available Tx chain. */ 2622 sc->sc_paprd_curchain = 0; 2623 while (!(sc->sc_txchainmask & (1 << sc->sc_paprd_curchain))) 2624 sc->sc_paprd_curchain++; 2625 2626 /* Make sure training done bit is clear. */ 2627 AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, 2628 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); 2629 AR_WRITE_BARRIER(sc); 2630 2631 /* Transmit training signal. */ 2632 ar9003_paprd_tx_tone(sc); 2633 } 2634 #endif /* notused */ 2635 2636 Static int 2637 ar9003_get_desired_txgain(struct athn_softc *sc, int chain, int pow) 2638 { 2639 int32_t scale, atemp, avolt, tempcal, voltcal, temp, volt; 2640 int32_t tempcorr, voltcorr; 2641 uint32_t reg; 2642 int8_t delta; 2643 2644 scale = MS(AR_READ(sc, AR_PHY_TPC_12), 2645 AR_PHY_TPC_12_DESIRED_SCALE_HT40_5); 2646 2647 reg = AR_READ(sc, AR_PHY_TPC_19); 2648 atemp = MS(reg, AR_PHY_TPC_19_ALPHA_THERM); 2649 avolt = MS(reg, AR_PHY_TPC_19_ALPHA_VOLT); 2650 2651 reg = AR_READ(sc, AR_PHY_TPC_18); 2652 tempcal = MS(reg, AR_PHY_TPC_18_THERM_CAL); 2653 voltcal = MS(reg, AR_PHY_TPC_18_VOLT_CAL); 2654 2655 reg = AR_READ(sc, AR_PHY_BB_THERM_ADC_4); 2656 temp = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_THERM); 2657 volt = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_VOLT); 2658 2659 delta = (int8_t)MS(AR_READ(sc, AR_PHY_TPC_11_B(chain)), 2660 AR_PHY_TPC_11_OLPC_GAIN_DELTA); 2661 2662 /* Compute temperature and voltage correction. */ 2663 tempcorr = (atemp * (temp - tempcal) + 128) / 256; 2664 voltcorr = (avolt * (volt - voltcal) + 64) / 128; 2665 2666 /* Compute desired Tx gain. */ 2667 return pow - delta - tempcorr - voltcorr + scale; 2668 } 2669 2670 Static void 2671 ar9003_force_txgain(struct athn_softc *sc, uint32_t txgain) 2672 { 2673 uint32_t reg; 2674 2675 reg = AR_READ(sc, AR_PHY_TX_FORCED_GAIN); 2676 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN, 2677 MS(txgain, AR_PHY_TXGAIN_TXBB1DBGAIN)); 2678 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN, 2679 MS(txgain, AR_PHY_TXGAIN_TXBB6DBGAIN)); 2680 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXMXRGAIN, 2681 MS(txgain, AR_PHY_TXGAIN_TXMXRGAIN)); 2682 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNA, 2683 MS(txgain, AR_PHY_TXGAIN_PADRVGNA)); 2684 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNB, 2685 MS(txgain, AR_PHY_TXGAIN_PADRVGNB)); 2686 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNC, 2687 MS(txgain, AR_PHY_TXGAIN_PADRVGNC)); 2688 reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGND, 2689 MS(txgain, AR_PHY_TXGAIN_PADRVGND)); 2690 reg &= ~AR_PHY_TX_FORCED_GAIN_ENABLE_PAL; 2691 reg &= ~AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN; 2692 AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, reg); 2693 2694 reg = AR_READ(sc, AR_PHY_TPC_1); 2695 reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0); 2696 reg &= ~AR_PHY_TPC_1_FORCE_DAC_GAIN; 2697 AR_WRITE(sc, AR_PHY_TPC_1, reg); 2698 AR_WRITE_BARRIER(sc); 2699 } 2700 2701 Static void 2702 ar9003_set_training_gain(struct athn_softc *sc, int chain) 2703 { 2704 size_t i; 2705 int gain; 2706 2707 /* 2708 * Get desired gain for training signal power (take into account 2709 * current temperature/voltage). 2710 */ 2711 gain = ar9003_get_desired_txgain(sc, chain, sc->sc_trainpow); 2712 /* Find entry in table. */ 2713 for (i = 0; i < AR9003_TX_GAIN_TABLE_SIZE - 1; i++) 2714 if ((int)MS(sc->sc_txgain[i], AR_PHY_TXGAIN_INDEX) >= gain) 2715 break; 2716 ar9003_force_txgain(sc, sc->sc_txgain[i]); 2717 } 2718 2719 Static int 2720 ar9003_paprd_tx_tone(struct athn_softc *sc) 2721 { 2722 #define TONE_LEN 1800 2723 struct ieee80211com *ic = &sc->sc_ic; 2724 struct ieee80211_frame *wh; 2725 struct ieee80211_node *ni; 2726 struct mbuf *m; 2727 int error; 2728 2729 /* Build a Null (no data) frame of TONE_LEN bytes. */ 2730 m = MCLGETI(NULL, M_DONTWAIT, NULL, TONE_LEN); 2731 if (m == NULL) 2732 return ENOBUFS; 2733 memset(mtod(m, void *), 0, TONE_LEN); 2734 wh = mtod(m, struct ieee80211_frame *); 2735 wh->i_fc[0] = IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_NODATA; 2736 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 2737 *(uint16_t *)wh->i_dur = htole16(10); /* XXX */ 2738 IEEE80211_ADDR_COPY(wh->i_addr1, ic->ic_myaddr); 2739 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 2740 IEEE80211_ADDR_COPY(wh->i_addr3, ic->ic_myaddr); 2741 m->m_pkthdr.len = m->m_len = TONE_LEN; 2742 2743 /* Set gain of training signal. */ 2744 ar9003_set_training_gain(sc, sc->sc_paprd_curchain); 2745 2746 /* Transmit training signal. */ 2747 ni = ieee80211_ref_node(ic->ic_bss); 2748 if ((error = ar9003_tx(sc, m, ni, ATHN_TXFLAG_PAPRD)) != 0) 2749 ieee80211_free_node(ni); 2750 return error; 2751 #undef TONE_LEN 2752 } 2753 2754 static __inline int 2755 get_scale(int val) 2756 { 2757 int log = 0; 2758 2759 /* Find the log base 2 (position of highest bit set). */ 2760 while (val >>= 1) 2761 log++; 2762 2763 return (log > 10) ? log - 10 : 0; 2764 } 2765 2766 /* 2767 * Compute predistortion function to linearize power amplifier output based 2768 * on feedback from training signal. 2769 */ 2770 Static int 2771 ar9003_compute_predistortion(struct athn_softc *sc, const uint32_t *lo, 2772 const uint32_t *hi) 2773 { 2774 #define NBINS 23 2775 int chain = sc->sc_paprd_curchain; 2776 int x[NBINS + 1], y[NBINS + 1], t[NBINS + 1]; 2777 int b1[NBINS + 1], b2[NBINS + 1], xtilde[NBINS + 1]; 2778 int nsamples, txsum, rxsum, rosum, maxidx; 2779 int order, order5x, order5xrem, order3x, order3xrem, y5, y3; 2780 int icept, G, I, L, M, angle, xnonlin, y2, y4, sumy2, sumy4; 2781 int alpha, beta, scale, Qalpha, Qbeta, Qscale, Qx, Qb1, Qb2; 2782 int tavg, ttilde, maxb1abs, maxb2abs, maxxtildeabs, in; 2783 int tmp, i; 2784 2785 /* Set values at origin. */ 2786 x[0] = y[0] = t[0] = 0; 2787 2788 #define SCALE 32 2789 maxidx = 0; 2790 for (i = 0; i < NBINS; i++) { 2791 nsamples = lo[i] & 0xffff; 2792 /* Skip bins that contain 16 or less samples. */ 2793 if (nsamples <= 16) { 2794 x[i + 1] = y[i + 1] = t[i + 1] = 0; 2795 continue; 2796 } 2797 txsum = (hi[i] & 0x7ff) << 16 | lo[i] >> 16; 2798 rxsum = (lo[i + NBINS] & 0xffff) << 5 | 2799 ((hi[i] >> 11) & 0x1f); 2800 rosum = (hi[i + NBINS] & 0x7ff) << 16 | hi[i + NBINS] >> 16; 2801 /* Sign-extend 27-bit value. */ 2802 rosum = (rosum ^ 0x4000000) - 0x4000000; 2803 2804 txsum *= SCALE; 2805 rxsum *= SCALE; 2806 rosum *= SCALE; 2807 2808 x[i + 1] = ((txsum + nsamples) / nsamples + SCALE) / SCALE; 2809 y[i + 1] = ((rxsum + nsamples) / nsamples + SCALE) / SCALE + 2810 SCALE * maxidx + SCALE / 2; 2811 t[i + 1] = (rosum + nsamples) / nsamples; 2812 maxidx++; 2813 } 2814 #undef SCALE 2815 2816 #define SCALE_LOG 8 2817 #define SCALE (1 << SCALE_LOG) 2818 if (x[6] == x[3]) 2819 return 1; /* Prevent division by 0. */ 2820 G = ((y[6] - y[3]) * SCALE + (x[6] - x[3])) / (x[6] - x[3]); 2821 if (G == 0) 2822 return 1; /* Prevent division by 0. */ 2823 2824 sc->sc_gain1[chain] = G; /* Save low signal gain. */ 2825 2826 /* Find interception point. */ 2827 icept = (G * (x[0] - x[3]) + SCALE) / SCALE + y[3]; 2828 for (i = 0; i <= 3; i++) { 2829 y[i] = i * 32; 2830 x[i] = (y[i] * SCALE + G) / G; 2831 } 2832 for (i = 4; i <= maxidx; i++) 2833 y[i] -= icept; 2834 2835 xnonlin = x[maxidx] - (y[maxidx] * SCALE + G) / G; 2836 order = (xnonlin + y[maxidx]) / y[maxidx]; 2837 if (order == 0) 2838 M = 10; 2839 else if (order == 1) 2840 M = 9; 2841 else 2842 M = 8; 2843 2844 I = (maxidx >= 16) ? 7 : maxidx / 2; 2845 L = maxidx - I; 2846 2847 sumy2 = sumy4 = y2 = y4 = 0; 2848 for (i = 0; i <= L; i++) { 2849 if (y[i + I] == 0) 2850 return 1; /* Prevent division by 0. */ 2851 2852 xnonlin = x[i + I] - ((y[i + I] * SCALE) + G) / G; 2853 xtilde[i] = ((xnonlin << M) + y[i + I]) / y[i + I]; 2854 xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; 2855 xtilde[i] = ((xtilde[i] << M) + y[i + I]) / y[i + I]; 2856 2857 y2 = (y[i + I] * y[i + I] + SCALE * SCALE) / (SCALE * SCALE); 2858 2859 sumy2 += y2; 2860 sumy4 += y2 * y2; 2861 2862 b1[i] = y2 * (L + 1); 2863 b2[i] = y2; 2864 } 2865 for (i = 0; i <= L; i++) { 2866 b1[i] -= sumy2; 2867 b2[i] = sumy4 - sumy2 * b2[i]; 2868 } 2869 2870 maxxtildeabs = maxb1abs = maxb2abs = 0; 2871 for (i = 0; i <= L; i++) { 2872 tmp = abs(xtilde[i]); 2873 if (tmp > maxxtildeabs) 2874 maxxtildeabs = tmp; 2875 2876 tmp = abs(b1[i]); 2877 if (tmp > maxb1abs) 2878 maxb1abs = tmp; 2879 2880 tmp = abs(b2[i]); 2881 if (tmp > maxb2abs) 2882 maxb2abs = tmp; 2883 } 2884 Qx = get_scale(maxxtildeabs); 2885 Qb1 = get_scale(maxb1abs); 2886 Qb2 = get_scale(maxb2abs); 2887 for (i = 0; i <= L; i++) { 2888 xtilde[i] /= 1 << Qx; 2889 b1[i] /= 1 << Qb1; 2890 b2[i] /= 1 << Qb2; 2891 } 2892 2893 alpha = beta = 0; 2894 for (i = 0; i <= L; i++) { 2895 alpha += b1[i] * xtilde[i]; 2896 beta += b2[i] * xtilde[i]; 2897 } 2898 2899 scale = ((y4 / SCALE_LOG) * (L + 1) - 2900 (y2 / SCALE_LOG) * sumy2) * SCALE_LOG; 2901 2902 Qscale = get_scale(abs(scale)); 2903 scale /= 1 << Qscale; 2904 Qalpha = get_scale(abs(alpha)); 2905 alpha /= 1 << Qalpha; 2906 Qbeta = get_scale(abs(beta)); 2907 beta /= 1 << Qbeta; 2908 2909 order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale; 2910 order5x = 1 << (order / 5); 2911 order5xrem = 1 << (order % 5); 2912 2913 order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale; 2914 order3x = 1 << (order / 3); 2915 order3xrem = 1 << (order % 3); 2916 2917 for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2918 tmp = i * 32; 2919 2920 /* Fifth order. */ 2921 y5 = ((beta * tmp) / 64) / order5x; 2922 y5 = (y5 * tmp) / order5x; 2923 y5 = (y5 * tmp) / order5x; 2924 y5 = (y5 * tmp) / order5x; 2925 y5 = (y5 * tmp) / order5x; 2926 y5 = y5 / order5xrem; 2927 2928 /* Third oder. */ 2929 y3 = (alpha * tmp) / order3x; 2930 y3 = (y3 * tmp) / order3x; 2931 y3 = (y3 * tmp) / order3x; 2932 y3 = y3 / order3xrem; 2933 2934 in = y5 + y3 + (SCALE * tmp) / G; 2935 if (i >= 2 && in < sc->sc_pa_in[chain][i - 1]) { 2936 in = sc->sc_pa_in[chain][i - 1] + 2937 (sc->sc_pa_in[chain][i - 1] - 2938 sc->sc_pa_in[chain][i - 2]); 2939 } 2940 if (in > 1400) 2941 in = 1400; 2942 sc->sc_pa_in[chain][i] = in; 2943 } 2944 2945 /* Compute average theta of first 5 bins (linear region). */ 2946 tavg = 0; 2947 for (i = 1; i <= 5; i++) 2948 tavg += t[i]; 2949 tavg /= 5; 2950 for (i = 1; i <= 5; i++) 2951 t[i] = 0; 2952 for (i = 6; i <= maxidx; i++) 2953 t[i] -= tavg; 2954 2955 alpha = beta = 0; 2956 for (i = 0; i <= L; i++) { 2957 ttilde = ((t[i + I] << M) + y[i + I]) / y[i + I]; 2958 ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; 2959 ttilde = ((ttilde << M) + y[i + I]) / y[i + I]; 2960 2961 alpha += b2[i] * ttilde; 2962 beta += b1[i] * ttilde; 2963 } 2964 2965 Qalpha = get_scale(abs(alpha)); 2966 alpha /= 1 << Qalpha; 2967 Qbeta = get_scale(abs(beta)); 2968 beta /= 1 << Qbeta; 2969 2970 order = 3 * M - Qx - Qb1 - Qbeta + 10 + Qscale + 5; 2971 order5x = 1 << (order / 5); 2972 order5xrem = 1 << (order % 5); 2973 2974 order = 3 * M - Qx - Qb2 - Qalpha + 10 + Qscale + 5; 2975 order3x = 1 << (order / 3); 2976 order3xrem = 1 << (order % 3); 2977 2978 for (i = 0; i <= 4; i++) 2979 sc->sc_angle[chain][i] = 0; /* Linear at that range. */ 2980 for (i = 5; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 2981 tmp = i * 32; 2982 2983 /* Fifth order. */ 2984 if (beta > 0) 2985 y5 = (((beta * tmp - 64) / 64) - order5x) / order5x; 2986 else 2987 y5 = (((beta * tmp - 64) / 64) + order5x) / order5x; 2988 y5 = (y5 * tmp) / order5x; 2989 y5 = (y5 * tmp) / order5x; 2990 y5 = (y5 * tmp) / order5x; 2991 y5 = (y5 * tmp) / order5x; 2992 y5 = y5 / order5xrem; 2993 2994 /* Third oder. */ 2995 if (beta > 0) /* XXX alpha? */ 2996 y3 = (alpha * tmp - order3x) / order3x; 2997 else 2998 y3 = (alpha * tmp + order3x) / order3x; 2999 y3 = (y3 * tmp) / order3x; 3000 y3 = (y3 * tmp) / order3x; 3001 y3 = y3 / order3xrem; 3002 3003 angle = y5 + y3; 3004 if (angle < -150) 3005 angle = -150; 3006 else if (angle > 150) 3007 angle = 150; 3008 sc->sc_angle[chain][i] = angle; 3009 } 3010 /* Angle for entry 4 is derived from angle for entry 5. */ 3011 sc->sc_angle[chain][4] = (sc->sc_angle[chain][5] + 2) / 2; 3012 3013 return 0; 3014 #undef SCALE 3015 #undef SCALE_LOG 3016 #undef NBINS 3017 } 3018 3019 Static void 3020 ar9003_enable_predistorter(struct athn_softc *sc, int chain) 3021 { 3022 uint32_t reg; 3023 int i; 3024 3025 /* Write digital predistorter lookup table. */ 3026 for (i = 0; i < AR9003_PAPRD_MEM_TAB_SIZE; i++) { 3027 AR_WRITE(sc, AR_PHY_PAPRD_MEM_TAB_B(chain, i), 3028 SM(AR_PHY_PAPRD_PA_IN, sc->sc_pa_in[chain][i]) | 3029 SM(AR_PHY_PAPRD_ANGLE, sc->sc_angle[chain][i])); 3030 } 3031 3032 reg = AR_READ(sc, AR_PHY_PA_GAIN123_B(chain)); 3033 reg = RW(reg, AR_PHY_PA_GAIN123_PA_GAIN1, sc->sc_gain1[chain]); 3034 AR_WRITE(sc, AR_PHY_PA_GAIN123_B(chain), reg); 3035 3036 /* Indicate Tx power used for calibration (training signal). */ 3037 reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(chain)); 3038 reg = RW(reg, AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL, sc->sc_trainpow); 3039 AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(chain), reg); 3040 3041 /* Enable digital predistorter for this chain. */ 3042 AR_SETBITS(sc, AR_PHY_PAPRD_CTRL0_B(chain), 3043 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE); 3044 AR_WRITE_BARRIER(sc); 3045 } 3046 3047 Static void 3048 ar9003_paprd_enable(struct athn_softc *sc) 3049 { 3050 int i; 3051 3052 /* Enable digital predistorters for all Tx chains. */ 3053 for (i = 0; i < AR9003_MAX_CHAINS; i++) 3054 if (sc->sc_txchainmask & (1 << i)) 3055 ar9003_enable_predistorter(sc, i); 3056 } 3057 3058 /* 3059 * This function is called when our training signal has been sent. 3060 */ 3061 Static void 3062 ar9003_paprd_tx_tone_done(struct athn_softc *sc) 3063 { 3064 uint32_t lo[48], hi[48]; 3065 size_t i; 3066 3067 /* Make sure training is complete. */ 3068 if (!(AR_READ(sc, AR_PHY_PAPRD_TRAINER_STAT1) & 3069 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE)) 3070 return; 3071 3072 /* Read feedback from training signal. */ 3073 AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); 3074 for (i = 0; i < __arraycount(lo); i++) 3075 lo[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); 3076 AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY, AR_PHY_CHAN_INFO_TAB_S2_READ); 3077 for (i = 0; i < __arraycount(hi); i++) 3078 hi[i] = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(0, i)); 3079 3080 AR_CLRBITS(sc, AR_PHY_PAPRD_TRAINER_STAT1, 3081 AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE); 3082 3083 /* Compute predistortion function based on this feedback. */ 3084 if (ar9003_compute_predistortion(sc, lo, hi) != 0) 3085 return; 3086 3087 /* Get next available Tx chain. */ 3088 while (++sc->sc_paprd_curchain < AR9003_MAX_CHAINS) 3089 if (sc->sc_txchainmask & (1 << sc->sc_paprd_curchain)) 3090 break; 3091 if (sc->sc_paprd_curchain == AR9003_MAX_CHAINS) { 3092 /* All Tx chains measured; enable digital predistortion. */ 3093 ar9003_paprd_enable(sc); 3094 } 3095 else /* Measure next Tx chain. */ 3096 ar9003_paprd_tx_tone(sc); 3097 } 3098 3099 PUBLIC void 3100 ar9003_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT]) 3101 { 3102 3103 /* Make sure forced gain is disabled. */ 3104 AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, 0); 3105 3106 AR_WRITE(sc, AR_PHY_PWRTX_RATE1, 3107 (power[ATHN_POWER_OFDM18 ] & 0x3f) << 24 | 3108 (power[ATHN_POWER_OFDM12 ] & 0x3f) << 16 | 3109 (power[ATHN_POWER_OFDM9 ] & 0x3f) << 8 | 3110 (power[ATHN_POWER_OFDM6 ] & 0x3f)); 3111 AR_WRITE(sc, AR_PHY_PWRTX_RATE2, 3112 (power[ATHN_POWER_OFDM54 ] & 0x3f) << 24 | 3113 (power[ATHN_POWER_OFDM48 ] & 0x3f) << 16 | 3114 (power[ATHN_POWER_OFDM36 ] & 0x3f) << 8 | 3115 (power[ATHN_POWER_OFDM24 ] & 0x3f)); 3116 AR_WRITE(sc, AR_PHY_PWRTX_RATE3, 3117 (power[ATHN_POWER_CCK2_SP ] & 0x3f) << 24 | 3118 (power[ATHN_POWER_CCK2_LP ] & 0x3f) << 16 | 3119 /* NB: No eXtended Range for AR9003. */ 3120 (power[ATHN_POWER_CCK1_LP ] & 0x3f)); 3121 AR_WRITE(sc, AR_PHY_PWRTX_RATE4, 3122 (power[ATHN_POWER_CCK11_SP] & 0x3f) << 24 | 3123 (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 | 3124 (power[ATHN_POWER_CCK55_SP] & 0x3f) << 8 | 3125 (power[ATHN_POWER_CCK55_LP] & 0x3f)); 3126 /* 3127 * NB: AR_PHY_PWRTX_RATE5 needs to be written even if HT is disabled 3128 * because it is read by PA predistortion functions. 3129 */ 3130 AR_WRITE(sc, AR_PHY_PWRTX_RATE5, 3131 (power[ATHN_POWER_HT20( 5)] & 0x3f) << 24 | 3132 (power[ATHN_POWER_HT20( 4)] & 0x3f) << 16 | 3133 (power[ATHN_POWER_HT20( 1)] & 0x3f) << 8 | 3134 (power[ATHN_POWER_HT20( 0)] & 0x3f)); 3135 #ifndef IEEE80211_NO_HT 3136 AR_WRITE(sc, AR_PHY_PWRTX_RATE6, 3137 (power[ATHN_POWER_HT20(13)] & 0x3f) << 24 | 3138 (power[ATHN_POWER_HT20(12)] & 0x3f) << 16 | 3139 (power[ATHN_POWER_HT20( 7)] & 0x3f) << 8 | 3140 (power[ATHN_POWER_HT20( 6)] & 0x3f)); 3141 AR_WRITE(sc, AR_PHY_PWRTX_RATE7, 3142 (power[ATHN_POWER_HT40( 5)] & 0x3f) << 24 | 3143 (power[ATHN_POWER_HT40( 4)] & 0x3f) << 16 | 3144 (power[ATHN_POWER_HT40( 1)] & 0x3f) << 8 | 3145 (power[ATHN_POWER_HT40( 0)] & 0x3f)); 3146 AR_WRITE(sc, AR_PHY_PWRTX_RATE8, 3147 (power[ATHN_POWER_HT40(13)] & 0x3f) << 24 | 3148 (power[ATHN_POWER_HT40(12)] & 0x3f) << 16 | 3149 (power[ATHN_POWER_HT40( 7)] & 0x3f) << 8 | 3150 (power[ATHN_POWER_HT40( 6)] & 0x3f)); 3151 AR_WRITE(sc, AR_PHY_PWRTX_RATE10, 3152 (power[ATHN_POWER_HT20(21)] & 0x3f) << 24 | 3153 (power[ATHN_POWER_HT20(20)] & 0x3f) << 16 | 3154 (power[ATHN_POWER_HT20(15)] & 0x3f) << 8 | 3155 (power[ATHN_POWER_HT20(14)] & 0x3f)); 3156 AR_WRITE(sc, AR_PHY_PWRTX_RATE11, 3157 (power[ATHN_POWER_HT40(23)] & 0x3f) << 24 | 3158 (power[ATHN_POWER_HT40(22)] & 0x3f) << 16 | 3159 (power[ATHN_POWER_HT20(23)] & 0x3f) << 8 | 3160 (power[ATHN_POWER_HT20(22)] & 0x3f)); 3161 AR_WRITE(sc, AR_PHY_PWRTX_RATE12, 3162 (power[ATHN_POWER_HT40(21)] & 0x3f) << 24 | 3163 (power[ATHN_POWER_HT40(20)] & 0x3f) << 16 | 3164 (power[ATHN_POWER_HT40(15)] & 0x3f) << 8 | 3165 (power[ATHN_POWER_HT40(14)] & 0x3f)); 3166 #endif 3167 AR_WRITE_BARRIER(sc); 3168 } 3169 3170 Static void 3171 ar9003_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 3172 { 3173 #define X(x) ((uint32_t)(x) << 2) 3174 const struct athn_gain *prog = sc->sc_rx_gain; 3175 const uint32_t *pvals; 3176 int i; 3177 3178 if (IEEE80211_IS_CHAN_2GHZ(c)) 3179 pvals = prog->vals_2g; 3180 else 3181 pvals = prog->vals_5g; 3182 for (i = 0; i < prog->nregs; i++) 3183 AR_WRITE(sc, X(prog->regs[i]), pvals[i]); 3184 AR_WRITE_BARRIER(sc); 3185 #undef X 3186 } 3187 3188 Static void 3189 ar9003_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 3190 { 3191 #define X(x) ((uint32_t)(x) << 2) 3192 const struct athn_gain *prog = sc->sc_tx_gain; 3193 const uint32_t *pvals; 3194 int i; 3195 3196 if (IEEE80211_IS_CHAN_2GHZ(c)) 3197 pvals = prog->vals_2g; 3198 else 3199 pvals = prog->vals_5g; 3200 for (i = 0; i < prog->nregs; i++) 3201 AR_WRITE(sc, X(prog->regs[i]), pvals[i]); 3202 AR_WRITE_BARRIER(sc); 3203 #undef X 3204 } 3205 3206 Static void 3207 ar9003_hw_init(struct athn_softc *sc, struct ieee80211_channel *c, 3208 struct ieee80211_channel *extc) 3209 { 3210 #define X(x) ((uint32_t)(x) << 2) 3211 struct athn_ops *ops = &sc->sc_ops; 3212 const struct athn_ini *ini = sc->sc_ini; 3213 const uint32_t *pvals; 3214 uint32_t reg; 3215 int i; 3216 3217 /* 3218 * The common init values include the pre and core phases for the 3219 * SoC, MAC, BB and Radio subsystems. 3220 */ 3221 DPRINTFN(DBG_INIT, sc, "writing pre and core init vals\n"); 3222 for (i = 0; i < ini->ncmregs; i++) { 3223 AR_WRITE(sc, X(ini->cmregs[i]), ini->cmvals[i]); 3224 if (AR_IS_ANALOG_REG(X(ini->cmregs[i]))) 3225 DELAY(100); 3226 if ((i & 0x1f) == 0) 3227 DELAY(1); 3228 } 3229 3230 /* 3231 * The modal init values include the post phase for the SoC, MAC, 3232 * BB and Radio subsystems. 3233 */ 3234 #ifndef IEEE80211_NO_HT 3235 if (extc != NULL) { 3236 if (IEEE80211_IS_CHAN_2GHZ(c)) 3237 pvals = ini->vals_2g40; 3238 else 3239 pvals = ini->vals_5g40; 3240 } 3241 else 3242 #endif 3243 { 3244 if (IEEE80211_IS_CHAN_2GHZ(c)) 3245 pvals = ini->vals_2g20; 3246 else 3247 pvals = ini->vals_5g20; 3248 } 3249 DPRINTFN(DBG_INIT, sc, "writing post init vals\n"); 3250 for (i = 0; i < ini->nregs; i++) { 3251 AR_WRITE(sc, X(ini->regs[i]), pvals[i]); 3252 if (AR_IS_ANALOG_REG(X(ini->regs[i]))) 3253 DELAY(100); 3254 if ((i & 0x1f) == 0) 3255 DELAY(1); 3256 } 3257 3258 if (sc->sc_rx_gain != NULL) 3259 ar9003_reset_rx_gain(sc, c); 3260 if (sc->sc_tx_gain != NULL) 3261 ar9003_reset_tx_gain(sc, c); 3262 3263 if (IEEE80211_IS_CHAN_5GHZ(c) && 3264 (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK)) { 3265 /* Update modal values for fast PLL clock. */ 3266 #ifndef IEEE80211_NO_HT 3267 if (extc != NULL) 3268 pvals = ini->fastvals_5g40; 3269 else 3270 #endif 3271 pvals = ini->fastvals_5g20; 3272 DPRINTFN(DBG_INIT, sc, "writing fast pll clock init vals\n"); 3273 for (i = 0; i < ini->nfastregs; i++) { 3274 AR_WRITE(sc, X(ini->fastregs[i]), pvals[i]); 3275 if (AR_IS_ANALOG_REG(X(ini->fastregs[i]))) 3276 DELAY(100); 3277 if ((i & 0x1f) == 0) 3278 DELAY(1); 3279 } 3280 } 3281 3282 /* 3283 * Set the RX_ABORT and RX_DIS bits to prevent frames with corrupted 3284 * descriptor status. 3285 */ 3286 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 3287 3288 reg = AR_READ(sc, AR_PCU_MISC_MODE2); 3289 reg &= ~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE; 3290 reg |= AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX; 3291 reg |= AR_PCU_MISC_MODE2_ENABLE_AGGWEP; 3292 AR_WRITE(sc, AR_PCU_MISC_MODE2, reg); 3293 AR_WRITE_BARRIER(sc); 3294 3295 ar9003_set_phy(sc, c, extc); 3296 ar9003_init_chains(sc); 3297 3298 ops->set_txpower(sc, c, extc); 3299 #undef X 3300 } 3301 3302 PUBLIC void 3303 ar9003_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c, 3304 uint8_t ctl, const uint8_t *fbins, 3305 const struct ar_cal_target_power_leg *tgt, int nchans, uint8_t tpow[4]) 3306 { 3307 uint8_t fbin; 3308 int i, delta, lo, hi; 3309 3310 lo = hi = -1; 3311 fbin = athn_chan2fbin(c); 3312 for (i = 0; i < nchans; i++) { 3313 delta = fbin - fbins[i]; 3314 /* Find the largest sample that is <= our frequency. */ 3315 if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) 3316 lo = i; 3317 /* Find the smallest sample that is >= our frequency. */ 3318 if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) 3319 hi = i; 3320 } 3321 if (lo == -1) 3322 lo = hi; 3323 else if (hi == -1) 3324 hi = lo; 3325 /* Interpolate values. */ 3326 for (i = 0; i < 4; i++) { 3327 tpow[i] = athn_interpolate(fbin, 3328 fbins[lo], tgt[lo].tPow2x[i], 3329 fbins[hi], tgt[hi].tPow2x[i]); 3330 } 3331 /* XXX Apply conformance test limit. */ 3332 } 3333 3334 PUBLIC void 3335 ar9003_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c, 3336 uint8_t ctl, const uint8_t *fbins, 3337 const struct ar_cal_target_power_ht *tgt, int nchans, uint8_t tpow[14]) 3338 { 3339 uint8_t fbin; 3340 int i, delta, lo, hi; 3341 3342 lo = hi = -1; 3343 fbin = athn_chan2fbin(c); 3344 for (i = 0; i < nchans; i++) { 3345 delta = fbin - fbins[i]; 3346 /* Find the largest sample that is <= our frequency. */ 3347 if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo])) 3348 lo = i; 3349 /* Find the smallest sample that is >= our frequency. */ 3350 if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi])) 3351 hi = i; 3352 } 3353 if (lo == -1) 3354 lo = hi; 3355 else if (hi == -1) 3356 hi = lo; 3357 /* Interpolate values. */ 3358 for (i = 0; i < 14; i++) { 3359 tpow[i] = athn_interpolate(fbin, 3360 fbins[lo], tgt[lo].tPow2x[i], 3361 fbins[hi], tgt[hi].tPow2x[i]); 3362 } 3363 /* XXX Apply conformance test limit. */ 3364 } 3365 3366 /* 3367 * Adaptive noise immunity. 3368 */ 3369 Static void 3370 ar9003_set_noise_immunity_level(struct athn_softc *sc, int level) 3371 { 3372 int high = level == 4; 3373 uint32_t reg; 3374 3375 reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 3376 reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55); 3377 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 3378 3379 reg = AR_READ(sc, AR_PHY_AGC); 3380 reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64); 3381 reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14); 3382 AR_WRITE(sc, AR_PHY_AGC, reg); 3383 3384 reg = AR_READ(sc, AR_PHY_FIND_SIG); 3385 reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78); 3386 AR_WRITE(sc, AR_PHY_FIND_SIG, reg); 3387 AR_WRITE_BARRIER(sc); 3388 } 3389 3390 Static void 3391 ar9003_enable_ofdm_weak_signal(struct athn_softc *sc) 3392 { 3393 uint32_t reg; 3394 3395 reg = AR_READ(sc, AR_PHY_SFCORR_LOW); 3396 reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50); 3397 reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40); 3398 reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48); 3399 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); 3400 3401 reg = AR_READ(sc, AR_PHY_SFCORR); 3402 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77); 3403 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64); 3404 reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16); 3405 AR_WRITE(sc, AR_PHY_SFCORR, reg); 3406 3407 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 3408 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50); 3409 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40); 3410 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77); 3411 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64); 3412 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 3413 3414 AR_SETBITS(sc, AR_PHY_SFCORR_LOW, 3415 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3416 AR_WRITE_BARRIER(sc); 3417 } 3418 3419 Static void 3420 ar9003_disable_ofdm_weak_signal(struct athn_softc *sc) 3421 { 3422 uint32_t reg; 3423 3424 reg = AR_READ(sc, AR_PHY_SFCORR_LOW); 3425 reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127); 3426 reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127); 3427 reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63); 3428 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg); 3429 3430 reg = AR_READ(sc, AR_PHY_SFCORR); 3431 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127); 3432 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127); 3433 reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31); 3434 AR_WRITE(sc, AR_PHY_SFCORR, reg); 3435 3436 reg = AR_READ(sc, AR_PHY_SFCORR_EXT); 3437 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127); 3438 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127); 3439 reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127); 3440 reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127); 3441 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg); 3442 3443 AR_CLRBITS(sc, AR_PHY_SFCORR_LOW, 3444 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3445 AR_WRITE_BARRIER(sc); 3446 } 3447 3448 Static void 3449 ar9003_set_cck_weak_signal(struct athn_softc *sc, int high) 3450 { 3451 uint32_t reg; 3452 3453 reg = AR_READ(sc, AR_PHY_CCK_DETECT); 3454 reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8); 3455 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg); 3456 AR_WRITE_BARRIER(sc); 3457 } 3458 3459 Static void 3460 ar9003_set_firstep_level(struct athn_softc *sc, int level) 3461 { 3462 uint32_t reg; 3463 3464 reg = AR_READ(sc, AR_PHY_FIND_SIG); 3465 reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4); 3466 AR_WRITE(sc, AR_PHY_FIND_SIG, reg); 3467 AR_WRITE_BARRIER(sc); 3468 } 3469 3470 Static void 3471 ar9003_set_spur_immunity_level(struct athn_softc *sc, int level) 3472 { 3473 uint32_t reg; 3474 3475 reg = AR_READ(sc, AR_PHY_TIMING5); 3476 reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2); 3477 AR_WRITE(sc, AR_PHY_TIMING5, reg); 3478 AR_WRITE_BARRIER(sc); 3479 } 3480
Indexes created Sun Sep 21 19:09:51 GMT 2025