| /src/sys/arch/arm/nxp/ |
| imx_ccm_composite.c | 86 const u_int post_div = __SHIFTOUT(val, TARGET_ROOT_POST_PODF) + 1; local in function:imx_ccm_composite_get_rate
88 return prate / pre_div / post_div;
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| /src/sys/arch/mips/atheros/ |
| ar9344.c | 123 uint32_t out_div, ref_div, nint, post_div; local in function:ar9344_get_freqs
162 post_div = __SHIFTOUT(clk_ctl,
165 freqs->freq_bus = ddr_pll_freq / (post_div + 1);
167 freqs->freq_bus = cpu_pll_freq / (post_div + 1);
170 post_div = __SHIFTOUT(clk_ctl,
173 freqs->freq_cpu = cpu_pll_freq / (post_div + 1);
176 freqs->freq_cpu = ddr_pll_freq / (post_div + 1);
180 post_div = __SHIFTOUT(clk_ctl,
183 freqs->freq_mem = ddr_pll_freq / (post_div + 1);
185 freqs->freq_mem = cpu_pll_freq / (post_div + 1)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_clocks.c | 48 uint32_t fb_div, ref_div, post_div, sclk; local in function:radeon_legacy_get_engine_clock
63 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
64 if (post_div == 2)
66 else if (post_div == 3)
68 else if (post_div == 4)
78 uint32_t fb_div, ref_div, post_div, mclk; local in function:radeon_legacy_get_memory_clock
93 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
94 if (post_div == 2)
96 else if (post_div == 3)
98 else if (post_div == 4
399 int fb_div, post_div; local in function:radeon_legacy_set_engine_clock
[all...] |
| radeon_legacy_crtc.c | 772 } *post_div, post_divs[] = { local in function:radeon_set_pll
838 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
839 if (post_div->divider == post_divider)
843 if (!post_div->divider)
844 post_div = &post_divs[0];
859 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
|
| radeon_legacy_tv.c | 861 int post_div; local in function:get_post_div
863 case 1: post_div = 0; break;
864 case 2: post_div = 1; break;
865 case 3: post_div = 4; break;
866 case 4: post_div = 2; break;
867 case 6: post_div = 6; break;
868 case 8: post_div = 3; break;
869 case 12: post_div = 7; break;
871 default: post_div = 5; break;
873 return post_div;
[all...] |
| radeon_rs780_dpm.c | 94 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
460 (min_dividers.post_div != max_dividers.post_div) ||
462 (max_dividers.post_div != current_max_dividers.post_div))
996 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + local in function:rs780_dpm_debugfs_print_current_performance_level
999 (post_div * ref_div);
1019 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + local in function:rs780_dpm_get_current_sclk
1022 (post_div * ref_div);
|
| radeon_uvd.c | 929 unsigned post_div = vco_freq / target_freq; local in function:radeon_uvd_calc_upll_post_div
932 if (post_div < pd_min)
933 post_div = pd_min;
936 if ((vco_freq / post_div) > target_freq)
937 post_div += 1;
940 if (post_div > pd_even && post_div % 2)
941 post_div += 1;
943 return post_div;
|
| radeon_atombios_crtc.c | 837 u32 post_div,
864 args.v1.ucPostDiv = post_div;
874 args.v2.ucPostDiv = post_div;
884 args.v3.ucPostDiv = post_div;
901 args.v5.ucPostDiv = post_div;
930 args.v6.ucPostDiv = post_div;
1077 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local in function:atombios_crtc_set_pll
1104 pll->post_div = radeon_crtc->pll_post_div;
1109 &fb_div, &frac_fb_div, &ref_div, &post_div);
1112 &fb_div, &frac_fb_div, &ref_div, &post_div);
[all...] |
| radeon_display.c | 913 * @post_div: post divider
922 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
927 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
930 *ref_div = min(max(den/post_div, 1u), ref_div_max);
931 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
951 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
965 unsigned post_div_min, post_div_max, post_div; local in function:radeon_compute_pll_avivo
996 post_div_min = pll->post_div;
997 post_div_max = pll->post_div;
1041 for (post_div = post_div_min; post_div <= post_div_max; ++post_div)
1128 uint32_t post_div; local in function:radeon_compute_pll_legacy
[all...] |
| radeon_mode.h | 173 uint32_t post_div; member in struct:radeon_pll
581 u32 post_div; member in struct:atom_clock_dividers
621 u32 post_div; member in struct:atom_mpll_param
|
| /src/sys/arch/arm/sunxi/ |
| sun9i_a80_cpusclk.c | 178 const u_int post_div = __SHIFTOUT(val, CPUS_POST_DIV); local in function:sun9i_a80_cpusclk_get_rate
183 rate /= (post_div + 1);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_pll.c | 81 * @post_div: post divider
90 static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
95 ref_div_max = min(128 / post_div, ref_div_max);
98 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
99 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
119 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
133 unsigned post_div_min, post_div_max, post_div; local in function:amdgpu_pll_compute
161 post_div_min = pll->post_div;
162 post_div_max = pll->post_div;
206 for (post_div = post_div_min; post_div <= post_div_max; ++post_div)
[all...] |
| amdgpu_atombios.h | 30 u32 post_div; member in struct:atom_clock_dividers
70 u32 post_div; member in struct:atom_mpll_param
|
| amdgpu_atombios_crtc.c | 591 u32 post_div,
618 args.v1.ucPostDiv = post_div;
628 args.v2.ucPostDiv = post_div;
638 args.v3.ucPostDiv = post_div;
655 args.v5.ucPostDiv = post_div;
685 args.v6.ucPostDiv = post_div;
832 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local in function:amdgpu_atombios_crtc_set_pll
858 pll->post_div = amdgpu_crtc->pll_post_div;
861 &fb_div, &frac_fb_div, &ref_div, &post_div);
868 ref_div, fb_div, frac_fb_div, post_div,
[all...] |
| amdgpu_mode.h | 198 uint32_t post_div; member in struct:amdgpu_pll
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_mcp77.c | 60 u32 post_div = 0; local in function:read_pll
66 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16);
69 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16;
79 clock = clock / post_div;
|
| /src/sys/arch/arm/broadcom/ |
| bcm53xx_board.c | 318 * F(ddr) = ((1 / pdiv) * ndiv * CH2) / (post_div * 2)
325 u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV); local in function:bcm53xx_get_ddr_freq
332 clk->clk_ddr = (clk->clk_ddr_ref / pdiv) * ndiv / (2 + post_div);
|
| /src/sys/dev/pci/ |
| machfb.c | 937 int post_div, dot_clock, vrefresh, vrefresh2; local in function:mach64_get_mode
971 post_div = 8;
974 post_div = 4;
977 post_div = 2;
980 post_div = 1;
983 dot_clock = (2 * ref_freq * vclk_fb_div) / (ref_div * post_div);
1408 DPRINTF("post_div: %d log2_post_div: %d mclk_div: %d\n",
|
