1 /* $NetBSD: sun9i_a80_cpusclk.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sun9i_a80_cpusclk.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/bus.h> 37 38 #include <dev/clk/clk_backend.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #define CPUS_CLK_SRC_SEL __BITS(17,16) 43 #define CPUS_CLK_SRC_SEL_PLL_PERIPH0 2 44 #define CPUS_POST_DIV __BITS(12,8) 45 #define CPUS_CLK_RATIO __BITS(5,4) 46 47 static int sun9i_a80_cpusclk_match(device_t, cfdata_t, void *); 48 static void sun9i_a80_cpusclk_attach(device_t, device_t, void *); 49 50 static struct clk *sun9i_a80_cpusclk_decode(device_t, int, const void *, size_t); 51 52 static const struct fdtbus_clock_controller_func sun9i_a80_cpusclk_fdt_funcs = { 53 .decode = sun9i_a80_cpusclk_decode 54 }; 55 56 static struct clk *sun9i_a80_cpusclk_get(void *, const char *); 57 static void sun9i_a80_cpusclk_put(void *, struct clk *); 58 static int sun9i_a80_cpusclk_set_rate(void *, struct clk *, u_int); 59 static u_int sun9i_a80_cpusclk_get_rate(void *, struct clk *); 60 static struct clk *sun9i_a80_cpusclk_get_parent(void *, struct clk *); 61 62 static const struct clk_funcs sun9i_a80_cpusclk_clk_funcs = { 63 .get = sun9i_a80_cpusclk_get, 64 .put = sun9i_a80_cpusclk_put, 65 .set_rate = sun9i_a80_cpusclk_set_rate, 66 .get_rate = sun9i_a80_cpusclk_get_rate, 67 .get_parent = sun9i_a80_cpusclk_get_parent, 68 }; 69 70 struct sun9i_a80_cpusclk_softc { 71 device_t sc_dev; 72 int sc_phandle; 73 bus_space_tag_t sc_bst; 74 bus_space_handle_t sc_bsh; 75 76 struct clk_domain sc_clkdom; 77 struct clk sc_clk; 78 }; 79 80 #define RD4(sc, reg) \ 81 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 82 #define WR4(sc, reg, val) \ 83 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 84 85 CFATTACH_DECL_NEW(sunxi_a80_cpusclk, sizeof(struct sun9i_a80_cpusclk_softc), 86 sun9i_a80_cpusclk_match, sun9i_a80_cpusclk_attach, NULL, NULL); 87 88 static const struct device_compatible_entry compat_data[] = { 89 { .compat = "allwinner,sun9i-a80-cpus-clk" }, 90 DEVICE_COMPAT_EOL 91 }; 92 93 static int 94 sun9i_a80_cpusclk_match(device_t parent, cfdata_t cf, void *aux) 95 { 96 const struct fdt_attach_args *faa = aux; 97 98 return of_compatible_match(faa->faa_phandle, compat_data); 99 } 100 101 static void 102 sun9i_a80_cpusclk_attach(device_t parent, device_t self, void *aux) 103 { 104 struct sun9i_a80_cpusclk_softc * const sc = device_private(self); 105 const struct fdt_attach_args *faa = aux; 106 const int phandle = faa->faa_phandle; 107 bus_addr_t addr; 108 bus_size_t size; 109 110 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 111 aprint_error(": couldn't get registers\n"); 112 return; 113 } 114 115 sc->sc_dev = self; 116 sc->sc_phandle = phandle; 117 sc->sc_bst = faa->faa_bst; 118 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 119 aprint_error(": couldn't map registers\n"); 120 return; 121 } 122 123 sc->sc_clkdom.funcs = &sun9i_a80_cpusclk_clk_funcs; 124 sc->sc_clkdom.priv = sc; 125 126 sc->sc_clk.domain = &sc->sc_clkdom; 127 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name); 128 129 aprint_naive("\n"); 130 aprint_normal(": A80 CPUS clock\n"); 131 132 fdtbus_register_clock_controller(self, phandle, &sun9i_a80_cpusclk_fdt_funcs); 133 } 134 135 static struct clk * 136 sun9i_a80_cpusclk_decode(device_t dev, int cc_phandle, const void *data, 137 size_t len) 138 { 139 struct sun9i_a80_cpusclk_softc * const sc = device_private(dev); 140 141 if (len != 0) 142 return NULL; 143 144 return &sc->sc_clk; 145 } 146 147 static struct clk * 148 sun9i_a80_cpusclk_get(void *priv, const char *name) 149 { 150 struct sun9i_a80_cpusclk_softc * const sc = priv; 151 152 if (strcmp(name, sc->sc_clk.name) != 0) 153 return NULL; 154 155 return &sc->sc_clk; 156 } 157 158 static void 159 sun9i_a80_cpusclk_put(void *priv, struct clk *clk) 160 { 161 } 162 163 static int 164 sun9i_a80_cpusclk_set_rate(void *priv, struct clk *clk, u_int rate) 165 { 166 return ENXIO; 167 } 168 169 static u_int 170 sun9i_a80_cpusclk_get_rate(void *priv, struct clk *clk) 171 { 172 struct sun9i_a80_cpusclk_softc * const sc = priv; 173 struct clk *clk_parent = clk_get_parent(clk); 174 u_int rate; 175 176 const uint32_t val = RD4(sc, 0); 177 const u_int sel = __SHIFTOUT(val, CPUS_CLK_SRC_SEL); 178 const u_int post_div = __SHIFTOUT(val, CPUS_POST_DIV); 179 const u_int clk_ratio = __SHIFTOUT(val, CPUS_CLK_RATIO); 180 181 rate = clk_get_rate(clk_parent) / (clk_ratio + 1); 182 if (sel == CPUS_CLK_SRC_SEL_PLL_PERIPH0) 183 rate /= (post_div + 1); 184 185 return rate; 186 } 187 188 static struct clk * 189 sun9i_a80_cpusclk_get_parent(void *priv, struct clk *clk) 190 { 191 struct sun9i_a80_cpusclk_softc * const sc = priv; 192 193 const uint32_t val = RD4(sc, 0); 194 const u_int sel = __SHIFTOUT(val, CPUS_CLK_SRC_SEL); 195 196 return fdtbus_clock_get_index(sc->sc_phandle, sel); 197 } 198
Indexes created Thu Sep 25 15:09:46 GMT 2025