1 /* 2 * Copyright 2009 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Zhenyu Wang <zhenyu.z.wang (at) intel.com> 25 * Wu Fengguang <fengguang.wu (at) intel.com> 26 * 27 */ 28 29 #include <stdio.h> 30 #include <stdlib.h> 31 #include <string.h> 32 #include <stdarg.h> 33 #include <sys/types.h> 34 #include <sys/mman.h> 35 #include <pciaccess.h> 36 #include <err.h> 37 #include <unistd.h> 38 #include <fcntl.h> 39 #include <getopt.h> 40 41 42 #include "reg_dumper.h" 43 #include "../i810_reg.h" 44 45 #define dump_reg(reg, desc) \ 46 do { \ 47 dword = INREG(reg); \ 48 printf("%-18s 0x%08x %s\n", # reg, dword, desc); \ 49 } while (0) 50 51 #define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1) 52 #define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low)) 53 #define BITS(reg, high, low) (((reg) & (BITMASK(high, low))) >> (low)) 54 #define BIT(reg, n) BITS(reg, n, n) 55 56 #define AUD_CONFIG 0x62000 57 #define AUD_DEBUG 0x62010 58 #define AUD_VID_DID 0x62020 59 #define AUD_RID 0x62024 60 #define AUD_SUBN_CNT 0x62028 61 #define AUD_FUNC_GRP 0x62040 62 #define AUD_SUBN_CNT2 0x62044 63 #define AUD_GRP_CAP 0x62048 64 #define AUD_PWRST 0x6204c 65 #define AUD_SUPPWR 0x62050 66 #define AUD_SID 0x62054 67 #define AUD_OUT_CWCAP 0x62070 68 #define AUD_OUT_PCMSIZE 0x62074 69 #define AUD_OUT_STR 0x62078 70 #define AUD_OUT_DIG_CNVT 0x6207c 71 #define AUD_OUT_CH_STR 0x62080 72 #define AUD_OUT_STR_DESC 0x62084 73 #define AUD_PINW_CAP 0x620a0 74 #define AUD_PIN_CAP 0x620a4 75 #define AUD_PINW_CONNLNG 0x620a8 76 #define AUD_PINW_CONNLST 0x620ac 77 #define AUD_PINW_CNTR 0x620b0 78 #define AUD_PINW_UNSOLRESP 0x620b8 79 #define AUD_CNTL_ST 0x620b4 80 #define AUD_PINW_CONFIG 0x620bc 81 #define AUD_HDMIW_STATUS 0x620d4 82 #define AUD_HDMIW_HDMIEDID 0x6210c 83 #define AUD_HDMIW_INFOFR 0x62118 84 #define AUD_CONV_CHCNT 0x62120 85 #define AUD_CTS_ENABLE 0x62128 86 87 #define VIDEO_DIP_CTL 0x61170 88 #define VIDEO_DIP_ENABLE (1<<31) 89 #define VIDEO_DIP_ENABLE_AVI (1<<21) 90 #define VIDEO_DIP_ENABLE_VENDOR (1<<22) 91 #define VIDEO_DIP_ENABLE_SPD (1<<24) 92 #define VIDEO_DIP_BUF_AVI (0<<19) 93 #define VIDEO_DIP_BUF_VENDOR (1<<19) 94 #define VIDEO_DIP_BUF_SPD (3<<19) 95 #define VIDEO_DIP_TRANS_ONCE (0<<16) 96 #define VIDEO_DIP_TRANS_1 (1<<16) 97 #define VIDEO_DIP_TRANS_2 (2<<16) 98 99 #define AUDIO_HOTPLUG_EN (1<<24) 100 101 #define min_t(type, x, y) ({ \ 102 type __min1 = (x); \ 103 type __min2 = (y); \ 104 __min1 < __min2 ? __min1: __min2; }) 105 106 #define OPNAME(names, index) \ 107 names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)] 108 109 static char *pixel_clock[] = { 110 [0] = "25.2 / 1.001 MHz", 111 [1] = "25.2 MHz", 112 [2] = "27 MHz", 113 [3] = "27 * 1.001 MHz", 114 [4] = "54 MHz", 115 [5] = "54 * 1.001 MHz", 116 [6] = "74.25 / 1.001 MHz", 117 [7] = "74.25 MHz", 118 [8] = "148.5 / 1.001 MHz", 119 [9] = "148.5 MHz", 120 [10] = "Reserved", 121 }; 122 123 static char *power_state[] = { 124 [0] = "D0", 125 [1] = "D1", 126 [2] = "D2", 127 [3] = "D3", 128 }; 129 130 static char *stream_type[] = { 131 [0] = "default samples", 132 [1] = "one bit stream", 133 [2] = "DST stream", 134 [3] = "MLP stream", 135 [4] = "Reserved", 136 }; 137 138 static char *dip_port[] = { 139 [0] = "Reserved", 140 [1] = "HDMI B", 141 [2] = "HDMI C", 142 [3] = "Reserved", 143 }; 144 145 static char *dip_index[] = { 146 [0] = "Audio DIP", 147 [1] = "ACP DIP", 148 [2] = "ISRC1 DIP", 149 [3] = "ISRC2 DIP", 150 [4] = "Reserved", 151 }; 152 153 static char *dip_trans[] = { 154 [0] = "disabled", 155 [1] = "reserved", 156 [2] = "send once", 157 [3] = "best effort", 158 }; 159 160 static char *video_dip_index[] = { 161 [0] = "AVI DIP", 162 [1] = "Vendor-specific DIP", 163 [2] = "Reserved", 164 [3] = "Source Product Description DIP", 165 }; 166 167 static char *video_dip_trans[] = { 168 [0] = "send once", 169 [1] = "send every vsync", 170 [2] = "send at least every other vsync", 171 [3] = "reserved", 172 }; 173 174 static void do_self_tests(void) 175 { 176 if (BIT(1, 0) != 1) 177 exit(1); 178 if (BIT(0x80000000, 31) != 1) 179 exit(2); 180 if (BITS(0xc0000000, 31, 30) != 3) 181 exit(3); 182 } 183 184 int main(int argc, char **argv) 185 { 186 I830Rec i830; 187 I830Ptr pI830 = &i830; 188 uint32_t dword; 189 int i; 190 191 do_self_tests(); 192 intel_i830rec_init(pI830); 193 194 /* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */ 195 196 #if 0 /* enable HDMI audio bits */ 197 dump_reg(SDVOB, "Digital Display Port B Control Register"); 198 dword |= SDVO_ENABLE; 199 dword |= SDVO_BORDER_ENABLE; 200 dword |= SDVO_AUDIO_ENABLE; 201 dword |= SDVO_NULL_PACKETS_DURING_VSYNC; 202 OUTREG(SDVOB, dword); 203 204 dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable"); 205 OUTREG(PORT_HOTPLUG_EN, dword | AUDIO_HOTPLUG_EN); 206 207 dump_reg(VIDEO_DIP_CTL, "Video DIP Control"); 208 dword &= ~( VIDEO_DIP_ENABLE_AVI | 209 VIDEO_DIP_ENABLE_VENDOR | 210 VIDEO_DIP_ENABLE_SPD); 211 OUTREG(VIDEO_DIP_CTL, dword); 212 dword |= VIDEO_DIP_ENABLE; 213 OUTREG(VIDEO_DIP_CTL, dword); 214 #endif 215 216 #if 0 /* disable HDMI audio bits */ 217 dump_reg(SDVOB, "Digital Display Port B Control Register"); 218 dword &= ~SDVO_AUDIO_ENABLE; 219 dword &= ~SDVO_NULL_PACKETS_DURING_VSYNC; 220 OUTREG(SDVOB, dword); 221 #endif 222 223 dump_reg(VIDEO_DIP_CTL, "Video DIP Control"); 224 dump_reg(SDVOB, "Digital Display Port B Control Register"); 225 dump_reg(SDVOC, "Digital Display Port C Control Register"); 226 dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable"); 227 228 dump_reg(AUD_CONFIG, "Audio Configuration"); 229 dump_reg(AUD_DEBUG, "Audio Debug"); 230 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID"); 231 dump_reg(AUD_RID, "Audio Revision ID"); 232 dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count"); 233 dump_reg(AUD_FUNC_GRP, "Audio Function Group Type"); 234 dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count"); 235 dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities"); 236 dump_reg(AUD_PWRST, "Audio Power State"); 237 dump_reg(AUD_SUPPWR, "Audio Supported Power States"); 238 dump_reg(AUD_SID, "Audio Root Node Subsystem ID"); 239 dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities"); 240 dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates"); 241 dump_reg(AUD_OUT_STR, "Audio Stream Formats"); 242 dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter"); 243 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID"); 244 dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format"); 245 dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities"); 246 dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities"); 247 dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length"); 248 dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry"); 249 dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control"); 250 dump_reg(AUD_PINW_UNSOLRESP,"Audio Unsolicited Response Enable"); 251 dump_reg(AUD_CNTL_ST, "Audio Control State Register"); 252 dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default"); 253 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status"); 254 dump_reg(AUD_HDMIW_HDMIEDID,"Audio HDMI Data EDID Block"); 255 dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet"); 256 dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count"); 257 dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable"); 258 259 printf("\nDetails:\n\n"); 260 261 dword = INREG(AUD_VID_DID); 262 printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16); 263 printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff); 264 265 dword = INREG(AUD_RID); 266 printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20)); 267 printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16)); 268 printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8)); 269 printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0)); 270 271 dword = INREG(SDVOB); 272 printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE)); 273 printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI)); 274 printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO)); 275 printf("SDVOB null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC)); 276 printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE)); 277 278 dword = INREG(SDVOC); 279 printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE)); 280 printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI)); 281 printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO)); 282 printf("SDVOC null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC)); 283 printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE)); 284 285 dword = INREG(PORT_HOTPLUG_EN); 286 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)), 287 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)), 288 printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)), 289 printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)), 290 printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)), 291 printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)), 292 printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)), 293 printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)), 294 295 dword = INREG(VIDEO_DIP_CTL); 296 printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)), 297 printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n", 298 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]); 299 printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28)); 300 printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21)); 301 printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22)); 302 printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24)); 303 printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n", 304 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]); 305 printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n", 306 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]); 307 printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8)); 308 printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0)); 309 310 dword = INREG(AUD_CONFIG); 311 printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16), 312 OPNAME(pixel_clock, BITS(dword, 19, 16))); 313 printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2)); 314 printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1)); 315 printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0)); 316 317 dword = INREG(AUD_DEBUG); 318 printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0)); 319 320 dword = INREG(AUD_SUBN_CNT); 321 printf("AUD_SUBN_CNT starting node number\t0x%lx\n", BITS(dword, 23, 16)); 322 printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", BITS(dword, 7, 0)); 323 324 dword = INREG(AUD_SUBN_CNT2); 325 printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n", BITS(dword, 24, 16)); 326 printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", BITS(dword, 7, 0)); 327 328 dword = INREG(AUD_FUNC_GRP); 329 printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8)); 330 printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0)); 331 332 dword = INREG(AUD_GRP_CAP); 333 printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16)); 334 printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8)); 335 printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0)); 336 337 dword = INREG(AUD_PWRST); 338 printf("AUD_PWRST device power state\t\t%s\n", 339 power_state[BITS(dword, 5, 4)]); 340 printf("AUD_PWRST device power state setting\t%s\n", 341 power_state[BITS(dword, 1, 0)]); 342 343 dword = INREG(AUD_SUPPWR); 344 printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0)); 345 printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1)); 346 printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2)); 347 printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3)); 348 349 dword = INREG(AUD_OUT_CWCAP); 350 printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20)); 351 printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16)); 352 printf("AUD_OUT_CWCAP channel count\t\t%lu\n", 353 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1); 354 printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11)); 355 printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10)); 356 printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9)); 357 printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8)); 358 printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7)); 359 printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5)); 360 printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4)); 361 printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3)); 362 printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2)); 363 printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1)); 364 365 dword = INREG(AUD_OUT_DIG_CNVT); 366 printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", BITS(dword, 14, 8)); 367 printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7)); 368 printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6)); 369 printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5)); 370 printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4)); 371 printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3)); 372 printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2)); 373 printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1)); 374 printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0)); 375 376 dword = INREG(AUD_OUT_CH_STR); 377 printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4)); 378 printf("AUD_OUT_CH_STR lowest channel\t\t0x%lx\n", BITS(dword, 3, 0)); 379 380 dword = INREG(AUD_OUT_STR_DESC); 381 printf("AUD_OUT_STR_DESC stream channels\t0x%lx\n", BITS(dword, 3, 0)); 382 383 dword = INREG(AUD_PINW_CAP); 384 printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20)); 385 printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16)); 386 printf("AUD_PINW_CAP channel count\t\t0x%lx\n", 387 BITS(dword, 15, 13) * 2 + BIT(dword, 0)); 388 printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12)); 389 printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11)); 390 printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10)); 391 printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9)); 392 printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8)); 393 printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7)); 394 printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5)); 395 printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4)); 396 printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3)); 397 printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2)); 398 printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1)); 399 400 401 dword = INREG(AUD_PIN_CAP); 402 printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16)); 403 printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7)); 404 printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4)); 405 printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2)); 406 407 dword = INREG(AUD_PINW_CNTR); 408 printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8)); 409 printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6)); 410 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8)); 411 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8)); 412 printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n", 413 BITS(dword, 2, 0), 414 OPNAME(stream_type, BITS(dword, 2, 0))); 415 416 dword = INREG(AUD_PINW_UNSOLRESP); 417 printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31)); 418 419 dword = INREG(AUD_CNTL_ST); 420 printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21)); 421 printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22)); 422 printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23)); 423 printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n", 424 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]); 425 printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n", 426 BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18))); 427 printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n", 428 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]); 429 printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0)); 430 printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15)); 431 printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14)); 432 printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4)); 433 printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9)); 434 printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5)); 435 436 dword = INREG(AUD_HDMIW_STATUS); 437 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31)); 438 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30)); 439 printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29)); 440 printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28)); 441 442 dword = INREG(AUD_CONV_CHCNT); 443 printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14)); 444 printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", BITS(dword, 11, 8) + 1); 445 446 printf("AUD_CONV_CHCNT HDMI channel mapping:\n"); 447 for (i = 0; i < 8; i++) { 448 OUTREG(AUD_CONV_CHCNT, i); 449 dword = INREG(AUD_CONV_CHCNT); 450 printf("\t\t\t\t\t[0x%x] %u => %lu \n", dword, i, BITS(dword, 7, 4)); 451 } 452 453 return 0; 454 } 455
Indexes created Thu Jul 23 00:25:05 UTC 2026