1 /* $NetBSD: if_ed_zbus.c,v 1.2 2012/10/27 21:13:03 phx Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank Wille. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Hydra Systems and ASDG ethernet cards. 34 * Based on the National Semiconductor DS8390/WD83C690. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_ed_zbus.c,v 1.2 2012/10/27 21:13:03 phx Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/device.h> 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_media.h> 46 #include <net/if_ether.h> 47 48 #include <dev/ic/dp8390reg.h> 49 #include <dev/ic/dp8390var.h> 50 51 #include <amiga/amiga/device.h> 52 #include <amiga/amiga/isr.h> 53 #include <amiga/dev/zbusvar.h> 54 55 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 56 57 /* Hydra Systems AmigaNet */ 58 #define HYDRA_MANID 2121 59 #define HYDRA_PRODID 1 60 #define HYDRA_REGADDR 0xffe1 61 #define HYDRA_MEMADDR 0 62 #define HYDRA_PROMADDR 0xffc0 63 64 /* ASDG LANRover */ 65 #define ASDG_MANID 1023 66 #define ASDG_PRODID 254 67 #define ASDG_REGADDR 0x1 68 #define ASDG_MEMADDR 0x8000 69 #define ASDG_PROMADDR 0x100 70 71 /* Buffer size is always 16k */ 72 #define ED_ZBUS_MEMSIZE 0x4000 73 74 int ed_zbus_match(device_t, cfdata_t , void *); 75 void ed_zbus_attach(device_t, device_t, void *); 76 int ed_zbus_test_mem(struct dp8390_softc *); 77 void ed_zbus_read_hdr(struct dp8390_softc *, int, struct dp8390_ring *); 78 int ed_zbus_ring_copy(struct dp8390_softc *, int, void *, u_short); 79 int ed_zbus_write_mbuf(struct dp8390_softc *, struct mbuf *, int); 80 81 struct ed_zbus_softc { 82 struct dp8390_softc sc_dp8390; 83 struct bus_space_tag sc_bst; 84 struct isr sc_isr; 85 }; 86 87 CFATTACH_DECL_NEW(ed_zbus, sizeof(struct ed_zbus_softc), 88 ed_zbus_match, ed_zbus_attach, NULL, NULL); 89 90 91 int 92 ed_zbus_match(device_t parent, cfdata_t cf, void *aux) 93 { 94 struct zbus_args *zap = aux; 95 96 if (zap->manid == HYDRA_MANID && zap->prodid == HYDRA_PRODID) 97 return 1; 98 else if (zap->manid == ASDG_MANID && zap->prodid == ASDG_PRODID) 99 return 1; 100 return 0; 101 } 102 103 void 104 ed_zbus_attach(device_t parent, device_t self, void *aux) 105 { 106 struct ed_zbus_softc *zsc = device_private(self); 107 struct dp8390_softc *sc = &zsc->sc_dp8390; 108 struct zbus_args *zap = aux; 109 bus_space_handle_t promh; 110 bus_addr_t memaddr, promaddr, regaddr; 111 int i; 112 113 zsc->sc_bst.base = (bus_addr_t)zap->va; 114 zsc->sc_bst.absm = &amiga_bus_stride_1; 115 116 if (zap->manid == HYDRA_MANID) { 117 regaddr = HYDRA_REGADDR; 118 memaddr = HYDRA_MEMADDR; 119 promaddr = HYDRA_PROMADDR; 120 } else { 121 regaddr = ASDG_REGADDR; 122 memaddr = ASDG_MEMADDR; 123 promaddr = ASDG_PROMADDR; 124 } 125 126 sc->sc_dev = self; 127 sc->sc_regt = &zsc->sc_bst; 128 sc->sc_buft = &zsc->sc_bst; 129 130 if (bus_space_map(sc->sc_regt, regaddr, 0x20, 0, &sc->sc_regh)) { 131 aprint_error_dev(self, "can't map i/o space\n"); 132 return; 133 } 134 135 if (bus_space_map(sc->sc_buft, memaddr, ED_ZBUS_MEMSIZE, 0, 136 &sc->sc_bufh)) { 137 aprint_error_dev(self, "can't map buffer space\n"); 138 return; 139 } 140 141 /* SRAM buffer size is always 16K */ 142 sc->mem_start = 0; 143 sc->mem_size = ED_ZBUS_MEMSIZE; 144 145 /* 146 * Read the ethernet address from the PROM. 147 * Interrupts must be inactive when reading the PROM, as the 148 * interrupt line is shared with one of its address lines. 149 */ 150 151 NIC_PUT(sc->sc_regt, sc->sc_regh, ED_P0_IMR, 0x00); 152 NIC_PUT(sc->sc_regt, sc->sc_regh, ED_P0_ISR, 0xff); 153 154 if (bus_space_map(&zsc->sc_bst, promaddr, ETHER_ADDR_LEN * 2, 0, 155 &promh) == 0) { 156 for (i = 0; i < ETHER_ADDR_LEN; i++) 157 sc->sc_enaddr[i] = 158 bus_space_read_1(&zsc->sc_bst, promh, i * 2); 159 160 bus_space_unmap(&zsc->sc_bst, promh, ETHER_ADDR_LEN * 2); 161 } 162 163 /* Initialize sc_reg_map[]. Registers have stride 2 on the bus. */ 164 for (i = 0; i < 16; i++) 165 sc->sc_reg_map[i] = i << 1; 166 167 /* 168 * Set 2 word FIFO threshold, no auto-init Remote DMA, 169 * byte order 68k, word-wide DMA xfers. 170 */ 171 sc->dcr_reg = ED_DCR_FT0 | ED_DCR_WTS | ED_DCR_LS | ED_DCR_BOS; 172 173 /* Remote DMA abort .*/ 174 sc->cr_proto = ED_CR_RD2; 175 176 /* 177 * Override all functions which deal with the buffer, because 178 * this implementation only allows 16-bit buffer accesses. 179 */ 180 sc->test_mem = ed_zbus_test_mem; 181 sc->read_hdr = ed_zbus_read_hdr; 182 sc->ring_copy = ed_zbus_ring_copy; 183 sc->write_mbuf = ed_zbus_write_mbuf; 184 185 sc->sc_flags = device_cfdata(self)->cf_flags; 186 sc->is790 = 0; 187 sc->sc_media_init = dp8390_media_init; 188 sc->sc_enabled = 1; 189 190 /* Do generic DS8390/WD83C690 config. */ 191 if (dp8390_config(sc)) { 192 bus_space_unmap(sc->sc_buft, sc->sc_bufh, ED_ZBUS_MEMSIZE); 193 bus_space_unmap(sc->sc_regt, sc->sc_regh, 0x10); 194 return; 195 } 196 197 /* establish level 2 interrupt handler */ 198 zsc->sc_isr.isr_intr = dp8390_intr; 199 zsc->sc_isr.isr_arg = sc; 200 zsc->sc_isr.isr_ipl = 2; 201 add_isr(&zsc->sc_isr); 202 } 203 204 int 205 ed_zbus_test_mem(struct dp8390_softc *sc) 206 { 207 bus_space_tag_t buft = sc->sc_buft; 208 bus_space_handle_t bufh = sc->sc_bufh; 209 int i; 210 211 bus_space_set_region_2(buft, bufh, sc->mem_start, 0, 212 sc->mem_size >> 1); 213 214 for (i = 0; i < sc->mem_size; i += 2) { 215 if (bus_space_read_2(sc->sc_buft, sc->sc_bufh, i)) { 216 printf(": failed to clear NIC buffer at offset %x - " 217 "check configuration\n", (sc->mem_start + i)); 218 return 1; 219 } 220 } 221 return 0; 222 } 223 224 void 225 ed_zbus_read_hdr(struct dp8390_softc *sc, int src, struct dp8390_ring *hdrp) 226 { 227 bus_space_tag_t buft = sc->sc_buft; 228 bus_space_handle_t bufh = sc->sc_bufh; 229 uint16_t wrd[2]; 230 231 /* 232 * Read the 4-byte header as two 16-bit words in little-endian 233 * format. Convert into big-endian and put them into hdrp. 234 */ 235 bus_space_read_region_stream_2(buft, bufh, src, wrd, 2); 236 hdrp->rsr = wrd[0] & 0xff; 237 hdrp->next_packet = wrd[0] >> 8; 238 hdrp->count = bswap16(wrd[1]); 239 } 240 241 /* 242 * Copy `amount' bytes from a packet in the ring buffer to a linear 243 * destination buffer, given a source offset and destination address. 244 * Takes into account ring-wrap. 245 */ 246 int 247 ed_zbus_ring_copy(struct dp8390_softc *sc, int src, void *dst, u_short amount) 248 { 249 bus_space_tag_t buft = sc->sc_buft; 250 bus_space_handle_t bufh = sc->sc_bufh; 251 u_short tmp_amount; 252 u_char readbyte[2]; 253 254 /* Does copy wrap to lower addr in ring buffer? */ 255 if (src + amount > sc->mem_end) { 256 tmp_amount = sc->mem_end - src; 257 258 /* copy amount up to end of NIC memory */ 259 bus_space_read_region_stream_2(buft, bufh, src, dst, 260 tmp_amount >> 1); 261 262 amount -= tmp_amount; 263 src = sc->mem_ring; 264 dst = (u_char *)dst + tmp_amount; 265 } 266 267 bus_space_read_region_stream_2(buft, bufh, src, dst, amount >> 1); 268 269 /* handle odd length packet */ 270 if (amount & 1) { 271 bus_space_read_region_stream_2(buft, bufh, src + amount - 1, 272 (u_int16_t *)readbyte, 1); 273 *((u_char *)dst + amount - 1) = readbyte[0]; 274 amount++; 275 } 276 277 return src + amount; 278 } 279 280 /* 281 * Copy packet from mbuf to the board memory. Currently uses an extra 282 * buffer/extra memory copy, unless the whole packet fits in one mbuf. 283 * As in the test_mem function, we use word-wide writes. 284 */ 285 int 286 ed_zbus_write_mbuf(struct dp8390_softc *sc, struct mbuf *m, int buf) 287 { 288 u_char *data, savebyte[2]; 289 int len, wantbyte; 290 u_short totlen = 0; 291 292 wantbyte = 0; 293 294 for (; m ; m = m->m_next) { 295 data = mtod(m, u_char *); 296 len = m->m_len; 297 totlen += len; 298 if (len > 0) { 299 /* Finish the last word. */ 300 if (wantbyte) { 301 savebyte[1] = *data; 302 bus_space_write_region_stream_2(sc->sc_buft, 303 sc->sc_bufh, buf, 304 (u_int16_t *)savebyte, 1); 305 buf += 2; 306 data++; 307 len--; 308 wantbyte = 0; 309 } 310 /* Output contiguous words. */ 311 if (len > 1) { 312 bus_space_write_region_stream_2(sc->sc_buft, 313 sc->sc_bufh, buf, 314 (u_int16_t *)data, len >> 1); 315 buf += len & ~1; 316 data += len & ~1; 317 len &= 1; 318 } 319 /* Save last byte, if necessary. */ 320 if (len == 1) { 321 savebyte[0] = *data; 322 wantbyte = 1; 323 } 324 } 325 } 326 327 len = ETHER_PAD_LEN - totlen; 328 if (wantbyte) { 329 savebyte[1] = 0; 330 bus_space_write_region_stream_2(sc->sc_buft, sc->sc_bufh, 331 buf, (u_int16_t *)savebyte, 1); 332 buf += 2; 333 totlen++; 334 len--; 335 } 336 /* if sent data is shorter than EHTER_PAD_LEN, put 0 to padding */ 337 if (len > 0) { 338 bus_space_set_region_2(sc->sc_buft, sc->sc_bufh, buf, 0, 339 len >> 1); 340 totlen = ETHER_PAD_LEN; 341 } 342 return totlen; 343 } 344
Indexes created Mon Sep 22 21:09:42 GMT 2025