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  /src/external/gpl3/gdb/dist/sim/testsuite/bfin/
ashift_left.s 9 r1 = r0 >>> \shift \opt; define
10 CHECKREG r1, \out;
add_shift.S 9 r1=0;
10 ASTAT = R1;
13 r2=(r2+r1)<<2;
22 r2=(r2+r1)<<1;
29 r1=0;
30 r1.h=0xd300;
33 r2=(r2+r1)<<1;
45 r1 = r0; define
46 _dbg r1;
47 r1 = (r1 + r0) << 1; // add overflows to zero, no shift overflo define
    [all...]
cmpdreg.S 11 r1 = 0; define
12 r1.h =0x8000;
13 cc = r1==r0;
22 r1.l = 0xffff;
23 r1.h =0x7fff;
24 cc = r1==r0;
33 r1.l = 0xffff;
34 r1.h =0x7fff;
35 cc = r1==r0;
divq.s 13 * r1 = divisor, or denominator
19 r1 = \den (Z); define
25 divs (r0, r1);
30 divq (r0, r1);
35 imm32 r1, (\num / \den);
36 CC = r0 == r1
10436.s 8 r1 = i0; define
22 CC = R0 == R1;
29 CC = R0 == R1;
c_compi2opd_flags_2.S 21 R1 = R0;
27 CHECKREG r1, 0x00000000;
38 R1 = R0;
44 CHECKREG r1, 0x00000000;
53 R1 = R0;
60 CHECKREG r1, 0x80000000;
72 R1 = R0;
79 CHECKREG r1, 0x7FFFFFFF;
86 imm32 r1, 0x00000000;
87 ASTAT = R1;
108 r1 = 0; define
    [all...]
load.s 21 r1 = \preg define
22 cc = r0 == r1
40 imm32 r1 \num;
42 cc = r0 == r1
85 load32 0 R0 R1
86 load32 0xFFFFFFFF R0 R1
87 load32 0x55aaaa55 r0 r1
88 load32 0x12345678 r0 r1
96 load32 0x89abcdef R1 R0
134 load16z 0x1234 R0 R1
    [all...]
msa_acp_5.12_2.S 24 r1 = 1; define
27 a1 = r1;
42 r1 = 0; define
45 a0 = r1;
  /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
ashift_left.s 9 r1 = r0 >>> \shift \opt; define
10 CHECKREG r1, \out;
add_shift.S 9 r1=0;
10 ASTAT = R1;
13 r2=(r2+r1)<<2;
22 r2=(r2+r1)<<1;
29 r1=0;
30 r1.h=0xd300;
33 r2=(r2+r1)<<1;
45 r1 = r0; define
46 _dbg r1;
47 r1 = (r1 + r0) << 1; // add overflows to zero, no shift overflo define
    [all...]
cmpdreg.S 11 r1 = 0; define
12 r1.h =0x8000;
13 cc = r1==r0;
22 r1.l = 0xffff;
23 r1.h =0x7fff;
24 cc = r1==r0;
33 r1.l = 0xffff;
34 r1.h =0x7fff;
35 cc = r1==r0;
divq.s 13 * r1 = divisor, or denominator
19 r1 = \den (Z); define
25 divs (r0, r1);
30 divq (r0, r1);
35 imm32 r1, (\num / \den);
36 CC = r0 == r1
10436.s 8 r1 = i0; define
22 CC = R0 == R1;
29 CC = R0 == R1;
c_compi2opd_flags_2.S 21 R1 = R0;
27 CHECKREG r1, 0x00000000;
38 R1 = R0;
44 CHECKREG r1, 0x00000000;
53 R1 = R0;
60 CHECKREG r1, 0x80000000;
72 R1 = R0;
79 CHECKREG r1, 0x7FFFFFFF;
86 imm32 r1, 0x00000000;
87 ASTAT = R1;
108 r1 = 0; define
    [all...]
load.s 21 r1 = \preg define
22 cc = r0 == r1
40 imm32 r1 \num;
42 cc = r0 == r1
85 load32 0 R0 R1
86 load32 0xFFFFFFFF R0 R1
87 load32 0x55aaaa55 r0 r1
88 load32 0x12345678 r0 r1
96 load32 0x89abcdef R1 R0
134 load16z 0x1234 R0 R1
    [all...]
msa_acp_5.12_2.S 24 r1 = 1; define
27 a1 = r1;
42 r1 = 0; define
45 a0 = r1;
  /src/external/bsd/libarchive/dist/libarchive/
archive_read_set_format.c 39 int r1, r2, slots, i; local
43 if ((r1 = archive_read_support_format_by_code(_a, code)) < (ARCHIVE_OK))
44 return r1;
46 r1 = r2 = (ARCHIVE_OK);
112 r1 = (ARCHIVE_FATAL);
115 return (r1 < r2) ? r1 : r2;
  /src/external/lgpl3/gmp/dist/mpn/generic/
div_qr_2n_pi1.c 49 mp_limb_t r1, r0; local
55 r1 = np[1];
59 if (r1 >= d1 && (r1 > d1 || r0 >= d0))
62 sub_ddmmss (r1, r0, r1, r0, d1, d0);
65 r1 = r1 - d1 - (r0 >> GMP_LIMB_BITS - 1);
75 udiv_qr_3by2 (q, r1, r0, r1, r0, n0, d1, d0, di)
    [all...]
div_qr_2u_pi1.c 49 mp_limb_t r2, r1, r0; local
57 r1 = (np[nn-1] << shift) | (np[nn-2] >> (GMP_LIMB_BITS - shift));
60 udiv_qr_3by2 (qh, r2, r1, r2, r1, r0, d1, d0, di);
66 r1 |= r0 >> (GMP_LIMB_BITS - shift);
68 udiv_qr_3by2 (q, r2, r1, r2, r1, r0, d1, d0, di);
72 rp[0] = (r1 >> shift) | (r2 << (GMP_LIMB_BITS - shift));
divrem_2.c 61 mp_limb_t r1, r0, d1, d0; local
74 r1 = np[1];
78 if (r1 >= d1 && (r1 > d1 || r0 >= d0))
81 sub_ddmmss (r1, r0, r1, r0, d1, d0);
84 r1 = r1 - d1 - (r0 >> GMP_LIMB_BITS - 1);
98 udiv_qr_3by2 (q, r1, r0, r1, r0, n0, d1, d0, di.inv32)
    [all...]
  /src/sys/arch/acorn32/stand/nbfs/
nbfs.h 8 uint32_t r0, r1, r2, r3, r4, r5, r6, r7; member in struct:nbfs_reg
  /src/sys/arch/m68k/fpe/
fpu_add.c 64 uint32_t r0, r1, r2; local
173 FPU_SUBCS(r1, x->fp_mant[1], y->fp_mant[1]);
177 if ((r0 | r1 | r2) == 0) {
196 FPU_SUBCS(r1, 0, r1);
200 r->fp_mant[1] = r1;
  /src/sys/arch/powerpc/fpu/
fpu_add.c 69 u_int r0, r1, r2, r3; local
196 FPU_SUBCS(r1, x->fp_mant[1], y->fp_mant[1]);
200 if ((r0 | r1 | r2 | r3) == 0) {
220 FPU_SUBCS(r1, 0, r1);
225 r->fp_mant[1] = r1;
  /src/sys/arch/sparc/fpu/
fpu_add.c 68 u_int r0, r1, r2, r3; local
179 FPU_SUBCS(r1, x->fp_mant[1], y->fp_mant[1]);
183 if ((r0 | r1 | r2 | r3) == 0) {
203 FPU_SUBCS(r1, 0, r1);
208 r->fp_mant[1] = r1;
  /src/external/lgpl3/gmp/dist/tests/rand/
t-mt.c 36 gmp_randstate_t r1, r2; local
44 gmp_randinit_mt (r1);
50 mpz_urandomb (a, r1, 19936L);
59 gmp_randclear (r1);

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1 2 3 4 5 6 7 8 91011>>