1 /* $NetBSD: ralink_gpio.c,v 1.14 2022/02/12 15:51:29 thorpej Exp $ */ 2 /*- 3 * Copyright (c) 2011 CradlePoint Technology, Inc. 4 * All rights reserved. 5 * 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* ra_gpio.c -- Ralink 3052 gpio driver */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ralink_gpio.c,v 1.14 2022/02/12 15:51:29 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/callout.h> 37 #include <sys/device.h> 38 #include <sys/event.h> 39 #include <sys/intr.h> 40 #include <sys/kernel.h> 41 #include <sys/systm.h> 42 43 #include <dev/cons.h> 44 45 #include <mips/cpuregs.h> 46 #include <sys/gpio.h> 47 #include <dev/gpio/gpiovar.h> 48 49 #include <mips/ralink/ralink_reg.h> 50 #include <mips/ralink/ralink_var.h> 51 52 #if !defined(MT7628) 53 #define SLICKROCK 54 #endif 55 #include <mips/ralink/ralink_gpio.h> 56 57 #if 0 58 #define ENABLE_RALINK_DEBUG_ERROR 1 59 #define ENABLE_RALINK_DEBUG_MISC 1 60 #define ENABLE_RALINK_DEBUG_INFO 1 61 #define ENABLE_RALINK_DEBUG_FORCE 1 62 #define ENABLE_RALINK_DEBUG_FUNC 1 63 #endif 64 65 #include <mips/ralink/ralink_debug.h> 66 67 /* 68 * From the RT3052 datasheet, the GPIO pins are 69 * shared with a number of other functions. Not 70 * all will be available for GPIO. To make sure 71 * pins are in GPIO mode, the GPIOMODE purpose 72 * select register must be set (reset defaults all pins 73 * as GPIO except for JTAG) 74 * 75 * Note, GPIO0 is not shared, it is the single dedicated 76 * GPIO pin. 77 * 78 * 52 pins: 79 * 80 * 40 - 51 RGMII (GE0_* pins) 81 * 24 - 39 SDRAM (MD31:MD16 pins) 82 * 22 - 23 MDIO (MDC/MDIO pins) 83 * 17 - 21 JTAG (JTAG_* pins) 84 * 15 - 16 UART Light (RXD2/TXD2 pins) 85 * 7 - 14 UART Full (8 pins) 86 * (7 - 14) UARTF_7 (3'b111 in Share mode reg) 87 * (11 - 14) UARTF_5 (3'b110 in Share mode reg, same with 6) 88 * (7 - 9) UARTF_4 (3'b100 in Share mode reg) 89 * 3 - 6 SPI (SPI_* pins) 90 * 1 - 2 I2C (I2C_SCLK/I2C_SD pins) 91 */ 92 93 #ifdef MT7628 94 #define GPIO_PINS 96 95 #define SPECIAL_COMMANDS 0 96 #else 97 #if defined(SLICKROCK) 98 #define GPIO_PINS 96 99 #else 100 #define GPIO_PINS 52 101 #endif 102 103 /* 104 * Special commands are pseudo pin numbers used to pass data to bootloader, 105 */ 106 #define BOOT_COUNT GPIO_PINS 107 #define UPGRADE (BOOT_COUNT + 1) 108 #define SPECIAL_COMMANDS (UPGRADE + 1 - GPIO_PINS) 109 #endif 110 111 112 /* 113 * The pin_share array maps to the highest pin used for each of the 10 114 * GPIO mode bit settings. 115 */ 116 #if defined(MT7628) 117 const static struct { 118 int pin_start; 119 int pin_end; 120 uint32_t sysreg; 121 uint32_t regmask; 122 uint32_t mode; 123 } gpio_mux_map[] = { 124 { 0, 3, RA_SYSCTL_GPIO1MODE, GPIO1MODE_I2S, 1 }, 125 { 4, 5, RA_SYSCTL_GPIO1MODE, GPIO1MODE_I2C, 1 }, 126 { 6, 6, RA_SYSCTL_GPIO1MODE, GPIO1MODE_SPI_CS1, 1 }, 127 { 7, 10, RA_SYSCTL_GPIO1MODE, GPIO1MODE_SPI, 1 }, 128 { 11, 11, RA_SYSCTL_GPIO1MODE, GPIO1MODE_GPIO, 1 }, 129 { 12, 13, RA_SYSCTL_GPIO1MODE, GPIO1MODE_UART0, 1 }, 130 { 14, 17, RA_SYSCTL_GPIO1MODE, GPIO1MODE_SPIS, 1 }, 131 { 18, 18, RA_SYSCTL_GPIO1MODE, GPIO1MODE_PWM0, 1 }, 132 { 19, 19, RA_SYSCTL_GPIO1MODE, GPIO1MODE_PWM1, 1 }, 133 { 20, 21, RA_SYSCTL_GPIO1MODE, GPIO1MODE_UART2, 1 }, 134 { 22, 29, RA_SYSCTL_GPIO1MODE, GPIO1MODE_SD, 1 }, 135 { 30, 30, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P4_LED_KN, 1 }, 136 { 31, 31, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P3_LED_KN, 1 }, 137 { 32, 32, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P2_LED_KN, 1 }, 138 { 33, 33, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P1_LED_KN, 1 }, 139 { 34, 34, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P0_LED_KN, 1 }, 140 { 35, 35, RA_SYSCTL_GPIO2MODE, GPIO2MODE_WLED_KN, 1 }, 141 { 36, 36, RA_SYSCTL_GPIO1MODE, GPIO1MODE_PERST, 1 }, 142 { 37, 37, RA_SYSCTL_GPIO1MODE, GPIO1MODE_REFCLK, 1 }, 143 { 38, 38, RA_SYSCTL_GPIO1MODE, GPIO1MODE_WDT, 1 }, 144 { 39, 39, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P4_LED_AN, 1 }, 145 { 40, 40, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P3_LED_AN, 1 }, 146 { 41, 41, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P2_LED_AN, 1 }, 147 { 42, 42, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P1_LED_AN, 1 }, 148 { 43, 43, RA_SYSCTL_GPIO2MODE, GPIO2MODE_P0_LED_AN, 1 }, 149 { 44, 44, RA_SYSCTL_GPIO2MODE, GPIO2MODE_WLED_AN, 1 }, 150 { 45, 45, RA_SYSCTL_GPIO1MODE, GPIO1MODE_UART1, 1 }, 151 { 46, 46, RA_SYSCTL_GPIO1MODE, GPIO1MODE_UART1, 1 }, 152 }; 153 #else 154 #if defined(SLICKROCK) 155 #define SR_GPIO_MODE 0xc1c1f 156 #else 157 const static u_int8_t pin_share[] = { 158 2, 6, 9, 14, 14, 16, 21, 23, 39, 51 159 }; 160 #endif 161 #endif /* MT7628 */ 162 163 #define DEBOUNCE_TIME 150 /* Milliseconds */ 164 165 #if defined(TABLEROCK) || defined(SPOT2) || defined(PUCK) || defined(MOAB) 166 167 static const u_int32_t debounce_pin[DEBOUNCED_PINS] = { 168 WPS_BUTTON, 169 POWER_OFF_BUTTON, 170 DOCK_SENSE, 171 IN_5V, 172 LAN_WAN_SW 173 }; 174 static struct timeval debounce_time[DEBOUNCED_PINS]; 175 176 /* LED defines for display during boot */ 177 static const char led_array1[] = { 178 LED_BATT_7, 179 LED_BATT_8, 180 LED_BATT_9, 181 LED_BATT_10, 182 LED_SS_11, 183 LED_SS_12, 184 LED_SS_13, 185 LED_SS_14 186 }; 187 188 #define SET_SS_LED_REG RA_PIO_24_39_SET_BIT 189 #define CLEAR_SS_LED_REG RA_PIO_24_39_CLR_BIT 190 #define SS_OFFSET 24 191 #define BOOT_LED_TIMING 3000 192 193 #endif /* TABLEROCK || SPOT2 || PUCK || MOAB */ 194 195 #if defined(PEBBLES500) || defined (PEBBLES35) 196 197 static const u_int32_t debounce_pin[DEBOUNCED_PINS] = { 198 WPS_BUTTON, 199 SOFT_RST_IN_BUTTON, 200 CURRENT_LIMIT_FLAG1_3_3v, 201 CURRENT_LIMIT_FLAG_USB1, 202 CURRENT_LIMIT_FLAG1_1_5v, 203 EXCARD_ATTACH 204 }; 205 static struct timeval debounce_time[DEBOUNCED_PINS]; 206 207 /* LED defines for display during boot */ 208 #if defined(PEBBLES500) 209 static const char led_array1[] = { 210 LED_SS_13, 211 LED_SS_12, 212 LED_SS_11, 213 LED_SS_10 214 }; 215 #else 216 static const char led_array1[] = {}; 217 #endif 218 219 #define SET_SS_LED_REG RA_PIO_40_51_SET_BIT 220 #define CLEAR_SS_LED_REG RA_PIO_40_51_CLR_BIT 221 #define SS_OFFSET 40 222 #define BOOT_LED_TIMING 5500 223 224 #endif /* PEBBLES500 || PEBBLES35 */ 225 226 227 #if defined(SLICKROCK) 228 229 static const u_int32_t debounce_pin[DEBOUNCED_PINS] = { 230 WPS_BUTTON, 231 SOFT_RST_IN_BUTTON, 232 SS_BUTTON, 233 CURRENT_LIMIT_FLAG_USB1, 234 CURRENT_LIMIT_FLAG_USB2, 235 CURRENT_LIMIT_FLAG_USB3, 236 CURRENT_LIMIT_FLAG_EX1, 237 CURRENT_LIMIT_FLAG_EX2, 238 WIFI_ENABLE 239 }; 240 static struct timeval debounce_time[DEBOUNCED_PINS]; 241 242 /* LED defines for display during boot */ 243 static const char led_array1[] = { 244 LED_SS_13, 245 LED_SS_12, 246 LED_SS_11, 247 LED_SS_10 248 }; 249 250 #define SET_SS_LED_REG RA_PIO_40_51_SET_BIT 251 #define CLEAR_SS_LED_REG RA_PIO_40_51_CLR_BIT 252 #define SS_OFFSET 40 253 #define BOOT_LED_TIMING 3250 254 255 #endif /* SLICKROCK */ 256 257 #ifndef DEBOUNCED_PINS 258 static const u_int32_t debounce_pin[] = {}; 259 static struct timeval debounce_time[] = {}; 260 #endif 261 #ifndef BOOT_LED_TIMING 262 static const char led_array1[] = {}; 263 #endif 264 265 #define RA_GPIO_PIN_INIT(sc, var, pin, ptp, regname) \ 266 do { \ 267 const u_int _reg_bit = 1 << (pin - ptp->pin_reg_base); \ 268 const u_int _mask_bit = 1 << (pin - ptp->pin_mask_base);\ 269 var = gp_read(sc, ptp->regname.reg); \ 270 if ((ptp->regname.mask & _mask_bit) != 0) { \ 271 var |= _reg_bit; \ 272 } else { \ 273 var &= ~_reg_bit; \ 274 } \ 275 gp_write(sc, ptp->regname.reg, var); \ 276 } while (0) 277 278 #define RA_GPIO_PIN_INIT_DIR(sc, var, pin, ptp) \ 279 do { \ 280 const u_int _reg_bit = 1 << (pin - ptp->pin_reg_base); \ 281 const u_int _mask_bit = 1 << (pin - ptp->pin_mask_base);\ 282 var = gp_read(sc, ptp->pin_dir.reg); \ 283 if ((ptp->pin_dir.mask & _mask_bit) != 0) { \ 284 var |= _reg_bit; \ 285 sc->sc_pins[pin].pin_flags = GPIO_PIN_OUTPUT; \ 286 } else { \ 287 var &= ~_reg_bit; \ 288 sc->sc_pins[pin].pin_flags = GPIO_PIN_INPUT; \ 289 } \ 290 gp_write(sc, ptp->pin_dir.reg, var); \ 291 } while (0) 292 293 294 295 typedef struct ra_gpio_softc { 296 device_t sc_dev; 297 struct gpio_chipset_tag sc_gc; 298 gpio_pin_t sc_pins[GPIO_PINS + SPECIAL_COMMANDS]; 299 300 bus_space_tag_t sc_memt; /* bus space tag */ 301 302 bus_space_handle_t sc_sy_memh; /* Sysctl bus space handle */ 303 int sc_sy_size; /* size of Sysctl register space */ 304 305 bus_space_handle_t sc_gp_memh; /* PIO bus space handle */ 306 int sc_gp_size; /* size of PIO register space */ 307 308 void *sc_ih; /* interrupt handle */ 309 void *sc_si; /* softintr handle */ 310 311 struct callout sc_tick_callout; /* For debouncing inputs */ 312 313 /* 314 * These track gpio pins that have interrupted 315 */ 316 #if defined(MT7628) 317 uint32_t sc_intr_status00_31; 318 uint32_t sc_intr_status32_63; 319 uint32_t sc_intr_status64_95; 320 #else 321 uint32_t sc_intr_status00_23; 322 uint32_t sc_intr_status24_39; 323 uint32_t sc_intr_status40_51; 324 uint32_t sc_intr_status72_95; 325 #endif 326 327 } ra_gpio_softc_t; 328 329 static int ra_gpio_match(device_t, cfdata_t , void *); 330 static void ra_gpio_attach(device_t, device_t, void *); 331 #ifdef NOTYET 332 static int ra_gpio_open(void *, device_t); 333 static int ra_gpio_close(void *, device_t); 334 #endif 335 static void ra_gpio_pin_init(ra_gpio_softc_t *, int); 336 static void ra_gpio_pin_ctl(void *, int, int); 337 338 static int ra_gpio_intr(void *); 339 static void ra_gpio_softintr(void *); 340 static void ra_gpio_debounce_process(void *); 341 static void ra_gpio_debounce_setup(ra_gpio_softc_t *); 342 343 static void disable_gpio_interrupt(ra_gpio_softc_t *, int); 344 static void enable_gpio_interrupt(ra_gpio_softc_t *, int); 345 346 static void gpio_reset_registers(ra_gpio_softc_t *); 347 #if 0 348 static void gpio_register_dump(ra_gpio_softc_t *); 349 #endif 350 351 typedef struct pin_reg { 352 u_int mask; 353 u_int reg; 354 } pin_reg_t; 355 356 typedef struct pin_tab { 357 int pin_reg_base; 358 int pin_reg_limit; 359 int pin_mask_base; 360 u_int pin_enabled; 361 u_int pin_input; 362 u_int pin_output_clr; 363 u_int pin_output_set; 364 pin_reg_t pin_dir; 365 pin_reg_t pin_rise; 366 pin_reg_t pin_fall; 367 pin_reg_t pin_pol; 368 } pin_tab_t; 369 370 /* 371 * use pin_tab[] in conjunction with pin_tab_index[] 372 * to look up register offsets, masks, etc. for a given GPIO pin, 373 * instead of lots of if/then/else test & branching 374 */ 375 static const pin_tab_t pin_tab[] = { 376 #if defined(MT7628) 377 { 378 0, 31, 0, 0xffffffff, 379 RA_PIO_00_31_DATA, 380 RA_PIO_00_31_CLR_BIT, 381 RA_PIO_00_31_SET_BIT, 382 { 0xffffffff, RA_PIO_00_31_DIR }, 383 { 0xffffffff, RA_PIO_00_31_INT_RISE_EN }, 384 { 0xffffffff, RA_PIO_00_31_INT_FALL_EN }, 385 { 0xffffffff, RA_PIO_00_31_POLARITY } 386 }, 387 { 388 32, 63, 32, 0xffffffff, 389 RA_PIO_32_63_DATA, 390 RA_PIO_32_63_CLR_BIT, 391 RA_PIO_32_63_SET_BIT, 392 { 0xffffffff, RA_PIO_32_63_DIR }, 393 { 0xffffffff, RA_PIO_32_63_INT_RISE_EN }, 394 { 0xffffffff, RA_PIO_32_63_INT_FALL_EN }, 395 { 0xffffffff, RA_PIO_32_63_POLARITY } 396 }, 397 { 398 64, 95, 64, 0xffffffff, 399 RA_PIO_64_95_DATA, 400 RA_PIO_64_95_CLR_BIT, 401 RA_PIO_64_95_SET_BIT, 402 { 0xffffffff, RA_PIO_64_95_DIR }, 403 { 0xffffffff, RA_PIO_64_95_INT_RISE_EN }, 404 { 0xffffffff, RA_PIO_64_95_INT_FALL_EN }, 405 { 0xffffffff, RA_PIO_64_95_POLARITY } 406 } 407 #else 408 { 409 0, 24, 0, GPIO_PIN_MASK, 410 RA_PIO_00_23_DATA, 411 RA_PIO_00_23_CLR_BIT, 412 RA_PIO_00_23_SET_BIT, 413 { GPIO_OUTPUT_PIN_MASK, RA_PIO_00_23_DIR, }, 414 { GPIO_INT_PIN_MASK, RA_PIO_00_23_INT_RISE_EN, }, 415 { GPIO_INT_FEDGE_PIN_MASK, RA_PIO_00_23_INT_RISE_EN, }, 416 { GPIO_POL_MASK, RA_PIO_00_23_POLARITY, }, 417 }, 418 { 419 24, 40, 24, GPIO_PIN_MASK_24_51, 420 RA_PIO_24_39_DATA, 421 RA_PIO_24_39_CLR_BIT, 422 RA_PIO_24_39_SET_BIT, 423 { GPIO_OUTPUT_PIN_MASK_24_51, RA_PIO_24_39_DIR, }, 424 { GPIO_INT_PIN_MASK_24_51, RA_PIO_24_39_INT_RISE_EN, }, 425 { GPIO_INT_FEDGE_PIN_MASK_24_51, RA_PIO_24_39_INT_FALL_EN, }, 426 { GPIO_POL_MASK_24_51, RA_PIO_24_39_POLARITY, }, 427 }, 428 { 429 40, 52, 24, GPIO_PIN_MASK_24_51, 430 RA_PIO_40_51_DATA, 431 RA_PIO_40_51_CLR_BIT, 432 RA_PIO_40_51_SET_BIT, 433 { GPIO_OUTPUT_PIN_MASK_24_51, RA_PIO_40_51_DIR, }, 434 { GPIO_INT_PIN_MASK_24_51, RA_PIO_40_51_INT_RISE_EN, }, 435 { GPIO_INT_FEDGE_PIN_MASK_24_51, RA_PIO_40_51_INT_FALL_EN, }, 436 { GPIO_POL_MASK_24_51, RA_PIO_40_51_POLARITY, }, 437 }, 438 #if defined(SLICKROCK) 439 { 440 72, 96, 72, GPIO_PIN_MASK_72_95, 441 RA_PIO_72_95_DATA, 442 RA_PIO_72_95_CLR_BIT, 443 RA_PIO_72_95_SET_BIT, 444 { GPIO_OUTPUT_PIN_MASK_72_95, RA_PIO_72_95_DIR, }, 445 { GPIO_INT_PIN_MASK_72_95, RA_PIO_72_95_INT_RISE_EN, }, 446 { GPIO_INT_FEDGE_PIN_MASK_72_95, RA_PIO_72_95_INT_FALL_EN, }, 447 { GPIO_POL_MASK_72_95, RA_PIO_72_95_POLARITY, }, 448 }, 449 #endif 450 #endif 451 }; 452 453 /* 454 * use pin_tab_index[] to determine index in pin_tab[] 455 * for a given pin. -1 means there is no pin there. 456 */ 457 static const int pin_tab_index[GPIO_PINS] = { 458 #if defined(MT7628) 459 /* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 */ 460 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 461 /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 462 /* 32 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 463 /* 48 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 464 /* 64 */ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 465 /* 80 */ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 466 #else /* !MT7628 */ 467 /* 0 1 2 3 4 5 6 7 8 9 */ 468 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 469 /* 10 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 470 /* 20 */ 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 471 /* 30 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 472 /* 40 */ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 473 /* 50 */ 2, 2, 474 #if defined(SLICKROCK) 475 /* 50 */ -1, -1, -1, -1, -1, -1, -1, -1, 476 /* 60 */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 477 /* 70 */ -1, -1, 478 /* 72 */ 3, 3, 3, 3, 3, 3, 3, 3, 479 /* 80 */ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 480 /* 90 */ 3, 3, 3, 3, 3, 3 481 #endif 482 #endif /* !MT7628 */ 483 }; 484 485 CFATTACH_DECL_NEW(rgpio, sizeof(struct ra_gpio_softc), ra_gpio_match, 486 ra_gpio_attach, NULL, NULL); 487 488 /* 489 * Event handler calls and structures 490 */ 491 static int gpio_event_app_user_attach(struct knote *); 492 static void gpio_event_app_user_detach(struct knote *); 493 static int gpio_event_app_user_event(struct knote *, long); 494 495 static struct klist knotes; 496 static int app_filter_id; 497 static struct filterops app_fops = { 498 .f_flags = 0, 499 .f_attach = gpio_event_app_user_attach, 500 .f_detach = gpio_event_app_user_detach, 501 .f_event = gpio_event_app_user_event, 502 }; 503 static struct callout led_tick_callout; 504 static int gpio_driver_blink_leds = 1; 505 506 static inline uint32_t 507 sy_read(ra_gpio_softc_t *sc, bus_size_t off) 508 { 509 KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n", 510 __func__, off); 511 return bus_space_read_4(sc->sc_memt, sc->sc_sy_memh, off); 512 } 513 514 static inline void 515 sy_write(ra_gpio_softc_t *sc, bus_size_t off, uint32_t val) 516 { 517 KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n", 518 __func__, off); 519 bus_space_write_4(sc->sc_memt, sc->sc_sy_memh, off, val); 520 } 521 522 static inline uint32_t 523 gp_read(ra_gpio_softc_t *sc, bus_size_t off) 524 { 525 KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n", 526 __func__, off); 527 return bus_space_read_4(sc->sc_memt, sc->sc_gp_memh, off); 528 } 529 530 static inline void 531 gp_write(ra_gpio_softc_t *sc, bus_size_t off, uint32_t val) 532 { 533 KASSERTMSG((off & 3) == 0, "%s: unaligned off=%#" PRIxBUSSIZE "\n", 534 __func__, off); 535 bus_space_write_4(sc->sc_memt, sc->sc_gp_memh, off, val); 536 } 537 538 /* 539 * Basic debug function, dump all PIO registers 540 */ 541 #if 0 542 static void 543 gpio_register_dump(ra_gpio_softc_t *sc) 544 { 545 for (int i=0; i < 0xb0; i+=4) 546 RALINK_DEBUG(RALINK_DEBUG_INFO, "Reg: 0x%x, Value: 0x%x\n", 547 (RA_PIO_BASE + i), gp_read(sc, i)); 548 } 549 #endif 550 551 static void 552 gpio_reset_registers(ra_gpio_softc_t *sc) 553 { 554 #if 0 555 for (int i=0; i < 0x88; i+=4) 556 gp_write(sc, i, 0); 557 #endif 558 } 559 560 561 static int 562 ra_gpio_match(device_t parent, cfdata_t cf, void *aux) 563 { 564 RALINK_DEBUG_FUNC_ENTRY(); 565 566 return 1; 567 } 568 569 static void 570 ra_gpio_attach(device_t parent, device_t self, void *aux) 571 { 572 573 struct gpiobus_attach_args gba; 574 ra_gpio_softc_t * const sc = device_private(self); 575 const struct mainbus_attach_args *ma = aux; 576 int error; 577 578 aprint_naive(": Ralink GPIO controller\n"); 579 aprint_normal(": Ralink GPIO controller\n"); 580 581 sc->sc_dev = self; 582 sc->sc_memt = ma->ma_memt; 583 sc->sc_sy_size = 0x10000; 584 sc->sc_gp_size = 0x1000; 585 586 /* 587 * map the registers 588 * 589 * we map the Sysctl, and PIO registers separately so we can use the 590 * defined register offsets sanely; just use the correct corresponding 591 * bus_space_handle 592 */ 593 594 if ((error = bus_space_map(sc->sc_memt, RA_SYSCTL_BASE, 595 sc->sc_sy_size, 0, &sc->sc_sy_memh)) != 0) { 596 aprint_error_dev(sc->sc_dev, 597 "unable to map Sysctl registers, error=%d\n", error); 598 goto fail_0; 599 } 600 601 if ((error = bus_space_map(sc->sc_memt, RA_PIO_BASE, 602 sc->sc_gp_size, 0, &sc->sc_gp_memh)) != 0) { 603 aprint_error_dev(sc->sc_dev, 604 "unable to map PIO registers, error=%d\n", error); 605 goto fail_1; 606 } 607 608 /* Reset some registers */ 609 #if defined(MT7628) 610 gp_write(sc, RA_PIO_00_31_INT_RISE_EN, 0xffffffff); 611 gp_write(sc, RA_PIO_00_31_INT_FALL_EN, 0xffffffff); 612 gp_write(sc, RA_PIO_00_31_INT_HIGH_EN, 0); 613 gp_write(sc, RA_PIO_00_31_INT_LOW_EN, 0); 614 615 gp_write(sc, RA_PIO_32_63_INT_RISE_EN, 0xffffffff); 616 gp_write(sc, RA_PIO_32_63_INT_FALL_EN, 0xffffffff); 617 gp_write(sc, RA_PIO_32_63_INT_HIGH_EN, 0); 618 gp_write(sc, RA_PIO_32_63_INT_LOW_EN, 0); 619 620 gp_write(sc, RA_PIO_64_95_INT_RISE_EN, 0xffffffff); 621 gp_write(sc, RA_PIO_64_95_INT_FALL_EN, 0xffffffff); 622 gp_write(sc, RA_PIO_64_95_INT_HIGH_EN, 0); 623 gp_write(sc, RA_PIO_64_95_INT_LOW_EN, 0); 624 625 gp_write(sc, RA_PIO_00_31_POLARITY, 0); 626 gp_write(sc, RA_PIO_32_63_POLARITY, 0); 627 gp_write(sc, RA_PIO_64_95_POLARITY, 0); 628 629 #else 630 gp_write(sc, RA_PIO_00_23_INT, 0xffffff); 631 gp_write(sc, RA_PIO_00_23_EDGE_INT, 0xffffff); 632 gp_write(sc, RA_PIO_24_39_INT, 0xffff); 633 gp_write(sc, RA_PIO_24_39_EDGE_INT, 0xffff); 634 gp_write(sc, RA_PIO_40_51_INT, 0xfff); 635 gp_write(sc, RA_PIO_40_51_EDGE_INT, 0xfff); 636 gp_write(sc, RA_PIO_00_23_POLARITY, 0); 637 #if defined(SLICKROCK) 638 gp_write(sc, RA_PIO_72_95_INT, 0xffffff); 639 gp_write(sc, RA_PIO_72_95_EDGE_INT, 0xffffff); 640 #endif 641 #endif 642 643 /* Set up for interrupt handling, low priority interrupt queue */ 644 sc->sc_ih = ra_intr_establish(RA_IRQ_PIO, 645 ra_gpio_intr, sc, 0); 646 if (sc->sc_ih == NULL) { 647 RALINK_DEBUG(RALINK_DEBUG_ERROR, 648 "%s: unable to establish interrupt\n", 649 device_xname(sc->sc_dev)); 650 goto fail_2; 651 } 652 653 /* Soft int setup */ 654 sc->sc_si = softint_establish(SOFTINT_BIO, ra_gpio_softintr, sc); 655 if (sc->sc_si == NULL) { 656 ra_intr_disestablish(sc->sc_ih); 657 RALINK_DEBUG(RALINK_DEBUG_ERROR, 658 "%s: unable to establish soft interrupt\n", 659 device_xname(sc->sc_dev)); 660 goto fail_3; 661 } 662 663 klist_init(&knotes); 664 if (kfilter_register("CP_GPIO_EVENT", &app_fops, &app_filter_id) != 0) { 665 RALINK_DEBUG(RALINK_DEBUG_ERROR, 666 "%s: kfilter_register for CP_GPIO_EVENT failed\n", 667 __func__); 668 goto fail_4; 669 } 670 671 sc->sc_gc.gp_cookie = sc; 672 sc->sc_gc.gp_pin_read = ra_gpio_pin_read; 673 sc->sc_gc.gp_pin_write = ra_gpio_pin_write; 674 sc->sc_gc.gp_pin_ctl = ra_gpio_pin_ctl; 675 676 #if 0 677 gpio_register_dump(sc); 678 #endif 679 gpio_reset_registers(sc); 680 681 /* Initialize the GPIO pins */ 682 for (int pin = 0; pin < GPIO_PINS; pin++) 683 ra_gpio_pin_init(sc, pin); 684 685 #if 0 686 /* debug check */ 687 KASSERT((sy_read(sc, RA_SYSCTL_GPIOMODE) == 0x31c) != 0); 688 RALINK_DEBUG(RALINK_DEBUG_INFO, "SYSCTL_GPIOMODE = 0x%x\n", 689 sy_read(sc, RA_SYSCTL_GPIOMODE)); 690 #endif 691 692 /* 693 * Some simple board setup actions: 694 * Check if we're attached to the dock. If so, enable dock power. 695 * BIG NOTE: Dock power is dependent on USB5V_EN! 696 */ 697 #if defined(PEBBLES500) || defined (PEBBLES35) 698 RALINK_DEBUG(RALINK_DEBUG_INFO, "Enabling USB power\n"); 699 ra_gpio_pin_write(sc, VBUS_EN, 1); 700 ra_gpio_pin_write(sc, POWER_EN_USB, 1); 701 #if defined(PEBBLES500) 702 /* 703 * Is an express card attached? Enable power if it is 704 * or it isn't 705 */ 706 #if 0 707 if (ra_gpio_pin_read(sc, EXCARD_ATTACH) == 0) { 708 #endif 709 ra_gpio_pin_write(sc, POWER_EN_EXCARD1_3_3v, 1); 710 ra_gpio_pin_write(sc, POWER_EN_EXCARD1_1_5v, 1); 711 #if 0 712 } 713 #endif /* 0 */ 714 #endif /* PEBBLES500 */ 715 #endif /* PEBBLES500 || PEBBLES35 */ 716 717 #if defined(TABLEROCK) || defined(SPOT2) || defined(PUCK) || defined(MOAB) 718 /* CHARGER_OFF pin matches the IN_5V */ 719 if (ra_gpio_pin_read(sc, IN_5V) == 0) { 720 ra_gpio_pin_write(sc, CHARGER_OFF, 0); 721 } else { 722 ra_gpio_pin_write(sc, CHARGER_OFF, 1); 723 } 724 #endif 725 726 #if defined(SLICKROCK) 727 /* Enable all modem slots */ 728 ra_gpio_pin_write(sc, POWER_EN_USB1, 1); 729 ra_gpio_pin_write(sc, POWER_EN_USB2, 1); 730 ra_gpio_pin_write(sc, POWER_EN_USB3, 1); 731 ra_gpio_pin_write(sc, POWER_EN_EX1, 1); 732 ra_gpio_pin_write(sc, EX1_CPUSB_RST, 0); 733 ra_gpio_pin_write(sc, POWER_EN_EX2, 1); 734 ra_gpio_pin_write(sc, EX2_CPUSB_RST, 0); 735 736 /* Wake up with an overcurrent on EX1. Try to shut it down. */ 737 gp_write(sc, RA_PIO_72_95_INT, 0xffffff); 738 gp_write(sc, RA_PIO_72_95_EDGE_INT, 0xffffff); 739 #endif 740 741 #ifdef BOOT_COUNT 742 sc->sc_pins[BOOT_COUNT].pin_flags = GPIO_PIN_OUTPUT; 743 sc->sc_pins[BOOT_COUNT].pin_mapped = 0; 744 #endif 745 #ifdef UPGRADE 746 sc->sc_pins[UPGRADE].pin_flags = GPIO_PIN_OUTPUT; 747 sc->sc_pins[UPGRADE].pin_mapped = 0; 748 #endif 749 gba.gba_gc = &sc->sc_gc; 750 gba.gba_pins = sc->sc_pins; 751 752 /* Note, > 52nd pin isn't a gpio, it is a special command */ 753 gba.gba_npins = (GPIO_PINS + SPECIAL_COMMANDS); 754 755 config_found(sc->sc_dev, &gba, gpiobus_print, CFARGS_NONE); 756 757 #if 0 758 gpio_register_dump(sc); 759 #endif 760 761 /* init our gpio debounce */ 762 callout_init(&sc->sc_tick_callout, 0); 763 callout_setfunc(&sc->sc_tick_callout, ra_gpio_debounce_process, sc); 764 765 /* LED blinking during boot */ 766 callout_init(&led_tick_callout, 0); 767 768 ra_gpio_toggle_LED(sc); 769 return; 770 771 fail_4: 772 softint_disestablish(sc->sc_si); 773 fail_3: 774 ra_intr_disestablish(sc->sc_ih); 775 fail_2: 776 bus_space_unmap(sc->sc_memt, sc->sc_gp_memh, sc->sc_sy_size); 777 fail_1: 778 bus_space_unmap(sc->sc_memt, sc->sc_sy_memh, sc->sc_sy_size); 779 fail_0: 780 return; 781 } 782 783 /* 784 * ra_gpio_pin_init - initialize the given gpio pin 785 */ 786 static void 787 ra_gpio_pin_init(ra_gpio_softc_t *sc, int pin) 788 { 789 uint32_t r; 790 791 sc->sc_pins[pin].pin_caps = 0; 792 sc->sc_pins[pin].pin_flags = 0; 793 sc->sc_pins[pin].pin_state = 0; 794 sc->sc_pins[pin].pin_mapped = 0; 795 796 /* ensure pin number is in range */ 797 KASSERT(pin < GPIO_PINS); 798 if (pin >= GPIO_PINS) 799 return; 800 801 /* if pin number is in a gap in the range, just return */ 802 const int index = pin_tab_index[pin]; 803 if (index == -1) 804 return; 805 806 /* if pin is not enabled, just return */ 807 const pin_tab_t * const ptp = &pin_tab[index]; 808 const u_int mask_bit = 1 << (pin - ptp->pin_mask_base); 809 if ((ptp->pin_enabled & mask_bit) == 0) 810 return; 811 812 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 813 GPIO_PIN_INVIN | GPIO_PIN_INVOUT; 814 sc->sc_pins[pin].pin_state = GPIO_PIN_INPUT; 815 816 #if defined(MT7628) 817 /* 818 * Set the SYSCTL_GPIO{1,2}MODE register 819 * for the PIO block of any mapped GPIO 820 */ 821 for (int i = 0; i < __arraycount(gpio_mux_map); i++) { 822 if ((pin >= gpio_mux_map[i].pin_start) && 823 (pin >= gpio_mux_map[i].pin_end)) { 824 r = sy_read(sc, gpio_mux_map[i].sysreg); 825 r &= ~gpio_mux_map[i].regmask; 826 r |= __SHIFTIN(gpio_mux_map[i].mode, 827 gpio_mux_map[i].regmask); 828 sy_write(sc, gpio_mux_map[i].sysreg, r); 829 break; 830 } 831 } 832 #else 833 #if defined(SLICKROCK) 834 r = sy_read(sc, RA_SYSCTL_GPIOMODE); 835 r |= SR_GPIO_MODE; 836 sy_write(sc, RA_SYSCTL_GPIOMODE, r); 837 #else 838 /* 839 * Set the SYSCTL_GPIOMODE register to 1 for 840 * the PIO block of any mapped GPIO 841 * (most have reset defaults of 1 already). 842 * GPIO0 doesn't have an associated MODE register. 843 */ 844 if (pin != 0) { 845 u_int gpio_mode; 846 847 for (gpio_mode = 0; gpio_mode < __arraycount(pin_share); 848 gpio_mode++) { 849 if (pin <= pin_share[gpio_mode]) { 850 r = sy_read(sc, RA_SYSCTL_GPIOMODE); 851 if (10 == pin) { 852 /* 853 * Special case: 854 * GPIO 10 requires GPIOMODE_UARTF0-2 855 */ 856 r |= GPIOMODE_UARTF_0_2; 857 } else { 858 /* standard case */ 859 r |= (1 << gpio_mode); 860 } 861 sy_write(sc, RA_SYSCTL_GPIOMODE, r); 862 break; 863 } 864 } 865 } 866 #endif /* SLICKROCK */ 867 #endif /* !MT7628 */ 868 869 /* set direction */ 870 RA_GPIO_PIN_INIT_DIR(sc, r, pin, ptp); 871 872 /* rising edge interrupt */ 873 RA_GPIO_PIN_INIT(sc, r, pin, ptp, pin_rise); 874 875 /* falling edge interrupt */ 876 RA_GPIO_PIN_INIT(sc, r, pin, ptp, pin_fall); 877 878 /* polarirty */ 879 RA_GPIO_PIN_INIT(sc, r, pin, ptp, pin_pol); 880 } 881 882 /* 883 * Note: This has special hacks in it. If pseudo-pin BOOT_COUNT 884 * is requested, it is a signal check the memo register for a special key 885 * that means run Wi-Fi in no security mode. 886 */ 887 int 888 ra_gpio_pin_read(void *arg, int pin) 889 { 890 RALINK_DEBUG_FUNC_ENTRY(); 891 const ra_gpio_softc_t * const sc = arg; 892 int rv; 893 894 KASSERT(sc != NULL); 895 896 if (pin < GPIO_PINS) { 897 /* 898 * normal case: a regular GPIO pin 899 * if pin number is in a gap in the range, 900 * then warn and return 0 901 */ 902 const int index = pin_tab_index[pin]; 903 KASSERTMSG(index != -1, "%s: non-existent pin=%d\n", 904 __func__, pin); 905 if (index == -1) { 906 rv = 0; 907 } else { 908 const pin_tab_t * const ptp = &pin_tab[index]; 909 const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base); 910 const bus_size_t off = ptp->pin_input; 911 uint32_t r; 912 913 r = bus_space_read_4(sc->sc_memt, sc->sc_gp_memh, off); 914 rv = ((r & (1 << reg_bit)) != 0); 915 } 916 } else { 917 /* 918 * Special hack: a pseudo-pin used for signaling 919 */ 920 rv = 0; 921 switch (pin) { 922 #ifdef BOOT_COUNT 923 case BOOT_COUNT: 924 if (1 == ra_check_memo_reg(NO_SECURITY)) 925 rv = 1; 926 break; 927 #endif 928 default: 929 #ifdef DIAGNOSTIC 930 aprint_normal_dev(sc->sc_dev, "%s: bad pin=%d\n", 931 __func__, pin); 932 #endif 933 break; 934 } 935 } 936 937 RALINK_DEBUG_0(RALINK_DEBUG_INFO, "pin %d, value %x\n", pin, rv); 938 return rv; 939 } 940 941 /* 942 * There are three ways to change the value of a pin. 943 * You can write to the DATA register, which will set 944 * or reset a pin. But you need to store it locally and 945 * read/mask/set it, which is potentially racy without locks. 946 * There are also SET and RESET registers, which allow you to write 947 * a value to a single pin and not affect any other pins 948 * by accident. 949 * 950 * NOTE: This has special hacks in it. If pin 52 (which does not exist) 951 * is written, it is a signal to clear the boot count register. If pin 952 * 53 is written, it is a upgrade signal to the bootloader. 953 * 954 */ 955 #define MAGIC 0x27051956 956 #define UPGRADE_MAGIC 0x27051957 957 void 958 ra_gpio_pin_write(void *arg, int pin, int value) 959 { 960 RALINK_DEBUG_FUNC_ENTRY(); 961 ra_gpio_softc_t * const sc = arg; 962 #if defined(BOOT_COUNT) || defined(UPGRADE) 963 uint32_t r; 964 #endif 965 966 KASSERT(sc != NULL); 967 RALINK_DEBUG(RALINK_DEBUG_INFO, "pin %d, val %d\n", pin, value); 968 969 if (pin >= GPIO_PINS) { 970 /* 971 * Special hack: a pseudo-pin used for signaling 972 */ 973 switch(pin) { 974 #ifdef BOOT_COUNT 975 case BOOT_COUNT: 976 /* Reset boot count */ 977 r = sy_read(sc, RA_SYSCTL_MEMO0); 978 if (r == MAGIC) 979 sy_write(sc, RA_SYSCTL_MEMO1, 0); 980 break; 981 #endif 982 #ifdef UPGRADE 983 case UPGRADE: 984 /* Set upgrade flag */ 985 sy_write(sc, RA_SYSCTL_MEMO0, UPGRADE_MAGIC); 986 sy_write(sc, RA_SYSCTL_MEMO1, UPGRADE_MAGIC); 987 break; 988 #endif 989 default: 990 #ifdef DIAGNOSTIC 991 aprint_normal_dev(sc->sc_dev, "%s: bad pin=%d\n", 992 __func__, pin); 993 #endif 994 } 995 return; 996 } 997 998 /* 999 * normal case: a regular GPIO pin 1000 * if pin number is in a gap in the range, 1001 * then warn and return 1002 */ 1003 const int index = pin_tab_index[pin]; 1004 KASSERTMSG(index != -1, "%s: non-existent pin=%d\n", __func__, pin); 1005 if (index == -1) 1006 return; 1007 1008 const pin_tab_t * const ptp = &pin_tab[index]; 1009 const u_int mask_bit = 1 << (pin - ptp->pin_mask_base); 1010 const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base); 1011 const bus_size_t off = (value == 0) ? 1012 ptp->pin_output_clr : ptp->pin_output_set; 1013 1014 if ((ptp->pin_dir.mask & mask_bit) == 0) { 1015 #ifdef DIAGNOSTIC 1016 aprint_normal_dev(sc->sc_dev, 1017 "%s: Writing non-output pin: %d\n", __func__, pin); 1018 #endif 1019 return; 1020 } 1021 1022 bus_space_write_4(sc->sc_memt, sc->sc_gp_memh, off, reg_bit); 1023 } 1024 1025 static void 1026 ra_gpio_pin_ctl(void *arg, int pin, int flags) 1027 { 1028 RALINK_DEBUG_FUNC_ENTRY(); 1029 1030 /* 1031 * For now, this lets us know that user-space is using the GPIOs 1032 * and the kernel shouldn't blink LEDs any more 1033 */ 1034 gpio_driver_blink_leds = 0; 1035 } 1036 1037 /* 1038 * Check the three interrupt registers and ack them 1039 * immediately. If a button is pushed, use the 1040 * handle_key_press call to debounce it. Otherwise, 1041 * call the softint handler to send any necessary 1042 * events. 1043 */ 1044 static int 1045 ra_gpio_intr(void *arg) 1046 { 1047 RALINK_DEBUG_FUNC_ENTRY(); 1048 ra_gpio_softc_t * const sc = arg; 1049 1050 #if 0 1051 /* Read the 3 interrupt registers */ 1052 #if defined(MT7628) 1053 if (sc->sc_intr_status00_31 || sc->sc_intr_status32_63 || 1054 sc->sc_intr_status64_95) { 1055 printf("\n0-31 %x, 32-63 %x, 64_95 %x\n", 1056 sc->sc_intr_status00_31, 1057 sc->sc_intr_status32_63, 1058 sc->sc_intr_status64_95); 1059 } 1060 #else 1061 if (sc->sc_intr_status00_23 || sc->sc_intr_status24_39 || 1062 sc->sc_intr_status40_51) { 1063 printf("\n0-23 %x, 24-39 %x, 40_51 %x\n", 1064 sc->sc_intr_status00_23, 1065 sc->sc_intr_status24_39, 1066 sc->sc_intr_status40_51); 1067 } 1068 #endif 1069 #endif 1070 1071 #if defined(MT7628) 1072 sc->sc_intr_status00_31 |= gp_read(sc, RA_PIO_00_31_INT_STAT); 1073 sc->sc_intr_status32_63 |= gp_read(sc, RA_PIO_32_63_INT_STAT); 1074 sc->sc_intr_status64_95 |= gp_read(sc, RA_PIO_64_95_INT_STAT); 1075 #else 1076 sc->sc_intr_status00_23 |= gp_read(sc, RA_PIO_00_23_INT); 1077 sc->sc_intr_status24_39 |= gp_read(sc, RA_PIO_24_39_INT); 1078 sc->sc_intr_status40_51 |= gp_read(sc, RA_PIO_40_51_INT); 1079 #if defined(SLICKROCK) 1080 sc->sc_intr_status72_95 |= gp_read(sc, RA_PIO_72_95_INT); 1081 #endif 1082 #endif 1083 1084 #if 0 1085 /* Trivial error checking, some interrupt had to have fired */ 1086 #if defined(MT7628) 1087 KASSERT((sc->sc_intr_status00_31 | sc->sc_intr_status32_64 | 1088 sc->sc_intr_status64_95) != 0); 1089 #else 1090 KASSERT((sc->sc_intr_status00_23 | sc->sc_intr_status24_39 | 1091 sc->sc_intr_status40_51) != 0); 1092 #endif 1093 #endif 1094 1095 /* Debounce interrupt */ 1096 ra_gpio_debounce_setup(sc); 1097 1098 /* 1099 * and ACK the interrupt. 1100 * OR the values in case the softint handler hasn't 1101 * been scheduled and handled any previous int 1102 * I don't know if resetting the EDGE register is 1103 * necessary, but the Ralink Linux driver does it. 1104 */ 1105 #if defined(MT7628) 1106 gp_write(sc, RA_PIO_00_31_INT_STAT, sc->sc_intr_status00_31); 1107 gp_write(sc, RA_PIO_00_31_INT_STAT_EDGE, sc->sc_intr_status00_31); 1108 gp_write(sc, RA_PIO_32_63_INT_STAT, sc->sc_intr_status32_63); 1109 gp_write(sc, RA_PIO_32_63_INT_STAT_EDGE, sc->sc_intr_status32_63); 1110 gp_write(sc, RA_PIO_64_95_INT_STAT, sc->sc_intr_status64_95); 1111 gp_write(sc, RA_PIO_64_95_INT_STAT_EDGE, sc->sc_intr_status64_95); 1112 1113 /* Reset until next time */ 1114 sc->sc_intr_status00_31 = 0; 1115 sc->sc_intr_status32_63 = 0; 1116 sc->sc_intr_status64_95 = 0; 1117 #else 1118 gp_write(sc, RA_PIO_00_23_INT, sc->sc_intr_status00_23); 1119 gp_write(sc, RA_PIO_00_23_EDGE_INT, sc->sc_intr_status00_23); 1120 gp_write(sc, RA_PIO_24_39_INT, sc->sc_intr_status24_39); 1121 gp_write(sc, RA_PIO_24_39_EDGE_INT, sc->sc_intr_status24_39); 1122 gp_write(sc, RA_PIO_40_51_INT, sc->sc_intr_status40_51); 1123 gp_write(sc, RA_PIO_40_51_EDGE_INT, sc->sc_intr_status40_51); 1124 #if defined(SLICKROCK) 1125 gp_write(sc, RA_PIO_72_95_INT, sc->sc_intr_status72_95); 1126 gp_write(sc, RA_PIO_72_95_EDGE_INT, sc->sc_intr_status72_95); 1127 #endif 1128 1129 /* Reset until next time */ 1130 sc->sc_intr_status00_23 = 0; 1131 sc->sc_intr_status24_39 = 0; 1132 sc->sc_intr_status40_51 = 0; 1133 sc->sc_intr_status72_95 = 0; 1134 #endif /* MT7628 */ 1135 1136 return 1; 1137 } 1138 1139 /* 1140 * Handle key debouncing for the given pin 1141 */ 1142 static bool 1143 ra_gpio_debounce_pin(ra_gpio_softc_t *sc, struct timeval *tv, u_int pin) 1144 { 1145 RALINK_DEBUG_FUNC_ENTRY(); 1146 1147 /* 1148 * If a pin has a time set, it is waiting for 1149 * a debounce period. Check if it is ready 1150 * to send its event and clean up. Otherwise, 1151 * reschedule 10mSec and try again later. 1152 */ 1153 if (0 != debounce_time[pin].tv_sec) { 1154 if (timercmp(tv, &debounce_time[pin], <)) { 1155 /* 1156 * Haven't hit debounce time, 1157 * need to reschedule 1158 */ 1159 return true; 1160 } 1161 #if defined(SLICKROCK) 1162 switch (debounce_pin[pin]) { 1163 case SOFT_RST_IN_BUTTON: 1164 KNOTE(&knotes, RESET_BUTTON_EVT); 1165 break; 1166 1167 case SS_BUTTON: 1168 KNOTE(&knotes, SS_BUTTON_EVT); 1169 break; 1170 1171 case WPS_BUTTON: 1172 KNOTE(&knotes, WPS_BUTTON_EVT); 1173 break; 1174 1175 case WIFI_ENABLE: 1176 KNOTE(&knotes, WIFI_ENABLE_EVT); 1177 break; 1178 1179 /* 1180 * These events are in case of overcurrent 1181 * on USB/ExpressCard devices. 1182 * If we receive an overcurrent signal, 1183 * turn off power to the device and 1184 * let the USB driver know. 1185 */ 1186 case CURRENT_LIMIT_FLAG_USB1: 1187 ra_gpio_pin_write(sc, POWER_EN_USB1, 0); 1188 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1189 #if 0 1190 cpusb_overcurrent_occurred(CURRENT_LIMIT_FLAG_USB1); 1191 #endif 1192 printf("\nUSB1 current limit received!\n"); 1193 break; 1194 1195 case CURRENT_LIMIT_FLAG_USB2: 1196 ra_gpio_pin_write(sc, POWER_EN_USB2, 0); 1197 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1198 #if 0 1199 cpusb_overcurrent_occurred(CURRENT_LIMIT_FLAG_USB2); 1200 #endif 1201 printf("\nUSB2 current limit received!\n"); 1202 break; 1203 1204 case CURRENT_LIMIT_FLAG_USB3: 1205 ra_gpio_pin_write(sc, POWER_EN_USB3, 0); 1206 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1207 #if 0 1208 cpusb_overcurrent_occurred(CURRENT_LIMIT_FLAG_USB3); 1209 #endif 1210 printf("\nUSB3 current limit received!\n"); 1211 break; 1212 1213 case CURRENT_LIMIT_FLAG_EX1: 1214 ra_gpio_pin_write(sc, POWER_EN_EX1, 0); 1215 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1216 #if 0 1217 cpusb_overcurrent_occurred(debounce_pin[pin]); 1218 #endif 1219 printf("\nExpressCard1 current limit received!\n"); 1220 break; 1221 1222 case CURRENT_LIMIT_FLAG_EX2: 1223 ra_gpio_pin_write(sc, POWER_EN_EX2, 0); 1224 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1225 #if 0 1226 cpusb_overcurrent_occurred(debounce_pin[pin]); 1227 #endif 1228 printf("\nExpressCard2 current limit received!\n"); 1229 break; 1230 1231 default: 1232 printf("\nUnknown debounce pin %d received.\n", 1233 debounce_pin[pin]); 1234 } 1235 #endif/* SLICKROCK */ 1236 #if defined(PEBBLES500) || defined(PEBBLES35) 1237 switch (debounce_pin[pin]) { 1238 case SOFT_RST_IN_BUTTON: 1239 KNOTE(&knotes, RESET_BUTTON_EVT); 1240 break; 1241 1242 case WPS_BUTTON: 1243 KNOTE(&knotes, WPS_BUTTON_EVT); 1244 break; 1245 1246 case EXCARD_ATTACH: 1247 KNOTE(&knotes, EXCARD_ATTACH_EVT); 1248 break; 1249 1250 /* 1251 * These events are in case of overcurrent 1252 * on USB/ExpressCard devices. 1253 * If we receive an overcurrent signal, 1254 * turn off power to the device and 1255 * let the USB driver know. 1256 */ 1257 case CURRENT_LIMIT_FLAG_USB1: 1258 ra_gpio_pin_write(sc, POWER_EN_USB, 0); 1259 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1260 cpusb_overcurrent_occurred(CURRENT_LIMIT_FLAG_USB1); 1261 printf("\nUSB current limit received!\n"); 1262 break; 1263 1264 /* 1265 * If either voltage is over current, 1266 * turn off all ExpressCard power 1267 */ 1268 case CURRENT_LIMIT_FLAG1_3_3v: 1269 case CURRENT_LIMIT_FLAG1_1_5v: 1270 ra_gpio_pin_write(sc, POWER_EN_EXCARD1_3_3v, 0); 1271 ra_gpio_pin_write(sc, POWER_EN_EXCARD1_1_5v, 0); 1272 KNOTE(&knotes, CURRENT_LIMIT_EVT); 1273 cpusb_overcurrent_occurred(debounce_pin[pin]); 1274 printf("\nExpressCard current limit received!\n"); 1275 break; 1276 1277 default: 1278 printf("\nUnknown debounce pin received.\n"); 1279 } 1280 #endif/* PEBBLES500 || PEBBLES35 */ 1281 #if defined(TABLEROCK) || defined(SPOT2) || defined(PUCK) || defined(MOAB) 1282 if (POWER_OFF_BUTTON == debounce_pin[pin]) { 1283 KNOTE(&knotes, POWER_BUTTON_EVT); 1284 } 1285 if (LAN_WAN_SW == debounce_pin[pin]) { 1286 KNOTE(&knotes, LAN_WAN_SW_EVT); 1287 } 1288 if (DOCK_SENSE == debounce_pin[pin]) { 1289 KNOTE(&knotes, DOCK_SENSE_EVT); 1290 } 1291 if (WPS_BUTTON == debounce_pin[pin]) { 1292 KNOTE(&knotes, WPS_BUTTON_EVT); 1293 } 1294 if (IN_5V == debounce_pin[pin]) { 1295 /* Set the charger to match the in 5V line */ 1296 if (ra_gpio_pin_read(sc, IN_5V) == 0) { 1297 ra_gpio_pin_write(sc, CHARGER_OFF, 0); 1298 } else { 1299 ra_gpio_pin_write(sc, CHARGER_OFF, 1); 1300 } 1301 KNOTE(&knotes, IN_5V_EVT); 1302 } 1303 #endif/* TABLEROCK || SPOT2 || PUCK || MOAB */ 1304 /* Re-enable interrupt and reset time */ 1305 enable_gpio_interrupt(sc, debounce_pin[pin]); 1306 debounce_time[pin].tv_sec = 0; 1307 1308 } 1309 return false; 1310 } 1311 1312 /* 1313 * Handle key debouncing. 1314 * Re-enable the key interrupt after DEBOUNCE_TIME 1315 */ 1316 static void 1317 ra_gpio_debounce_process(void *arg) 1318 { 1319 RALINK_DEBUG_FUNC_ENTRY(); 1320 ra_gpio_softc_t * const sc = arg; 1321 bool reschedule = false; 1322 struct timeval now; 1323 1324 microtime(&now); 1325 1326 for (u_int pin=0; pin < __arraycount(debounce_pin); pin++) 1327 if (ra_gpio_debounce_pin(sc, &now, pin)) 1328 reschedule = true; 1329 1330 if (reschedule) 1331 callout_schedule(&sc->sc_tick_callout, MS_TO_HZ(10)); 1332 } 1333 1334 /* 1335 * Handle key and other interrupt debouncing. 1336 */ 1337 static void 1338 ra_gpio_debounce_setup(ra_gpio_softc_t *sc) 1339 { 1340 RALINK_DEBUG_FUNC_ENTRY(); 1341 u_int32_t pin; 1342 struct timeval now; 1343 struct timeval wait = { 1344 .tv_sec = 0, 1345 .tv_usec = (DEBOUNCE_TIME * 1000) 1346 }; 1347 1348 /* 1349 * The 371/372 series are a bit more complex. They have 1350 * interrupt sources across all three interrupt 1351 * registers. 1352 */ 1353 for (int i = 0; i < __arraycount(debounce_pin); i++) { 1354 u_int32_t *intr_status; 1355 int offset; 1356 #if defined(MT7628) 1357 if (debounce_pin[i] < 32) { 1358 intr_status = &sc->sc_intr_status00_31; 1359 offset = 0; 1360 } else if (debounce_pin[i] < 64) { 1361 intr_status = &sc->sc_intr_status32_63; 1362 offset = 32; 1363 } else { 1364 intr_status = &sc->sc_intr_status64_95; 1365 offset = 64; 1366 } 1367 #else /* !MT7628 */ 1368 if (debounce_pin[i] < 24) { 1369 intr_status = &sc->sc_intr_status00_23; 1370 offset = 0; 1371 } else if (debounce_pin[i] < 40) { 1372 intr_status = &sc->sc_intr_status24_39; 1373 offset = 24; 1374 } else if (debounce_pin[i] < 71) { 1375 intr_status = &sc->sc_intr_status40_51; 1376 offset = 40; 1377 } else { 1378 intr_status = &sc->sc_intr_status72_95; 1379 offset = 72; 1380 } 1381 #endif /* !MT7628 */ 1382 if (*intr_status & (1 << (debounce_pin[i] - offset))) { 1383 pin = debounce_pin[i]; 1384 1385 #ifdef ENABLE_RALINK_DEBUG_INFO 1386 if (ra_gpio_pin_read(sc, pin)) { 1387 RALINK_DEBUG(RALINK_DEBUG_INFO, 1388 "%s() button 0x%x, pin %d released\n", 1389 __func__, *intr_status, pin); 1390 } else { 1391 RALINK_DEBUG(RALINK_DEBUG_INFO, 1392 "%s() button 0x%x, pin %d pressed\n", 1393 __func__, *intr_status, pin); 1394 } 1395 #endif 1396 1397 #if 0 1398 /* Mask pin that is being handled */ 1399 *intr_status &= ~((1 << (debounce_pin[i] - offset))); 1400 #endif 1401 1402 /* Handle debouncing. */ 1403 disable_gpio_interrupt(sc, pin); 1404 microtime(&now); 1405 1406 #if defined(TABLEROCK) 1407 /* 1408 * The dock's LAN_WAN switch can cause a fire of 1409 * interrupts if it sticks in the half-way position. 1410 * Ignore it for longer than other buttons. 1411 */ 1412 if (pin == LAN_WAN_SW) { 1413 wait.tv_usec *= 2; 1414 } 1415 #endif 1416 1417 timeradd(&now, &wait, &debounce_time[i]); 1418 } 1419 } 1420 1421 /* If the debounce callout hasn't been scheduled, start it up. */ 1422 if (FALSE == callout_pending(&sc->sc_tick_callout)) { 1423 callout_schedule(&sc->sc_tick_callout, MS_TO_HZ(DEBOUNCE_TIME)); 1424 } 1425 } 1426 1427 /* 1428 * Disable both rising and falling 1429 */ 1430 static void 1431 disable_gpio_interrupt(ra_gpio_softc_t *sc, int pin) 1432 { 1433 RALINK_DEBUG_FUNC_ENTRY(); 1434 const int index = pin_tab_index[pin]; 1435 KASSERTMSG(index != -1, "%s: non-existent pin=%d\n", __func__, pin); 1436 if (index == -1) 1437 return; 1438 1439 const pin_tab_t * const ptp = &pin_tab[index]; 1440 const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base); 1441 uint32_t r; 1442 1443 r = gp_read(sc, ptp->pin_rise.reg); 1444 r &= ~reg_bit; 1445 gp_write(sc, ptp->pin_rise.reg, r); 1446 1447 r = gp_read(sc, ptp->pin_fall.reg); 1448 r &= ~reg_bit; 1449 gp_write(sc, ptp->pin_fall.reg, r); 1450 } 1451 1452 /* 1453 * Restore GPIO interrupt setting 1454 */ 1455 static void 1456 enable_gpio_interrupt(ra_gpio_softc_t *sc, int pin) 1457 { 1458 const int index = pin_tab_index[pin]; 1459 KASSERTMSG(index != -1, "%s: non-existent pin=%d\n", __func__, pin); 1460 if (index == -1) 1461 return; 1462 1463 const pin_tab_t * const ptp = &pin_tab[index]; 1464 const uint32_t mask_bit = 1 << (pin - ptp->pin_mask_base); 1465 const uint32_t reg_bit = 1 << (pin - ptp->pin_reg_base); 1466 uint32_t r; 1467 1468 if (ptp->pin_rise.mask & mask_bit) { 1469 r = gp_read(sc, ptp->pin_rise.reg); 1470 r |= reg_bit; 1471 gp_write(sc, ptp->pin_rise.reg, r); 1472 } 1473 1474 if (ptp->pin_fall.mask & mask_bit) { 1475 r = gp_read(sc, ptp->pin_fall.reg); 1476 r |= reg_bit; 1477 gp_write(sc, ptp->pin_fall.reg, r); 1478 } 1479 } 1480 1481 /* 1482 * XXX this function is obsolete/unused? XXX 1483 * 1484 * Go through each of the interrupts and send the appropriate 1485 * event. 1486 */ 1487 static void 1488 ra_gpio_softintr(void *arg) 1489 { 1490 #if defined(MT7628) 1491 RALINK_DEBUG(RALINK_DEBUG_INFO, 1492 "gpio softintr called with 0x%x, 0x%x, 0x%x\n", 1493 sc->sc_intr_status00_31, sc->sc_intr_status32_63, 1494 sc->sc_intr_status64_95); 1495 #else 1496 RALINK_DEBUG(RALINK_DEBUG_INFO, 1497 "gpio softintr called with 0x%x, 0x%x, 0x%x, 0x%x\n", 1498 sc->sc_intr_status00_23, sc->sc_intr_status24_39, 1499 sc->sc_intr_status40_51, sc->sc_intr_status72_95); 1500 #endif 1501 } 1502 1503 /* 1504 * gpio_event_app_user_attach - called when knote is ADDed 1505 */ 1506 static int 1507 gpio_event_app_user_attach(struct knote *kn) 1508 { 1509 RALINK_DEBUG_0(RALINK_DEBUG_INFO, "%s() %p\n", __func__, kn); 1510 1511 if (NULL == kn) { 1512 RALINK_DEBUG(RALINK_DEBUG_ERROR, "Null kn found\n"); 1513 return 0; 1514 } 1515 1516 kn->kn_flags |= EV_CLEAR; /* automatically set */ 1517 klist_insert(&knotes, kn); 1518 1519 return 0; 1520 } 1521 1522 /* 1523 * gpio_event_app_user_detach - called when knote is DELETEd 1524 */ 1525 static void 1526 gpio_event_app_user_detach(struct knote *kn) 1527 { 1528 RALINK_DEBUG_0(RALINK_DEBUG_INFO, "%s() %p\n", __func__, kn); 1529 if (NULL == kn) { 1530 RALINK_DEBUG(RALINK_DEBUG_ERROR, "Null kn found\n"); 1531 return; 1532 } 1533 klist_remove(&knotes, kn); 1534 } 1535 1536 /* 1537 * gpio_event_app_user_event - called when event is triggered 1538 */ 1539 static int 1540 gpio_event_app_user_event(struct knote *kn, long hint) 1541 { 1542 RALINK_DEBUG_0(RALINK_DEBUG_INFO, "%s() %p hint: %ld\n", 1543 __func__, kn, hint); 1544 1545 if (NULL == kn) { 1546 RALINK_DEBUG(RALINK_DEBUG_ERROR, "Null kn found\n"); 1547 return 0; 1548 } 1549 1550 if (hint != 0) { 1551 kn->kn_data = kn->kn_sdata; 1552 kn->kn_fflags |= hint; 1553 } 1554 1555 return 1; 1556 } 1557 1558 /* 1559 * Blinky light control during boot. 1560 * This marches through the SS/BATT LEDS 1561 * to give an indication something is going on. 1562 */ 1563 void 1564 ra_gpio_toggle_LED(void *arg) 1565 { 1566 RALINK_DEBUG_FUNC_ENTRY(); 1567 ra_gpio_softc_t * const sc = arg; 1568 static int led_index = 0; 1569 static int led_timing_hack = 1; 1570 1571 if ((led_timing_hack >= 6) || 1572 (0 == gpio_driver_blink_leds)) { 1573 /* We're out of boot timing, don't blink LEDs any more */ 1574 return; 1575 } 1576 1577 #if 0 1578 /* Disable lit LED */ 1579 gp_write(sc, SET_SS_LED_REG, 1580 (1 << (led_array1[led_index++] - SS_OFFSET))); 1581 #endif 1582 1583 if (led_index >= (sizeof(led_array1))) { 1584 led_index = 0; 1585 for (int i = 0; i < sizeof(led_array1); i++) { 1586 ra_gpio_pin_write(sc, led_array1[i], 1); 1587 } 1588 } 1589 1590 /* Light next LED */ 1591 ra_gpio_pin_write(sc, led_array1[led_index++], 0); 1592 1593 #if 0 1594 if (led_index == 4) { 1595 led_timing_hack = 1; 1596 } 1597 #endif 1598 1599 #ifdef BOOT_LED_TIMING 1600 /* Setting 3.5 second per LED */ 1601 if ((led_timing_hack) && 1602 (led_timing_hack < 6)) { 1603 led_timing_hack++; 1604 callout_reset(&led_tick_callout, MS_TO_HZ(BOOT_LED_TIMING), 1605 ra_gpio_toggle_LED, sc); 1606 } 1607 #endif 1608 } 1609
Indexes created Sat Sep 20 22:09:52 GMT 2025