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      1 /*	$NetBSD: cl0080.h,v 1.2 2021/12/18 23:45:33 riastradh Exp $	*/
      2 
      3 /* SPDX-License-Identifier: MIT */
      4 #ifndef __NVIF_CL0080_H__
      5 #define __NVIF_CL0080_H__
      6 
      7 struct nv_device_v0 {
      8 	__u8  version;
      9 	__u8  pad01[7];
     10 	__u64 device;	/* device identifier, ~0 for client default */
     11 };
     12 
     13 #define NV_DEVICE_V0_INFO                                                  0x00
     14 #define NV_DEVICE_V0_TIME                                                  0x01
     15 
     16 struct nv_device_info_v0 {
     17 	__u8  version;
     18 #define NV_DEVICE_INFO_V0_IGP                                              0x00
     19 #define NV_DEVICE_INFO_V0_PCI                                              0x01
     20 #define NV_DEVICE_INFO_V0_AGP                                              0x02
     21 #define NV_DEVICE_INFO_V0_PCIE                                             0x03
     22 #define NV_DEVICE_INFO_V0_SOC                                              0x04
     23 	__u8  platform;
     24 	__u16 chipset;	/* from NV_PMC_BOOT_0 */
     25 	__u8  revision;	/* from NV_PMC_BOOT_0 */
     26 #define NV_DEVICE_INFO_V0_TNT                                              0x01
     27 #define NV_DEVICE_INFO_V0_CELSIUS                                          0x02
     28 #define NV_DEVICE_INFO_V0_KELVIN                                           0x03
     29 #define NV_DEVICE_INFO_V0_RANKINE                                          0x04
     30 #define NV_DEVICE_INFO_V0_CURIE                                            0x05
     31 #define NV_DEVICE_INFO_V0_TESLA                                            0x06
     32 #define NV_DEVICE_INFO_V0_FERMI                                            0x07
     33 #define NV_DEVICE_INFO_V0_KEPLER                                           0x08
     34 #define NV_DEVICE_INFO_V0_MAXWELL                                          0x09
     35 #define NV_DEVICE_INFO_V0_PASCAL                                           0x0a
     36 #define NV_DEVICE_INFO_V0_VOLTA                                            0x0b
     37 #define NV_DEVICE_INFO_V0_TURING                                           0x0c
     38 	__u8  family;
     39 	__u8  pad06[2];
     40 	__u64 ram_size;
     41 	__u64 ram_user;
     42 	char  chip[16];
     43 	char  name[64];
     44 };
     45 
     46 struct nv_device_info_v1 {
     47 	__u8  version;
     48 	__u8  count;
     49 	__u8  pad02[6];
     50 	struct nv_device_info_v1_data {
     51 		__u64 mthd; /* NV_DEVICE_INFO_* (see below). */
     52 		__u64 data;
     53 	} data[];
     54 };
     55 
     56 struct nv_device_time_v0 {
     57 	__u8  version;
     58 	__u8  pad01[7];
     59 	__u64 time;
     60 };
     61 
     62 #define NV_DEVICE_INFO_UNIT                               (0xffffffffULL << 32)
     63 #define NV_DEVICE_INFO(n)                          ((n) | (0x00000000ULL << 32))
     64 #define NV_DEVICE_FIFO(n)                          ((n) | (0x00000001ULL << 32))
     65 
     66 /* This will be returned for unsupported queries. */
     67 #define NV_DEVICE_INFO_INVALID                                           ~0ULL
     68 
     69 /* These return a mask of available engines of particular type. */
     70 #define NV_DEVICE_INFO_ENGINE_SW                     NV_DEVICE_INFO(0x00000000)
     71 #define NV_DEVICE_INFO_ENGINE_GR                     NV_DEVICE_INFO(0x00000001)
     72 #define NV_DEVICE_INFO_ENGINE_MPEG                   NV_DEVICE_INFO(0x00000002)
     73 #define NV_DEVICE_INFO_ENGINE_ME                     NV_DEVICE_INFO(0x00000003)
     74 #define NV_DEVICE_INFO_ENGINE_CIPHER                 NV_DEVICE_INFO(0x00000004)
     75 #define NV_DEVICE_INFO_ENGINE_BSP                    NV_DEVICE_INFO(0x00000005)
     76 #define NV_DEVICE_INFO_ENGINE_VP                     NV_DEVICE_INFO(0x00000006)
     77 #define NV_DEVICE_INFO_ENGINE_CE                     NV_DEVICE_INFO(0x00000007)
     78 #define NV_DEVICE_INFO_ENGINE_SEC                    NV_DEVICE_INFO(0x00000008)
     79 #define NV_DEVICE_INFO_ENGINE_MSVLD                  NV_DEVICE_INFO(0x00000009)
     80 #define NV_DEVICE_INFO_ENGINE_MSPDEC                 NV_DEVICE_INFO(0x0000000a)
     81 #define NV_DEVICE_INFO_ENGINE_MSPPP                  NV_DEVICE_INFO(0x0000000b)
     82 #define NV_DEVICE_INFO_ENGINE_MSENC                  NV_DEVICE_INFO(0x0000000c)
     83 #define NV_DEVICE_INFO_ENGINE_VIC                    NV_DEVICE_INFO(0x0000000d)
     84 #define NV_DEVICE_INFO_ENGINE_SEC2                   NV_DEVICE_INFO(0x0000000e)
     85 #define NV_DEVICE_INFO_ENGINE_NVDEC                  NV_DEVICE_INFO(0x0000000f)
     86 #define NV_DEVICE_INFO_ENGINE_NVENC                  NV_DEVICE_INFO(0x00000010)
     87 
     88 /* Returns the number of available channels. */
     89 #define NV_DEVICE_FIFO_CHANNELS                      NV_DEVICE_FIFO(0x00000000)
     90 
     91 /* Returns a mask of available runlists. */
     92 #define NV_DEVICE_FIFO_RUNLISTS                      NV_DEVICE_FIFO(0x00000001)
     93 
     94 /* These return a mask of engines available on a particular runlist. */
     95 #define NV_DEVICE_FIFO_RUNLIST_ENGINES(n)     ((n) + NV_DEVICE_FIFO(0x00000010))
     96 #define NV_DEVICE_FIFO_RUNLIST_ENGINES__SIZE                                64
     97 #endif
     98