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    Searched defs:reg_val (Results 1 - 20 of 20) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
amdgpu_dmub_reg.c 81 uint32_t reg_val; local in function:dmub_reg_update
89 reg_val = srv->funcs.reg_read(srv->user_ctx, addr);
90 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
91 srv->funcs.reg_write(srv->user_ctx, addr, reg_val);
94 void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,
105 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
106 srv->funcs.reg_write(srv->user_ctx, addr, reg_val);
112 uint32_t reg_val = srv->funcs.reg_read(srv->user_ctx, addr) local in function:dmub_reg_get
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  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dsb.c 205 u32 reg_val; local in function:intel_dsb_indexed_reg_write
233 reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
234 if (reg_val != i915_mmio_reg_offset(reg)) {
intel_dp_aux_backlight.c 35 u8 reg_val = 0; local in function:set_aux_backlight_enable
42 &reg_val) < 0) {
48 reg_val |= DP_EDP_BACKLIGHT_ENABLE;
50 reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
53 reg_val) != 1) {
intel_display.c 8071 u32 reg_val; local in function:vlv_pllb_recal_opamp
8077 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8078 reg_val &= 0xffffff00;
8079 reg_val |= 0x00000030;
8080 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8082 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8083 reg_val &= 0x00ffffff;
8084 reg_val |= 0x8c000000;
8085 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8087 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1))
8223 u32 coreclk, reg_val; local in function:vlv_prepare_pll
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  /src/sys/dev/i2c/
axp809.c 206 u_int vol, reg_val; local in function:axp809_set_voltage
216 reg_val = 0;
221 ++reg_val;
225 ++reg_val;
236 val |= __SHIFTIN(reg_val, c->c_voltage_mask);
252 int reg_val, error; local in function:axp809_get_voltage
264 reg_val = __SHIFTOUT(val, c->c_voltage_mask);
265 if (reg_val < c->c_step1cnt) {
266 *pvol = c->c_min + reg_val * c->c_step1;
269 ((reg_val - c->c_step1cnt) * c->c_step2)
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axppmic.c 596 u_int vol, reg_val; local in function:axppmic_set_voltage
606 reg_val = 0;
611 ++reg_val;
619 ++reg_val;
629 val |= __SHIFTIN(reg_val, c->c_voltage_mask);
640 int reg_val, error; local in function:axppmic_get_voltage
652 reg_val = __SHIFTOUT(val, c->c_voltage_mask);
653 if (reg_val < c->c_step1cnt) {
654 *pvol = c->c_min + reg_val * c->c_step1;
657 ((reg_val - c->c_step1cnt) * c->c_step2)
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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
amdgpu_dc_helper.c 171 uint32_t reg_val)
189 cmd_buf->write_values[offload->reg_seq_count] = reg_val;
254 uint32_t reg_val; local in function:generic_reg_update_ex
270 reg_val = dm_read_reg(ctx, addr);
271 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
272 dm_write_reg(ctx, addr, reg_val);
273 return reg_val;
277 uint32_t addr, uint32_t reg_val, int n,
293 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value
334 uint32_t reg_val = dm_read_reg(ctx, addr); local in function:generic_reg_get
343 uint32_t reg_val = dm_read_reg(ctx, addr); local in function:generic_reg_get2
354 uint32_t reg_val = dm_read_reg(ctx, addr); local in function:generic_reg_get3
367 uint32_t reg_val = dm_read_reg(ctx, addr); local in function:generic_reg_get4
382 uint32_t reg_val = dm_read_reg(ctx, addr); local in function:generic_reg_get5
399 uint32_t reg_val = dm_read_reg(ctx, addr); local in function:generic_reg_get6
418 uint32_t reg_val = dm_read_reg(ctx, addr); local in function:generic_reg_get7
439 uint32_t reg_val = dm_read_reg(ctx, addr); local in function:generic_reg_get8
487 uint32_t reg_val; local in function:generic_reg_wait
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  /src/sys/dev/pci/ixgbe/
ixgbe_vf.c 265 u32 reg_val; local in function:ixgbe_stop_adapter_vf
286 reg_val = IXGBE_VFREAD_REG(hw, IXGBE_VFRXDCTL(i));
287 reg_val &= ~IXGBE_RXDCTL_ENABLE;
288 IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val);
ixgbe_x550.c 2325 u32 reg_val; local in function:ixgbe_setup_kr_speed_x550em
2329 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2333 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2334 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2339 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2343 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2347 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2353 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2358 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2359 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN
2810 u16 reg_slice, reg_val; local in function:ixgbe_setup_mac_link_sfp_x550em
2854 u32 reg_val; local in function:ixgbe_setup_sfi_x550a
3009 u32 reg_val; local in function:ixgbe_setup_ixfi_x550em_x
3080 u32 reg_val; local in function:ixgbe_setup_ixfi_x550em
3238 u32 reg_val; local in function:ixgbe_setup_phy_loopback_x550em
4103 u32 pause, asm_dir, reg_val; local in function:ixgbe_setup_fc_X550em
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ixgbe_common.c 1119 u32 reg_val; local in function:ixgbe_stop_adapter_generic
1165 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1166 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1167 reg_val |= IXGBE_RXDCTL_SWFLSH;
1168 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
3415 * @reg_val: Value we read from AUTOC
3419 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3422 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3429 * @reg_val: value to write to AUTOC
3435 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked
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  /src/sys/external/bsd/drm2/dist/drm/i915/gem/
i915_gem_stolen.c 180 u32 reg_val = intel_uncore_read(uncore, local in function:g4x_get_stolen_reserved
187 IS_GM45(i915) ? "CTG" : "ELK", reg_val);
189 if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0)
197 reg_val);
199 if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK))
202 if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK))
205 *base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16;
206 WARN_ON((reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base);
216 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); local in function:gen6_get_stolen_reserved
218 DRM_DEBUG_DRIVER("GEN6_STOLEN_RESERVED = %08x\n", reg_val);
249 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); local in function:vlv_get_stolen_reserved
278 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); local in function:gen7_get_stolen_reserved
305 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); local in function:chv_get_stolen_reserved
338 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); local in function:bdw_get_stolen_reserved
358 u64 reg_val = intel_uncore_read64(uncore, GEN6_STOLEN_RESERVED); local in function:icl_get_stolen_reserved
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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hubp.c 56 uint32_t reg_val = REG_READ(DCHUBP_CNTL); local in function:hubp1_set_blank
58 if (reg_val) {
62 * we just wrote reg_val to non-0, if it stay 0
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hubp.c 924 uint32_t reg_val = REG_READ(DCHUBP_CNTL); local in function:hubp2_set_blank
926 if (reg_val) {
930 * we just wrote reg_val to non-0, if it stay 0
  /src/sys/dev/usb/
if_smsc.c 581 uint32_t reg_val; local in function:smsc_chip_init
618 if ((err = smsc_readreg(un, SMSC_HW_CFG, &reg_val)) != 0) {
622 reg_val |= SMSC_HW_CFG_BIR;
623 smsc_writereg(un, SMSC_HW_CFG, reg_val);
653 if ((err = smsc_readreg(un, SMSC_HW_CFG, &reg_val)) < 0) {
663 reg_val |= (SMSC_HW_CFG_MEF | SMSC_HW_CFG_BCE);
669 reg_val |= ETHER_ALIGN << SMSC_HW_CFG_RXDOFF_SHIFT;
671 smsc_writereg(un, SMSC_HW_CFG, reg_val);
683 reg_val = SMSC_LED_GPIO_CFG_SPD_LED | SMSC_LED_GPIO_CFG_LNK_LED |
685 smsc_writereg(un, SMSC_LED_GPIO_CFG, reg_val);
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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_resource.c 667 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); local in function:read_dce_straps
669 straps->audio_stream_number = get_reg_field_value(reg_val,
672 straps->hdmi_disable = get_reg_field_value(reg_val,
676 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
677 straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
  /src/sys/external/bsd/drm2/dist/drm/i915/
intel_uncore.h 482 u32 reg_val; local in function:intel_uncore_write_and_verify
485 reg_val = intel_uncore_read(uncore, reg);
487 return (reg_val & mask) != expected_val ? -EINVAL : 0;
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
handlers.c 718 u32 reg_val; local in function:dp_tp_status_mmio_write
721 reg_val = *((u32 *)p_data);
724 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
726 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
  /src/sys/external/bsd/ena-com/
ena_admin_defs.h 929 uint32_t reg_val; member in struct:ena_admin_ena_mmio_req_read_less_resp
  /src/sys/external/bsd/ena-com/ena_defs/
ena_admin_defs.h 1001 uint32_t reg_val; member in struct:ena_admin_ena_mmio_req_read_less_resp
  /src/sys/dev/pci/
if_iwm.c 1821 uint32_t reg_val = 0; local in function:iwm_nic_config
1830 reg_val |= IWM_CSR_HW_REV_STEP(sc->sc_hw_rev) <<
1832 reg_val |= IWM_CSR_HW_REV_DASH(sc->sc_hw_rev) <<
1836 reg_val |= radio_cfg_type << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE;
1837 reg_val |= radio_cfg_step << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP;
1838 reg_val |= radio_cfg_dash << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH;
1840 IWM_WRITE(sc, IWM_CSR_HW_IF_CONFIG_REG, reg_val);

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