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  /xsrc/external/mit/MesaLib/dist/src/mesa/x86-64/
x86-64.c 44 extern void _mesa_x86_64_cpuid(unsigned int *regs);
77 unsigned int regs[4]; local
93 regs[0] = 0x80000001;
94 regs[1] = 0x00000000;
95 regs[2] = 0x00000000;
96 regs[3] = 0x00000000;
97 _mesa_x86_64_cpuid(regs);
98 if (regs[3] & (1U << 31)) {
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/x86-64/
x86-64.c 44 extern void _mesa_x86_64_cpuid(unsigned int *regs);
77 unsigned int regs[4]; local
93 regs[0] = 0x80000001;
94 regs[1] = 0x00000000;
95 regs[2] = 0x00000000;
96 regs[3] = 0x00000000;
97 _mesa_x86_64_cpuid(regs);
98 if (regs[3] & (1U << 31)) {
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/lima/ir/gp/
optimize.c 175 /* Kill all the writes to regs that are never read. All the known
181 BITSET_WORD *regs = rzalloc_array(comp, BITSET_WORD, comp->cur_reg); local
187 BITSET_SET(regs, load->reg->index);
196 if (!BITSET_TEST(regs, store->reg->index))
201 ralloc_free(regs);
  /xsrc/external/mit/MesaLib/dist/src/util/
register_allocate_test.cpp 49 thumb_checks(struct ra_regs *regs, unsigned reg32_base, unsigned reg64_base)
51 struct ra_class *reg32low = ra_get_class_from_index(regs, 0);
52 struct ra_class *reg64low = ra_get_class_from_index(regs, 1);
53 struct ra_class *reg96 = ra_get_class_from_index(regs, 2);
69 /* These individual regs should conflict with themselves, but nothing else from their class */
88 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, 100, true); local
95 struct ra_class *reg32low = ra_alloc_reg_class(regs);
99 ra_add_transitive_reg_conflict(regs, i, vreg);
104 struct ra_class *reg64low = ra_alloc_reg_class(regs);
108 ra_add_transitive_reg_conflict(regs, i, vreg)
128 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, 16, true); local
152 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, 16, true); local
173 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, base_regs, true); local
    [all...]
register_allocate_internal.h 47 struct ra_reg *regs; member in struct:ra_regs
64 BITSET_WORD *regs; member in struct:ra_class
67 * Number of regs after each bit in *regs that are also conflicted by an
75 * This is "how many regs are in the set."
130 struct ra_regs *regs; member in struct:ra_graph
u_cpu_detect.c 480 uint32_t regs[4]; local
522 cpuid(0x00000001, regs);
523 unsigned apic_id = regs[1] >> 24;
527 if (regs[3] & (1 << 28))
528 core_count = (regs[1] >> 16) & 0xff;
533 cpuid_count(0x8000001D, 3, regs);
534 unsigned cache_level = (regs[0] >> 5) & 0x7;
535 unsigned cores_per_L3 = ((regs[0] >> 14) & 0xfff) + 1;
691 uint32_t regs[4]; local
697 cpuid(0x00000000, regs);
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/amd/common/
sid_tables.py 370 regs = {} variable
376 previous = regs.get(reg.r_name, None)
386 regs[reg.r_name] = reg
  /xsrc/external/mit/xf86-video-tdfx/dist/src/
tdfx_dri.h 8 drm_handle_t regs; member in struct:__anon9438
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/
etnaviv_compiler_nir_ra.c 87 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, ETNA_MAX_TEMPS * local
95 classes[c] = ra_alloc_reg_class(regs);
104 ra_add_reg_conflict(regs, NUM_REG_TYPES * r + i,
110 ra_set_finalize(regs, q_values);
112 return regs;
119 struct ra_regs *regs = compiler->regs; local
141 struct ra_graph *g = ra_alloc_interference_graph(regs, num_nodes);
176 ra_set_node_class(g, i, ra_get_class_from_index(regs, comp));
201 ra_set_node_class(g, index, ra_get_class_from_index(regs, REG_CLASS_VEC4))
    [all...]
etnaviv_compiler.h 54 struct ra_regs *regs; member in struct:etna_compiler
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/compiler/
radeon_regalloc.h 55 struct ra_regs *regs; member in struct:rc_regalloc_state
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/compiler/
radeon_regalloc.h 55 struct ra_regs *regs; member in struct:rc_regalloc_state
  /xsrc/external/mit/MesaLib.old/dist/src/util/
u_cpu_detect.c 386 uint32_t regs[4]; local
389 cpuid_count(0x8000001D, 3, regs);
390 unsigned cache_level = (regs[0] >> 5) & 0x7;
391 unsigned cores_per_cache = ((regs[0] >> 14) & 0xfff) + 1;
438 uint32_t regs[4]; local
444 cpuid(0x00000000, regs);
446 if (regs[0] >= 0x00000001) {
483 if (util_cpu_caps.has_avx && regs[0] >= 0x00000007) {
506 if (regs[1] == 0x756e6547 && regs[2] == 0x6c65746e && regs[3] == 0x49656e69)
    [all...]
  /xsrc/external/mit/xf86-video-intel-old/dist/src/
i830_dri.h 17 drm_handle_t regs; member in struct:_I830DRIRec
  /xsrc/external/mit/xf86-video-ngle/dist/src/
ngle.h 55 void *regs; member in struct:__anon9065
88 volatile uint32_t *ptr = (uint32_t *)((uint8_t *)fPtr->regs + offset);
95 volatile uint8_t *ptr = (uint8_t *)fPtr->regs + offset;
102 volatile uint32_t *ptr = (uint32_t *)((uint8_t *)fPtr->regs + offset);
109 volatile uint8_t *ptr = (uint8_t *)fPtr->regs + offset;
  /xsrc/external/mit/xf86-video-openchrome/dist/src/
via_dri.h 48 viaRegion regs; member in struct:__anon9143
  /xsrc/external/mit/MesaLib/dist/src/amd/compiler/
aco_validate.cpp 944 std::array<unsigned, 2048> regs; /* register file in bytes */ local
945 regs.fill(0);
958 if (regs[reg.reg_b + i]) {
961 i, tmp.id(), regs[reg.reg_b + i]);
963 regs[reg.reg_b + i] = tmp.id();
966 regs.fill(0);
976 if (regs[reg.reg_b + i])
980 tmp.id(), regs[reg.reg_b + i]);
1006 regs[reg.reg_b + i] = tmp.id();
1012 /* remove killed p_phi operands from regs */
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
ir3_postsched.c 355 * Note, this table is twice as big as the # of regs, to deal with
356 * half-precision regs. The approach differs depending on whether
363 struct ir3_postsched_node *regs[2 * 256]; member in struct:ir3_postsched_deps_state
371 assert((idx) < ARRAY_SIZE((state)->regs)); \
372 &(state)->regs[(idx)]; \
418 * If positive, corresponds to node->instr->regs[src_n]. If negative, then
441 num += ARRAY_SIZE(state->regs) / 2;
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/lima/ir/gp/
scheduler.c 630 gpir_node *regs[GPIR_VALUE_REG_NUM] = {0}; local
636 gpir_node *reg = regs[node->value_reg];
647 regs[node->value_reg] = node;
674 gpir_reg *regs[GPIR_VALUE_REG_NUM] = {0}; local
676 if (!regs[reg->index])
677 regs[reg->index] = reg;
679 list_splicetail(&reg->defs_list, &regs[reg->index]->defs_list);
680 list_splicetail(&reg->uses_list, &regs[reg->index]->uses_list);
686 gpir_reg *reg = regs[i];
  /xsrc/external/mit/xf86-video-ag10e/dist/src/
ag10e.h 43 unsigned char *regs; member in struct:__anon6698
  /xsrc/external/mit/xf86-video-intel-old/dist/src/ch7xxx/
ch7xxx.c 70 uint8_t regs[CH7xxx_NUM_REGS]; member in struct:ch7xxx_reg_state
282 ErrorF("%02X ", dev_priv->ModeReg.regs[i]);
  /xsrc/external/mit/xf86-video-mach64/dist/src/
mach64_dri.h 115 drm_handle_t regs; member in struct:__anon9015
  /xsrc/external/mit/xf86-video-sis/dist/src/
sis_dri.h 75 sisRegion regs; /* MMIO registers */ member in struct:__anon9405
  /xsrc/external/mit/xf86-video-xgi/dist/src/
xgi_dri.h 77 xgiRegion regs, agp; member in struct:__anon9683
  /xsrc/external/mit/xorg-server/dist/hw/sun/
sunCfb.c 383 struct cg2fb regs; member in struct:__anon9909
390 volatile struct cg2statusreg *regp = &fb->regs.status.reg;
394 fb->regs.redmap[index] = rmap[index];
395 fb->regs.greenmap[index] = gmap[index];
396 fb->regs.bluemap[index] = bmap[index];
409 rmap[index] = fb->regs.redmap[index];
410 gmap[index] = fb->regs.greenmap[index];
411 bmap[index] = fb->regs.bluemap[index];
422 ((CG2Ptr)sunFbs[screen].fb)->regs.ppmask.reg = 1;
429 volatile struct cg2statusreg *regp = &fb->regs.status.reg
    [all...]

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