| /xsrc/external/mit/MesaLib/dist/src/amd/common/ |
| ac_binary.h | 48 unsigned rsrc1; member in struct:ac_shader_config
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| radv_pipeline_cache.c | 37 uint32_t rsrc1, rsrc2; member in struct:cache_entry_variant_info
327 variant->rsrc1 = info.rsrc1;
416 info.rsrc1 = variants[i]->rsrc1;
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| radv_shader.h | 316 unsigned rsrc1; member in struct:radv_shader_variant
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| radv_device.c | 2600 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | local
2603 map[1] = rsrc1;
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| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| aco_statistics.cpp | 103 BlockCycleEstimator::resource rsrc1; member in struct:aco::perf_info
192 if (perf.rsrc1 != resource_count) {
193 res_available[(int)perf.rsrc1] = cur_cycle + perf.cost1;
194 res_usage[(int)perf.rsrc1] += perf.cost1;
206 if (perf.rsrc1 != resource_count)
207 cost = MAX2(cost, res_available[(int)perf.rsrc1] - cur_cycle);
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| si_compute.c | 97 uint32_t rsrc1 = code_object->compute_pgm_resource_registers; local
101 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
102 out_config->rsrc1 = rsrc1;
195 shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) /
204 shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
544 radeon_emit(config->rsrc1);
550 config->rsrc1, config->rsrc2);
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| si_state_shaders.c | 542 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
923 uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) | local
937 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
941 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
1513 uint32_t rsrc1 = local
1527 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1537 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1733 uint32_t rsrc1 = local
1739 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1742 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| si_compute.c | 71 uint32_t rsrc1 = code_object->compute_pgm_resource_registers; local
75 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
76 out_config->rsrc1 = rsrc1;
168 shader->config.rsrc1 =
497 radeon_emit(cs, config->rsrc1);
501 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
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| si_shader.h | 574 unsigned rsrc1; member in struct:si_shader_config
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| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| radv_shader.h | 480 uint32_t rsrc1; member in struct:radv_shader_prolog
|
| radv_cmd_buffer.c | 2883 uint32_t rsrc1 = vs_shader->config.rsrc1; local
2884 if (chip < GFX10 && G_00B228_SGPRS(prolog->rsrc1) > G_00B228_SGPRS(vs_shader->config.rsrc1))
2885 rsrc1 = (rsrc1 & C_00B228_SGPRS) | (prolog->rsrc1 & ~C_00B228_SGPRS);
2890 assert(G_00B848_VGPRS(vs_shader->config.rsrc1) >= G_00B848_VGPRS(prolog->rsrc1));
2913 radeon_set_sh_reg(cmd_buffer->cs, rsrc1_reg, rsrc1);
[all...] |
| radv_device.c | 3930 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE(1); local
3932 map[1] = rsrc1;
|
