1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#include "ac_exp_param.h" 26#include "ac_shader_util.h" 27#include "compiler/nir/nir_serialize.h" 28#include "nir/tgsi_to_nir.h" 29#include "si_build_pm4.h" 30#include "sid.h" 31#include "util/crc32.h" 32#include "util/disk_cache.h" 33#include "util/hash_table.h" 34#include "util/mesa-sha1.h" 35#include "util/u_async_debug.h" 36#include "util/u_memory.h" 37#include "util/u_prim.h" 38#include "tgsi/tgsi_from_mesa.h" 39 40/* SHADER_CACHE */ 41 42/** 43 * Return the IR key for the shader cache. 44 */ 45void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es, 46 unsigned char ir_sha1_cache_key[20]) 47{ 48 struct blob blob = {}; 49 unsigned ir_size; 50 void *ir_binary; 51 52 if (sel->nir_binary) { 53 ir_binary = sel->nir_binary; 54 ir_size = sel->nir_size; 55 } else { 56 assert(sel->nir); 57 58 blob_init(&blob); 59 nir_serialize(&blob, sel->nir, true); 60 ir_binary = blob.data; 61 ir_size = blob.size; 62 } 63 64 /* These settings affect the compilation, but they are not derived 65 * from the input shader IR. 66 */ 67 unsigned shader_variant_flags = 0; 68 69 if (ngg) 70 shader_variant_flags |= 1 << 0; 71 if (sel->nir) 72 shader_variant_flags |= 1 << 1; 73 if (si_get_wave_size(sel->screen, sel->info.stage, ngg, es) == 32) 74 shader_variant_flags |= 1 << 2; 75 if (sel->info.stage == MESA_SHADER_FRAGMENT && 76 /* Derivatives imply helper invocations so check for needs_quad_helper_invocations. */ 77 sel->info.base.fs.needs_quad_helper_invocations && 78 sel->info.base.fs.uses_discard && 79 sel->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL)) 80 shader_variant_flags |= 1 << 3; 81 /* use_ngg_culling disables NGG passthrough for non-culling shaders to reduce context 82 * rolls, which can be changed with AMD_DEBUG=nonggc or AMD_DEBUG=nggc. 83 */ 84 if (sel->screen->use_ngg_culling) 85 shader_variant_flags |= 1 << 4; 86 87 /* bit gap */ 88 89 if (sel->screen->options.no_infinite_interp) 90 shader_variant_flags |= 1 << 7; 91 if (sel->screen->options.clamp_div_by_zero) 92 shader_variant_flags |= 1 << 8; 93 if (sel->screen->debug_flags & DBG(GISEL)) 94 shader_variant_flags |= 1 << 9; 95 if ((sel->info.stage == MESA_SHADER_VERTEX || 96 sel->info.stage == MESA_SHADER_TESS_EVAL || 97 sel->info.stage == MESA_SHADER_GEOMETRY) && 98 !es && 99 sel->screen->options.vrs2x2) 100 shader_variant_flags |= 1 << 10; 101 if (sel->screen->options.inline_uniforms) 102 shader_variant_flags |= 1 << 11; 103 104 struct mesa_sha1 ctx; 105 _mesa_sha1_init(&ctx); 106 _mesa_sha1_update(&ctx, &shader_variant_flags, 4); 107 _mesa_sha1_update(&ctx, ir_binary, ir_size); 108 if (sel->info.stage == MESA_SHADER_VERTEX || sel->info.stage == MESA_SHADER_TESS_EVAL || 109 sel->info.stage == MESA_SHADER_GEOMETRY) 110 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so)); 111 _mesa_sha1_final(&ctx, ir_sha1_cache_key); 112 113 if (ir_binary == blob.data) 114 blob_finish(&blob); 115} 116 117/** Copy "data" to "ptr" and return the next dword following copied data. */ 118static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size) 119{ 120 /* data may be NULL if size == 0 */ 121 if (size) 122 memcpy(ptr, data, size); 123 ptr += DIV_ROUND_UP(size, 4); 124 return ptr; 125} 126 127/** Read data from "ptr". Return the next dword following the data. */ 128static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size) 129{ 130 memcpy(data, ptr, size); 131 ptr += DIV_ROUND_UP(size, 4); 132 return ptr; 133} 134 135/** 136 * Write the size as uint followed by the data. Return the next dword 137 * following the copied data. 138 */ 139static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size) 140{ 141 *ptr++ = size; 142 return write_data(ptr, data, size); 143} 144 145/** 146 * Read the size as uint followed by the data. Return both via parameters. 147 * Return the next dword following the data. 148 */ 149static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size) 150{ 151 *size = *ptr++; 152 assert(*data == NULL); 153 if (!*size) 154 return ptr; 155 *data = malloc(*size); 156 return read_data(ptr, *data, *size); 157} 158 159/** 160 * Return the shader binary in a buffer. The first 4 bytes contain its size 161 * as integer. 162 */ 163static void *si_get_shader_binary(struct si_shader *shader) 164{ 165 /* There is always a size of data followed by the data itself. */ 166 unsigned llvm_ir_size = 167 shader->binary.llvm_ir_string ? strlen(shader->binary.llvm_ir_string) + 1 : 0; 168 169 /* Refuse to allocate overly large buffers and guard against integer 170 * overflow. */ 171 if (shader->binary.elf_size > UINT_MAX / 4 || llvm_ir_size > UINT_MAX / 4) 172 return NULL; 173 174 unsigned size = 4 + /* total size */ 175 4 + /* CRC32 of the data below */ 176 align(sizeof(shader->config), 4) + align(sizeof(shader->info), 4) + 4 + 177 align(shader->binary.elf_size, 4) + 4 + align(llvm_ir_size, 4); 178 void *buffer = CALLOC(1, size); 179 uint32_t *ptr = (uint32_t *)buffer; 180 181 if (!buffer) 182 return NULL; 183 184 *ptr++ = size; 185 ptr++; /* CRC32 is calculated at the end. */ 186 187 ptr = write_data(ptr, &shader->config, sizeof(shader->config)); 188 ptr = write_data(ptr, &shader->info, sizeof(shader->info)); 189 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size); 190 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size); 191 assert((char *)ptr - (char *)buffer == size); 192 193 /* Compute CRC32. */ 194 ptr = (uint32_t *)buffer; 195 ptr++; 196 *ptr = util_hash_crc32(ptr + 1, size - 8); 197 198 return buffer; 199} 200 201static bool si_load_shader_binary(struct si_shader *shader, void *binary) 202{ 203 uint32_t *ptr = (uint32_t *)binary; 204 uint32_t size = *ptr++; 205 uint32_t crc32 = *ptr++; 206 unsigned chunk_size; 207 unsigned elf_size; 208 209 if (util_hash_crc32(ptr, size - 8) != crc32) { 210 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n"); 211 return false; 212 } 213 214 ptr = read_data(ptr, &shader->config, sizeof(shader->config)); 215 ptr = read_data(ptr, &shader->info, sizeof(shader->info)); 216 ptr = read_chunk(ptr, (void **)&shader->binary.elf_buffer, &elf_size); 217 shader->binary.elf_size = elf_size; 218 ptr = read_chunk(ptr, (void **)&shader->binary.llvm_ir_string, &chunk_size); 219 220 return true; 221} 222 223/** 224 * Insert a shader into the cache. It's assumed the shader is not in the cache. 225 * Use si_shader_cache_load_shader before calling this. 226 */ 227void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20], 228 struct si_shader *shader, bool insert_into_disk_cache) 229{ 230 void *hw_binary; 231 struct hash_entry *entry; 232 uint8_t key[CACHE_KEY_SIZE]; 233 bool memory_cache_full = sscreen->shader_cache_size >= sscreen->shader_cache_max_size; 234 235 if (!insert_into_disk_cache && memory_cache_full) 236 return; 237 238 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key); 239 if (entry) 240 return; /* already added */ 241 242 hw_binary = si_get_shader_binary(shader); 243 if (!hw_binary) 244 return; 245 246 if (!memory_cache_full) { 247 if (_mesa_hash_table_insert(sscreen->shader_cache, 248 mem_dup(ir_sha1_cache_key, 20), 249 hw_binary) == NULL) { 250 FREE(hw_binary); 251 return; 252 } 253 /* The size is stored at the start of the binary */ 254 sscreen->shader_cache_size += *(uint32_t*)hw_binary; 255 } 256 257 if (sscreen->disk_shader_cache && insert_into_disk_cache) { 258 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, key); 259 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary, *((uint32_t *)hw_binary), NULL); 260 } 261 262 if (memory_cache_full) 263 FREE(hw_binary); 264} 265 266bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20], 267 struct si_shader *shader) 268{ 269 struct hash_entry *entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key); 270 271 if (entry) { 272 if (si_load_shader_binary(shader, entry->data)) { 273 p_atomic_inc(&sscreen->num_memory_shader_cache_hits); 274 return true; 275 } 276 } 277 p_atomic_inc(&sscreen->num_memory_shader_cache_misses); 278 279 if (!sscreen->disk_shader_cache) 280 return false; 281 282 unsigned char sha1[CACHE_KEY_SIZE]; 283 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, sha1); 284 285 size_t binary_size; 286 uint8_t *buffer = disk_cache_get(sscreen->disk_shader_cache, sha1, &binary_size); 287 if (buffer) { 288 if (binary_size >= sizeof(uint32_t) && *((uint32_t *)buffer) == binary_size) { 289 if (si_load_shader_binary(shader, buffer)) { 290 free(buffer); 291 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, false); 292 p_atomic_inc(&sscreen->num_disk_shader_cache_hits); 293 return true; 294 } 295 } else { 296 /* Something has gone wrong discard the item from the cache and 297 * rebuild/link from source. 298 */ 299 assert(!"Invalid radeonsi shader disk cache item!"); 300 disk_cache_remove(sscreen->disk_shader_cache, sha1); 301 } 302 } 303 304 free(buffer); 305 p_atomic_inc(&sscreen->num_disk_shader_cache_misses); 306 return false; 307} 308 309static uint32_t si_shader_cache_key_hash(const void *key) 310{ 311 /* Take the first dword of SHA1. */ 312 return *(uint32_t *)key; 313} 314 315static bool si_shader_cache_key_equals(const void *a, const void *b) 316{ 317 /* Compare SHA1s. */ 318 return memcmp(a, b, 20) == 0; 319} 320 321static void si_destroy_shader_cache_entry(struct hash_entry *entry) 322{ 323 FREE((void *)entry->key); 324 FREE(entry->data); 325} 326 327bool si_init_shader_cache(struct si_screen *sscreen) 328{ 329 (void)simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain); 330 sscreen->shader_cache = 331 _mesa_hash_table_create(NULL, si_shader_cache_key_hash, si_shader_cache_key_equals); 332 sscreen->shader_cache_size = 0; 333 /* Maximum size: 64MB on 32 bits, 1GB else */ 334 sscreen->shader_cache_max_size = ((sizeof(void *) == 4) ? 64 : 1024) * 1024 * 1024; 335 336 return sscreen->shader_cache != NULL; 337} 338 339void si_destroy_shader_cache(struct si_screen *sscreen) 340{ 341 if (sscreen->shader_cache) 342 _mesa_hash_table_destroy(sscreen->shader_cache, si_destroy_shader_cache_entry); 343 simple_mtx_destroy(&sscreen->shader_cache_mutex); 344} 345 346/* SHADER STATES */ 347 348bool si_shader_mem_ordered(struct si_shader *shader) 349{ 350 if (shader->selector->screen->info.chip_class < GFX10) 351 return false; 352 353 const struct si_shader_info *info = &shader->selector->info; 354 const struct si_shader_info *prev_info = 355 shader->previous_stage_sel ? &shader->previous_stage_sel->info : NULL; 356 357 bool sampler_or_bvh = info->uses_vmem_return_type_sampler_or_bvh; 358 bool other = info->uses_vmem_return_type_other || 359 info->uses_indirect_descriptor || 360 shader->config.scratch_bytes_per_wave || 361 (info->stage == MESA_SHADER_FRAGMENT && 362 (info->base.fs.uses_fbfetch_output || 363 shader->key.part.ps.prolog.poly_stipple)); 364 365 if (prev_info) { 366 sampler_or_bvh |= prev_info->uses_vmem_return_type_sampler_or_bvh; 367 other |= prev_info->uses_vmem_return_type_other || 368 prev_info->uses_indirect_descriptor; 369 } 370 371 /* Return true if both types of VMEM that return something are used. */ 372 return sampler_or_bvh && other; 373} 374 375static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shader_selector *tes, 376 struct si_shader *shader) 377{ 378 const struct si_shader_info *info = &tes->info; 379 unsigned tes_prim_mode = info->base.tess.primitive_mode; 380 unsigned tes_spacing = info->base.tess.spacing; 381 bool tes_vertex_order_cw = !info->base.tess.ccw; 382 bool tes_point_mode = info->base.tess.point_mode; 383 unsigned type, partitioning, topology, distribution_mode; 384 385 switch (tes_prim_mode) { 386 case GL_LINES: 387 type = V_028B6C_TESS_ISOLINE; 388 break; 389 case GL_TRIANGLES: 390 type = V_028B6C_TESS_TRIANGLE; 391 break; 392 case GL_QUADS: 393 type = V_028B6C_TESS_QUAD; 394 break; 395 default: 396 assert(0); 397 return; 398 } 399 400 switch (tes_spacing) { 401 case TESS_SPACING_FRACTIONAL_ODD: 402 partitioning = V_028B6C_PART_FRAC_ODD; 403 break; 404 case TESS_SPACING_FRACTIONAL_EVEN: 405 partitioning = V_028B6C_PART_FRAC_EVEN; 406 break; 407 case TESS_SPACING_EQUAL: 408 partitioning = V_028B6C_PART_INTEGER; 409 break; 410 default: 411 assert(0); 412 return; 413 } 414 415 if (tes_point_mode) 416 topology = V_028B6C_OUTPUT_POINT; 417 else if (tes_prim_mode == GL_LINES) 418 topology = V_028B6C_OUTPUT_LINE; 419 else if (tes_vertex_order_cw) 420 /* for some reason, this must be the other way around */ 421 topology = V_028B6C_OUTPUT_TRIANGLE_CCW; 422 else 423 topology = V_028B6C_OUTPUT_TRIANGLE_CW; 424 425 if (sscreen->info.has_distributed_tess) { 426 if (sscreen->info.family == CHIP_FIJI || sscreen->info.family >= CHIP_POLARIS10) 427 distribution_mode = V_028B6C_TRAPEZOIDS; 428 else 429 distribution_mode = V_028B6C_DONUTS; 430 } else 431 distribution_mode = V_028B6C_NO_DIST; 432 433 shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) | 434 S_028B6C_TOPOLOGY(topology) | 435 S_028B6C_DISTRIBUTION_MODE(distribution_mode); 436} 437 438/* Polaris needs different VTX_REUSE_DEPTH settings depending on 439 * whether the "fractional odd" tessellation spacing is used. 440 * 441 * Possible VGT configurations and which state should set the register: 442 * 443 * Reg set in | VGT shader configuration | Value 444 * ------------------------------------------------------ 445 * VS as VS | VS | 30 446 * VS as ES | ES -> GS -> VS | 30 447 * TES as VS | LS -> HS -> VS | 14 or 30 448 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30 449 */ 450static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_shader_selector *sel, 451 struct si_shader *shader) 452{ 453 if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.chip_class >= GFX10) 454 return; 455 456 /* VS as VS, or VS as ES: */ 457 if ((sel->info.stage == MESA_SHADER_VERTEX && 458 (!shader->key.as_ls && !shader->is_gs_copy_shader)) || 459 /* TES as VS, or TES as ES: */ 460 sel->info.stage == MESA_SHADER_TESS_EVAL) { 461 unsigned vtx_reuse_depth = 30; 462 463 if (sel->info.stage == MESA_SHADER_TESS_EVAL && 464 sel->info.base.tess.spacing == TESS_SPACING_FRACTIONAL_ODD) 465 vtx_reuse_depth = 14; 466 467 shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth; 468 } 469} 470 471static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader) 472{ 473 si_pm4_clear_state(&shader->pm4); 474 shader->pm4.is_shader = true; 475 return &shader->pm4; 476} 477 478static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader, 479 unsigned num_always_on_user_sgprs) 480{ 481 struct si_shader_selector *vs = 482 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector; 483 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs; 484 485 /* 1 SGPR is reserved for the vertex buffer pointer. */ 486 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1); 487 488 if (num_vbos_in_user_sgprs) 489 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4; 490 491 /* Add the pointer to VBO descriptors. */ 492 return num_always_on_user_sgprs + 1; 493} 494 495/* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */ 496static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen, struct si_shader *shader, 497 bool legacy_vs_prim_id) 498{ 499 assert(shader->selector->info.stage == MESA_SHADER_VERTEX || 500 (shader->previous_stage_sel && shader->previous_stage_sel->info.stage == MESA_SHADER_VERTEX)); 501 502 /* GFX6-9 LS (VertexID, RelAutoIndex, InstanceID / StepRate0, InstanceID) 503 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0, VSPrimID, InstanceID) 504 * GFX10 LS (VertexID, RelAutoIndex, UserVGPR1, UserVGPR2 or InstanceID) 505 * GFX10 ES,VS (VertexID, UserVGPR1, UserVGPR2 or VSPrimID, UserVGPR3 or InstanceID) 506 */ 507 bool is_ls = shader->selector->info.stage == MESA_SHADER_TESS_CTRL || shader->key.as_ls; 508 unsigned max = 0; 509 510 if (shader->info.uses_instanceid) { 511 if (sscreen->info.chip_class >= GFX10) 512 max = MAX2(max, 3); 513 else if (is_ls) 514 max = MAX2(max, 2); /* use (InstanceID / StepRate0) because StepRate0 == 1 */ 515 else 516 max = MAX2(max, 1); /* use (InstanceID / StepRate0) because StepRate0 == 1 */ 517 } 518 519 if (legacy_vs_prim_id) 520 max = MAX2(max, 2); /* VSPrimID */ 521 522 if (is_ls) 523 max = MAX2(max, 1); /* RelAutoIndex */ 524 525 return max; 526} 527 528static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader) 529{ 530 struct si_pm4_state *pm4; 531 uint64_t va; 532 533 assert(sscreen->info.chip_class <= GFX8); 534 535 pm4 = si_get_shader_pm4_state(shader); 536 if (!pm4) 537 return; 538 539 va = shader->bo->gpu_address; 540 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); 541 542 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) | 543 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) | 544 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) | 545 S_00B528_DX10_CLAMP(1) | S_00B528_FLOAT_MODE(shader->config.float_mode); 546 shader->config.rsrc2 = 547 S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) | 548 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0); 549} 550 551static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader) 552{ 553 struct si_pm4_state *pm4; 554 uint64_t va; 555 556 pm4 = si_get_shader_pm4_state(shader); 557 if (!pm4) 558 return; 559 560 va = shader->bo->gpu_address; 561 562 if (sscreen->info.chip_class >= GFX9) { 563 if (sscreen->info.chip_class >= GFX10) { 564 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); 565 } else { 566 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8); 567 } 568 569 unsigned num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR); 570 571 shader->config.rsrc2 = S_00B42C_USER_SGPR(num_user_sgprs) | 572 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0); 573 574 if (sscreen->info.chip_class >= GFX10) 575 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5); 576 else 577 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5); 578 } else { 579 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8); 580 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, 581 S_00B424_MEM_BASE(sscreen->info.address32_hi >> 8)); 582 583 shader->config.rsrc2 = S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) | S_00B42C_OC_LDS_EN(1) | 584 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0); 585 } 586 587 si_pm4_set_reg( 588 pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 589 S_00B428_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) | 590 (sscreen->info.chip_class <= GFX9 ? S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) 591 : 0) | 592 S_00B428_DX10_CLAMP(1) | S_00B428_MEM_ORDERED(si_shader_mem_ordered(shader)) | 593 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) | 594 S_00B428_FLOAT_MODE(shader->config.float_mode) | 595 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 596 ? si_get_vs_vgpr_comp_cnt(sscreen, shader, false) 597 : 0)); 598 599 if (sscreen->info.chip_class <= GFX8) { 600 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2); 601 } 602} 603 604static void si_emit_shader_es(struct si_context *sctx) 605{ 606 struct si_shader *shader = sctx->queued.named.es; 607 if (!shader) 608 return; 609 610 radeon_begin(&sctx->gfx_cs); 611 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE, 612 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, 613 shader->selector->esgs_itemsize / 4); 614 615 if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL) 616 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM, 617 shader->vgt_tf_param); 618 619 if (shader->vgt_vertex_reuse_block_cntl) 620 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 621 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, 622 shader->vgt_vertex_reuse_block_cntl); 623 radeon_end_update_context_roll(sctx); 624} 625 626static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader) 627{ 628 struct si_pm4_state *pm4; 629 unsigned num_user_sgprs; 630 unsigned vgpr_comp_cnt; 631 uint64_t va; 632 unsigned oc_lds_en; 633 634 assert(sscreen->info.chip_class <= GFX8); 635 636 pm4 = si_get_shader_pm4_state(shader); 637 if (!pm4) 638 return; 639 640 pm4->atom.emit = si_emit_shader_es; 641 va = shader->bo->gpu_address; 642 643 if (shader->selector->info.stage == MESA_SHADER_VERTEX) { 644 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false); 645 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR); 646 } else if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL) { 647 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2; 648 num_user_sgprs = SI_TES_NUM_USER_SGPR; 649 } else 650 unreachable("invalid shader selector type"); 651 652 oc_lds_en = shader->selector->info.stage == MESA_SHADER_TESS_EVAL ? 1 : 0; 653 654 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); 655 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, 656 S_00B324_MEM_BASE(sscreen->info.address32_hi >> 8)); 657 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES, 658 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) | 659 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) | 660 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B328_DX10_CLAMP(1) | 661 S_00B328_FLOAT_MODE(shader->config.float_mode)); 662 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES, 663 S_00B32C_USER_SGPR(num_user_sgprs) | S_00B32C_OC_LDS_EN(oc_lds_en) | 664 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0)); 665 666 if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL) 667 si_set_tesseval_regs(sscreen, shader->selector, shader); 668 669 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader); 670} 671 672void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *gs, 673 struct gfx9_gs_info *out) 674{ 675 unsigned gs_num_invocations = MAX2(gs->info.base.gs.invocations, 1); 676 unsigned input_prim = gs->info.base.gs.input_primitive; 677 bool uses_adjacency = 678 input_prim >= PIPE_PRIM_LINES_ADJACENCY && input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY; 679 680 /* All these are in dwords: */ 681 /* We can't allow using the whole LDS, because GS waves compete with 682 * other shader stages for LDS space. */ 683 const unsigned max_lds_size = 8 * 1024; 684 const unsigned esgs_itemsize = es->esgs_itemsize / 4; 685 unsigned esgs_lds_size; 686 687 /* All these are per subgroup: */ 688 const unsigned max_out_prims = 32 * 1024; 689 const unsigned max_es_verts = 255; 690 const unsigned ideal_gs_prims = 64; 691 unsigned max_gs_prims, gs_prims; 692 unsigned min_es_verts, es_verts, worst_case_es_verts; 693 694 if (uses_adjacency || gs_num_invocations > 1) 695 max_gs_prims = 127 / gs_num_invocations; 696 else 697 max_gs_prims = 255; 698 699 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations. 700 * Make sure we don't go over the maximum value. 701 */ 702 if (gs->info.base.gs.vertices_out > 0) { 703 max_gs_prims = 704 MIN2(max_gs_prims, max_out_prims / (gs->info.base.gs.vertices_out * gs_num_invocations)); 705 } 706 assert(max_gs_prims > 0); 707 708 /* If the primitive has adjacency, halve the number of vertices 709 * that will be reused in multiple primitives. 710 */ 711 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1); 712 713 gs_prims = MIN2(ideal_gs_prims, max_gs_prims); 714 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts); 715 716 /* Compute ESGS LDS size based on the worst case number of ES vertices 717 * needed to create the target number of GS prims per subgroup. 718 */ 719 esgs_lds_size = esgs_itemsize * worst_case_es_verts; 720 721 /* If total LDS usage is too big, refactor partitions based on ratio 722 * of ESGS item sizes. 723 */ 724 if (esgs_lds_size > max_lds_size) { 725 /* Our target GS Prims Per Subgroup was too large. Calculate 726 * the maximum number of GS Prims Per Subgroup that will fit 727 * into LDS, capped by the maximum that the hardware can support. 728 */ 729 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)), max_gs_prims); 730 assert(gs_prims > 0); 731 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts); 732 733 esgs_lds_size = esgs_itemsize * worst_case_es_verts; 734 assert(esgs_lds_size <= max_lds_size); 735 } 736 737 /* Now calculate remaining ESGS information. */ 738 if (esgs_lds_size) 739 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts); 740 else 741 es_verts = max_es_verts; 742 743 /* Vertices for adjacency primitives are not always reused, so restore 744 * it for ES_VERTS_PER_SUBGRP. 745 */ 746 min_es_verts = gs->gs_input_verts_per_prim; 747 748 /* For normal primitives, the VGT only checks if they are past the ES 749 * verts per subgroup after allocating a full GS primitive and if they 750 * are, kick off a new subgroup. But if those additional ES verts are 751 * unique (e.g. not reused) we need to make sure there is enough LDS 752 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP. 753 */ 754 es_verts -= min_es_verts - 1; 755 756 out->es_verts_per_subgroup = es_verts; 757 out->gs_prims_per_subgroup = gs_prims; 758 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations; 759 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup * gs->info.base.gs.vertices_out; 760 out->esgs_ring_size = esgs_lds_size; 761 762 assert(out->max_prims_per_subgroup <= max_out_prims); 763} 764 765static void si_emit_shader_gs(struct si_context *sctx) 766{ 767 struct si_shader *shader = sctx->queued.named.gs; 768 if (!shader) 769 return; 770 771 radeon_begin(&sctx->gfx_cs); 772 773 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2 774 * R_028A68_VGT_GSVS_RING_OFFSET_3 */ 775 radeon_opt_set_context_reg3( 776 sctx, R_028A60_VGT_GSVS_RING_OFFSET_1, SI_TRACKED_VGT_GSVS_RING_OFFSET_1, 777 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1, shader->ctx_reg.gs.vgt_gsvs_ring_offset_2, 778 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3); 779 780 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */ 781 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE, 782 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE, 783 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize); 784 785 /* R_028B38_VGT_GS_MAX_VERT_OUT */ 786 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT, 787 shader->ctx_reg.gs.vgt_gs_max_vert_out); 788 789 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1 790 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */ 791 radeon_opt_set_context_reg4( 792 sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE, SI_TRACKED_VGT_GS_VERT_ITEMSIZE, 793 shader->ctx_reg.gs.vgt_gs_vert_itemsize, shader->ctx_reg.gs.vgt_gs_vert_itemsize_1, 794 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2, shader->ctx_reg.gs.vgt_gs_vert_itemsize_3); 795 796 /* R_028B90_VGT_GS_INSTANCE_CNT */ 797 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT, 798 shader->ctx_reg.gs.vgt_gs_instance_cnt); 799 800 if (sctx->chip_class >= GFX9) { 801 /* R_028A44_VGT_GS_ONCHIP_CNTL */ 802 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL, 803 shader->ctx_reg.gs.vgt_gs_onchip_cntl); 804 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */ 805 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, 806 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP, 807 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup); 808 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */ 809 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE, 810 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, 811 shader->ctx_reg.gs.vgt_esgs_ring_itemsize); 812 813 if (shader->key.part.gs.es->info.stage == MESA_SHADER_TESS_EVAL) 814 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM, 815 shader->vgt_tf_param); 816 if (shader->vgt_vertex_reuse_block_cntl) 817 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 818 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, 819 shader->vgt_vertex_reuse_block_cntl); 820 } 821 radeon_end_update_context_roll(sctx); 822 823 /* These don't cause any context rolls. */ 824 radeon_begin_again(&sctx->gfx_cs); 825 if (sctx->chip_class >= GFX7) { 826 radeon_opt_set_sh_reg(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, 827 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS, 828 shader->ctx_reg.gs.spi_shader_pgm_rsrc3_gs); 829 } 830 if (sctx->chip_class >= GFX10) { 831 radeon_opt_set_sh_reg(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS, 832 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS, 833 shader->ctx_reg.gs.spi_shader_pgm_rsrc4_gs); 834 } 835 radeon_end(); 836} 837 838static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) 839{ 840 struct si_shader_selector *sel = shader->selector; 841 const ubyte *num_components = sel->info.num_stream_output_components; 842 unsigned gs_num_invocations = sel->info.base.gs.invocations; 843 struct si_pm4_state *pm4; 844 uint64_t va; 845 unsigned max_stream = util_last_bit(sel->info.base.gs.active_stream_mask); 846 unsigned offset; 847 848 pm4 = si_get_shader_pm4_state(shader); 849 if (!pm4) 850 return; 851 852 pm4->atom.emit = si_emit_shader_gs; 853 854 offset = num_components[0] * sel->info.base.gs.vertices_out; 855 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset; 856 857 if (max_stream >= 2) 858 offset += num_components[1] * sel->info.base.gs.vertices_out; 859 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset; 860 861 if (max_stream >= 3) 862 offset += num_components[2] * sel->info.base.gs.vertices_out; 863 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset; 864 865 if (max_stream >= 4) 866 offset += num_components[3] * sel->info.base.gs.vertices_out; 867 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset; 868 869 /* The GSVS_RING_ITEMSIZE register takes 15 bits */ 870 assert(offset < (1 << 15)); 871 872 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->info.base.gs.vertices_out; 873 874 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0]; 875 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 2) ? num_components[1] : 0; 876 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 3) ? num_components[2] : 0; 877 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 4) ? num_components[3] : 0; 878 879 shader->ctx_reg.gs.vgt_gs_instance_cnt = 880 S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0); 881 882 /* Copy over fields from the GS copy shader to make them easily accessible from GS. */ 883 shader->pa_cl_vs_out_cntl = sel->gs_copy_shader->pa_cl_vs_out_cntl; 884 885 va = shader->bo->gpu_address; 886 887 if (sscreen->info.chip_class >= GFX9) { 888 unsigned input_prim = sel->info.base.gs.input_primitive; 889 gl_shader_stage es_stage = shader->key.part.gs.es->info.stage; 890 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt; 891 892 if (es_stage == MESA_SHADER_VERTEX) { 893 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false); 894 } else if (es_stage == MESA_SHADER_TESS_EVAL) 895 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2; 896 else 897 unreachable("invalid shader selector type"); 898 899 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and 900 * VGPR[0:4] are always loaded. 901 */ 902 if (sel->info.uses_invocationid) 903 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */ 904 else if (sel->info.uses_primid) 905 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */ 906 else if (input_prim >= PIPE_PRIM_TRIANGLES) 907 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */ 908 else 909 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */ 910 911 unsigned num_user_sgprs; 912 if (es_stage == MESA_SHADER_VERTEX) 913 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR); 914 else 915 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR; 916 917 if (sscreen->info.chip_class >= GFX10) { 918 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); 919 } else { 920 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8); 921 } 922 923 uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) | 924 S_00B228_MEM_ORDERED(si_shader_mem_ordered(shader)) | 925 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) | 926 S_00B228_FLOAT_MODE(shader->config.float_mode) | 927 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt); 928 uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) | 929 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | 930 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL) | 931 S_00B22C_LDS_SIZE(shader->config.lds_size) | 932 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0); 933 934 if (sscreen->info.chip_class >= GFX10) { 935 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5); 936 } else { 937 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8); 938 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5); 939 } 940 941 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1); 942 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2); 943 944 shader->ctx_reg.gs.spi_shader_pgm_rsrc3_gs = S_00B21C_CU_EN(0xffff) | 945 S_00B21C_WAVE_LIMIT(0x3F); 946 shader->ctx_reg.gs.spi_shader_pgm_rsrc4_gs = 947 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0); 948 949 shader->ctx_reg.gs.vgt_gs_onchip_cntl = 950 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) | 951 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) | 952 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup); 953 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup = 954 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup); 955 shader->ctx_reg.gs.vgt_esgs_ring_itemsize = shader->key.part.gs.es->esgs_itemsize / 4; 956 957 if (es_stage == MESA_SHADER_TESS_EVAL) 958 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, shader); 959 960 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es, shader); 961 } else { 962 shader->ctx_reg.gs.spi_shader_pgm_rsrc3_gs = S_00B21C_CU_EN(0xffff) | 963 S_00B21C_WAVE_LIMIT(0x3F); 964 965 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8); 966 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, 967 S_00B224_MEM_BASE(sscreen->info.address32_hi >> 8)); 968 969 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 970 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | 971 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) | 972 S_00B228_DX10_CLAMP(1) | S_00B228_FLOAT_MODE(shader->config.float_mode)); 973 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, 974 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) | 975 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0)); 976 } 977} 978 979bool gfx10_is_ngg_passthrough(struct si_shader *shader) 980{ 981 struct si_shader_selector *sel = shader->selector; 982 983 /* Never use NGG passthrough if culling is possible even when it's not used by this shader, 984 * so that we don't get context rolls when enabling and disabling NGG passthrough. 985 */ 986 if (sel->screen->use_ngg_culling) 987 return false; 988 989 /* The definition of NGG passthrough is: 990 * - user GS is turned off (no amplification, no GS instancing, and no culling) 991 * - VGT_ESGS_RING_ITEMSIZE is ignored (behaving as if it was equal to 1) 992 * - vertex indices are packed into 1 VGPR 993 * - Dimgrey and later chips can optionally skip the gs_alloc_req message 994 * 995 * NGG passthrough still allows the use of LDS. 996 */ 997 return sel->info.stage != MESA_SHADER_GEOMETRY && !shader->key.opt.ngg_culling; 998} 999 1000/* Common tail code for NGG primitive shaders. */ 1001static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader *shader) 1002{ 1003 radeon_begin(&sctx->gfx_cs); 1004 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP, 1005 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, 1006 shader->ctx_reg.ngg.ge_max_output_per_subgroup); 1007 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL, 1008 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl); 1009 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN, 1010 shader->ctx_reg.ngg.vgt_primitiveid_en); 1011 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL, 1012 shader->ctx_reg.ngg.vgt_gs_onchip_cntl); 1013 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT, 1014 shader->ctx_reg.ngg.vgt_gs_instance_cnt); 1015 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE, 1016 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, 1017 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize); 1018 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG, 1019 shader->ctx_reg.ngg.spi_vs_out_config); 1020 radeon_opt_set_context_reg2( 1021 sctx, R_028708_SPI_SHADER_IDX_FORMAT, SI_TRACKED_SPI_SHADER_IDX_FORMAT, 1022 shader->ctx_reg.ngg.spi_shader_idx_format, shader->ctx_reg.ngg.spi_shader_pos_format); 1023 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL, 1024 shader->ctx_reg.ngg.pa_cl_vte_cntl); 1025 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL, 1026 shader->ctx_reg.ngg.pa_cl_ngg_cntl); 1027 1028 radeon_end_update_context_roll(sctx); 1029 1030 /* These don't cause a context roll. */ 1031 radeon_begin_again(&sctx->gfx_cs); 1032 radeon_opt_set_uconfig_reg(sctx, R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC, 1033 shader->ctx_reg.ngg.ge_pc_alloc); 1034 radeon_opt_set_sh_reg(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, 1035 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS, 1036 shader->ctx_reg.ngg.spi_shader_pgm_rsrc3_gs); 1037 radeon_opt_set_sh_reg(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS, 1038 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS, 1039 shader->ctx_reg.ngg.spi_shader_pgm_rsrc4_gs); 1040 radeon_end(); 1041} 1042 1043static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx) 1044{ 1045 struct si_shader *shader = sctx->queued.named.gs; 1046 if (!shader) 1047 return; 1048 1049 gfx10_emit_shader_ngg_tail(sctx, shader); 1050} 1051 1052static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx) 1053{ 1054 struct si_shader *shader = sctx->queued.named.gs; 1055 if (!shader) 1056 return; 1057 1058 radeon_begin(&sctx->gfx_cs); 1059 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM, 1060 shader->vgt_tf_param); 1061 radeon_end_update_context_roll(sctx); 1062 1063 gfx10_emit_shader_ngg_tail(sctx, shader); 1064} 1065 1066static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx) 1067{ 1068 struct si_shader *shader = sctx->queued.named.gs; 1069 if (!shader) 1070 return; 1071 1072 radeon_begin(&sctx->gfx_cs); 1073 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT, 1074 shader->ctx_reg.ngg.vgt_gs_max_vert_out); 1075 radeon_end_update_context_roll(sctx); 1076 1077 gfx10_emit_shader_ngg_tail(sctx, shader); 1078} 1079 1080static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx) 1081{ 1082 struct si_shader *shader = sctx->queued.named.gs; 1083 1084 if (!shader) 1085 return; 1086 1087 radeon_begin(&sctx->gfx_cs); 1088 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT, 1089 shader->ctx_reg.ngg.vgt_gs_max_vert_out); 1090 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM, 1091 shader->vgt_tf_param); 1092 radeon_end_update_context_roll(sctx); 1093 1094 gfx10_emit_shader_ngg_tail(sctx, shader); 1095} 1096 1097unsigned si_get_input_prim(const struct si_shader_selector *gs, const struct si_shader_key *key) 1098{ 1099 if (gs->info.stage == MESA_SHADER_GEOMETRY) 1100 return gs->info.base.gs.input_primitive; 1101 1102 if (gs->info.stage == MESA_SHADER_TESS_EVAL) { 1103 if (gs->info.base.tess.point_mode) 1104 return PIPE_PRIM_POINTS; 1105 if (gs->info.base.tess.primitive_mode == GL_LINES) 1106 return PIPE_PRIM_LINES; 1107 return PIPE_PRIM_TRIANGLES; 1108 } 1109 1110 if (key->opt.ngg_culling & SI_NGG_CULL_LINES) 1111 return PIPE_PRIM_LINES; 1112 1113 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */ 1114} 1115 1116static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, 1117 const struct si_shader *shader, bool ngg) 1118{ 1119 /* Clip distances can be killed, but cull distances can't. */ 1120 unsigned clipcull_mask = (sel->clipdist_mask & ~shader->key.opt.kill_clip_distances) | 1121 sel->culldist_mask; 1122 bool writes_psize = sel->info.writes_psize && !shader->key.opt.kill_pointsize; 1123 bool misc_vec_ena = writes_psize || (sel->info.writes_edgeflag && !ngg) || 1124 sel->screen->options.vrs2x2 || 1125 sel->info.writes_layer || sel->info.writes_viewport_index; 1126 1127 return S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipcull_mask & 0x0F) != 0) | 1128 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipcull_mask & 0xF0) != 0) | 1129 S_02881C_USE_VTX_POINT_SIZE(writes_psize) | 1130 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) | 1131 S_02881C_USE_VTX_VRS_RATE(sel->screen->options.vrs2x2) | 1132 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) | 1133 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) | 1134 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) | 1135 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena); 1136} 1137 1138/** 1139 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader 1140 * in NGG mode. 1141 */ 1142static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader) 1143{ 1144 const struct si_shader_selector *gs_sel = shader->selector; 1145 const struct si_shader_info *gs_info = &gs_sel->info; 1146 const gl_shader_stage gs_stage = shader->selector->info.stage; 1147 const struct si_shader_selector *es_sel = 1148 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector; 1149 const struct si_shader_info *es_info = &es_sel->info; 1150 const gl_shader_stage es_stage = es_sel->info.stage; 1151 unsigned num_user_sgprs; 1152 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt; 1153 uint64_t va; 1154 bool window_space = gs_info->stage == MESA_SHADER_VERTEX ? 1155 gs_info->base.vs.window_space_position : 0; 1156 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid; 1157 unsigned gs_num_invocations = MAX2(gs_sel->info.base.gs.invocations, 1); 1158 unsigned input_prim = si_get_input_prim(gs_sel, &shader->key); 1159 bool break_wave_at_eoi = false; 1160 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader); 1161 if (!pm4) 1162 return; 1163 1164 if (es_stage == MESA_SHADER_TESS_EVAL) { 1165 pm4->atom.emit = gs_stage == MESA_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs 1166 : gfx10_emit_shader_ngg_tess_nogs; 1167 } else { 1168 pm4->atom.emit = gs_stage == MESA_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs 1169 : gfx10_emit_shader_ngg_notess_nogs; 1170 } 1171 1172 va = shader->bo->gpu_address; 1173 1174 if (es_stage == MESA_SHADER_VERTEX) { 1175 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false); 1176 1177 if (es_info->base.vs.blit_sgprs_amd) { 1178 num_user_sgprs = 1179 SI_SGPR_VS_BLIT_DATA + es_info->base.vs.blit_sgprs_amd; 1180 } else { 1181 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR); 1182 } 1183 } else { 1184 assert(es_stage == MESA_SHADER_TESS_EVAL); 1185 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2; 1186 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR; 1187 1188 if (es_enable_prim_id || gs_info->uses_primid) 1189 break_wave_at_eoi = true; 1190 } 1191 1192 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and 1193 * VGPR[0:4] are always loaded. 1194 * 1195 * Vertex shaders always need to load VGPR3, because they need to 1196 * pass edge flags for decomposed primitives (such as quads) to the PA 1197 * for the GL_LINE polygon mode to skip rendering lines on inner edges. 1198 */ 1199 if (gs_info->uses_invocationid || 1200 (gfx10_edgeflags_have_effect(shader) && !gfx10_is_ngg_passthrough(shader))) 1201 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */ 1202 else if ((gs_stage == MESA_SHADER_GEOMETRY && gs_info->uses_primid) || 1203 (gs_stage == MESA_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id)) 1204 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */ 1205 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader)) 1206 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */ 1207 else 1208 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */ 1209 1210 unsigned wave_size = si_get_shader_wave_size(shader); 1211 unsigned late_alloc_wave64, cu_mask; 1212 1213 ac_compute_late_alloc(&sscreen->info, true, shader->key.opt.ngg_culling, 1214 shader->config.scratch_bytes_per_wave > 0, 1215 &late_alloc_wave64, &cu_mask); 1216 1217 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); 1218 si_pm4_set_reg( 1219 pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 1220 S_00B228_VGPRS((shader->config.num_vgprs - 1) / (wave_size == 32 ? 8 : 4)) | 1221 S_00B228_FLOAT_MODE(shader->config.float_mode) | S_00B228_DX10_CLAMP(1) | 1222 S_00B228_MEM_ORDERED(si_shader_mem_ordered(shader)) | 1223 /* Disable the WGP mode on gfx10.3 because it can hang. (it happened on VanGogh) 1224 * Let's disable it on all chips that disable exactly 1 CU per SA for GS. */ 1225 S_00B228_WGP_MODE(sscreen->info.chip_class == GFX10) | 1226 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt)); 1227 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, 1228 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) | 1229 S_00B22C_USER_SGPR(num_user_sgprs) | 1230 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | 1231 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) | 1232 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL) | 1233 S_00B22C_LDS_SIZE(shader->config.lds_size)); 1234 1235 shader->ctx_reg.ngg.spi_shader_pgm_rsrc3_gs = S_00B21C_CU_EN(cu_mask) | 1236 S_00B21C_WAVE_LIMIT(0x3F); 1237 shader->ctx_reg.ngg.spi_shader_pgm_rsrc4_gs = 1238 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64); 1239 1240 nparams = MAX2(shader->info.nr_param_exports, 1); 1241 shader->ctx_reg.ngg.spi_vs_out_config = 1242 S_0286C4_VS_EXPORT_COUNT(nparams - 1) | 1243 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0); 1244 1245 shader->ctx_reg.ngg.spi_shader_idx_format = 1246 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP); 1247 shader->ctx_reg.ngg.spi_shader_pos_format = 1248 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | 1249 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP 1250 : V_02870C_SPI_SHADER_NONE) | 1251 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP 1252 : V_02870C_SPI_SHADER_NONE) | 1253 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP 1254 : V_02870C_SPI_SHADER_NONE); 1255 1256 shader->ctx_reg.ngg.vgt_primitiveid_en = 1257 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) | 1258 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id || 1259 gs_sel->info.writes_primid); 1260 1261 if (gs_stage == MESA_SHADER_GEOMETRY) { 1262 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4; 1263 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->info.base.gs.vertices_out; 1264 } else { 1265 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1; 1266 } 1267 1268 if (es_stage == MESA_SHADER_TESS_EVAL) 1269 si_set_tesseval_regs(sscreen, es_sel, shader); 1270 1271 shader->ctx_reg.ngg.vgt_gs_onchip_cntl = 1272 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) | 1273 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) | 1274 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations); 1275 shader->ctx_reg.ngg.ge_max_output_per_subgroup = 1276 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts); 1277 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl = S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) | 1278 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */ 1279 shader->ctx_reg.ngg.vgt_gs_instance_cnt = 1280 S_028B90_CNT(gs_num_invocations) | S_028B90_ENABLE(gs_num_invocations > 1) | 1281 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(shader->ngg.max_vert_out_per_gs_instance); 1282 1283 /* Output hw-generated edge flags if needed and pass them via the prim 1284 * export to prevent drawing lines on internal edges of decomposed 1285 * primitives (such as quads) with polygon mode = lines. 1286 */ 1287 shader->ctx_reg.ngg.pa_cl_ngg_cntl = 1288 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gfx10_edgeflags_have_effect(shader)) | 1289 /* Reuse for NGG. */ 1290 S_028838_VERTEX_REUSE_DEPTH(sscreen->info.chip_class >= GFX10_3 ? 30 : 0); 1291 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, shader, true); 1292 1293 /* Oversubscribe PC. This improves performance when there are too many varyings. */ 1294 unsigned oversub_pc_factor = 1; 1295 1296 if (shader->key.opt.ngg_culling) { 1297 /* Be more aggressive with NGG culling. */ 1298 if (shader->info.nr_param_exports > 4) 1299 oversub_pc_factor = 4; 1300 else if (shader->info.nr_param_exports > 2) 1301 oversub_pc_factor = 3; 1302 else 1303 oversub_pc_factor = 2; 1304 } 1305 1306 unsigned oversub_pc_lines = 1307 late_alloc_wave64 ? (sscreen->info.pc_lines / 4) * oversub_pc_factor : 0; 1308 shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(oversub_pc_lines > 0) | 1309 S_030980_NUM_PC_LINES(oversub_pc_lines - 1); 1310 1311 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) | 1312 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) | 1313 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi); 1314 1315 /* On gfx10, the GE only checks against the maximum number of ES verts after 1316 * allocating a full GS primitive. So we need to ensure that whenever 1317 * this check passes, there is enough space for a full primitive without 1318 * vertex reuse. VERT_GRP_SIZE=256 doesn't need this. We should always get 256 1319 * if we have enough LDS. 1320 * 1321 * Tessellation is unaffected because it always sets GE_CNTL.VERT_GRP_SIZE = 0. 1322 */ 1323 if ((sscreen->info.chip_class == GFX10) && 1324 (es_stage == MESA_SHADER_VERTEX || gs_stage == MESA_SHADER_VERTEX) && /* = no tess */ 1325 shader->ngg.hw_max_esverts != 256 && 1326 shader->ngg.hw_max_esverts > 5) { 1327 /* This could be based on the input primitive type. 5 is the worst case 1328 * for primitive types with adjacency. 1329 */ 1330 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE; 1331 shader->ge_cntl |= S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5); 1332 } 1333 1334 if (window_space) { 1335 shader->ctx_reg.ngg.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1); 1336 } else { 1337 shader->ctx_reg.ngg.pa_cl_vte_cntl = 1338 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) | 1339 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) | 1340 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1); 1341 } 1342 1343 shader->ctx_reg.ngg.vgt_stages.u.ngg = 1; 1344 shader->ctx_reg.ngg.vgt_stages.u.streamout = gs_sel->so.num_outputs; 1345 shader->ctx_reg.ngg.vgt_stages.u.ngg_passthrough = gfx10_is_ngg_passthrough(shader); 1346} 1347 1348static void si_emit_shader_vs(struct si_context *sctx) 1349{ 1350 struct si_shader *shader = sctx->queued.named.vs; 1351 if (!shader) 1352 return; 1353 1354 radeon_begin(&sctx->gfx_cs); 1355 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE, SI_TRACKED_VGT_GS_MODE, 1356 shader->ctx_reg.vs.vgt_gs_mode); 1357 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN, 1358 shader->ctx_reg.vs.vgt_primitiveid_en); 1359 1360 if (sctx->chip_class <= GFX8) { 1361 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF, 1362 shader->ctx_reg.vs.vgt_reuse_off); 1363 } 1364 1365 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG, 1366 shader->ctx_reg.vs.spi_vs_out_config); 1367 1368 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT, 1369 SI_TRACKED_SPI_SHADER_POS_FORMAT, 1370 shader->ctx_reg.vs.spi_shader_pos_format); 1371 1372 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL, 1373 shader->ctx_reg.vs.pa_cl_vte_cntl); 1374 1375 if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL) 1376 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM, 1377 shader->vgt_tf_param); 1378 1379 if (shader->vgt_vertex_reuse_block_cntl) 1380 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 1381 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, 1382 shader->vgt_vertex_reuse_block_cntl); 1383 1384 /* Required programming for tessellation. (legacy pipeline only) */ 1385 if (sctx->chip_class >= GFX10 && shader->selector->info.stage == MESA_SHADER_TESS_EVAL) { 1386 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, 1387 SI_TRACKED_VGT_GS_ONCHIP_CNTL, 1388 S_028A44_ES_VERTS_PER_SUBGRP(250) | 1389 S_028A44_GS_PRIMS_PER_SUBGRP(126) | 1390 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126)); 1391 } 1392 1393 radeon_end_update_context_roll(sctx); 1394 1395 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */ 1396 if (sctx->chip_class >= GFX10) { 1397 radeon_begin_again(&sctx->gfx_cs); 1398 radeon_opt_set_uconfig_reg(sctx, R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC, 1399 shader->ctx_reg.vs.ge_pc_alloc); 1400 radeon_end(); 1401 } 1402} 1403 1404/** 1405 * Compute the state for \p shader, which will run as a vertex shader on the 1406 * hardware. 1407 * 1408 * If \p gs is non-NULL, it points to the geometry shader for which this shader 1409 * is the copy shader. 1410 */ 1411static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader, 1412 struct si_shader_selector *gs) 1413{ 1414 const struct si_shader_info *info = &shader->selector->info; 1415 struct si_pm4_state *pm4; 1416 unsigned num_user_sgprs, vgpr_comp_cnt; 1417 uint64_t va; 1418 unsigned nparams, oc_lds_en; 1419 bool window_space = info->stage == MESA_SHADER_VERTEX ? 1420 info->base.vs.window_space_position : 0; 1421 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid; 1422 1423 pm4 = si_get_shader_pm4_state(shader); 1424 if (!pm4) 1425 return; 1426 1427 pm4->atom.emit = si_emit_shader_vs; 1428 1429 /* We always write VGT_GS_MODE in the VS state, because every switch 1430 * between different shader pipelines involving a different GS or no 1431 * GS at all involves a switch of the VS (different GS use different 1432 * copy shaders). On the other hand, when the API switches from a GS to 1433 * no GS and then back to the same GS used originally, the GS state is 1434 * not sent again. 1435 */ 1436 if (!gs) { 1437 unsigned mode = V_028A40_GS_OFF; 1438 1439 /* PrimID needs GS scenario A. */ 1440 if (enable_prim_id) 1441 mode = V_028A40_GS_SCENARIO_A; 1442 1443 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode); 1444 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id; 1445 } else { 1446 shader->ctx_reg.vs.vgt_gs_mode = 1447 ac_vgt_gs_mode(gs->info.base.gs.vertices_out, sscreen->info.chip_class); 1448 shader->ctx_reg.vs.vgt_primitiveid_en = 0; 1449 } 1450 1451 if (sscreen->info.chip_class <= GFX8) { 1452 /* Reuse needs to be set off if we write oViewport. */ 1453 shader->ctx_reg.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(info->writes_viewport_index); 1454 } 1455 1456 va = shader->bo->gpu_address; 1457 1458 if (gs) { 1459 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */ 1460 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR; 1461 } else if (shader->selector->info.stage == MESA_SHADER_VERTEX) { 1462 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id); 1463 1464 if (info->base.vs.blit_sgprs_amd) { 1465 num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->base.vs.blit_sgprs_amd; 1466 } else { 1467 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR); 1468 } 1469 } else if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL) { 1470 vgpr_comp_cnt = enable_prim_id ? 3 : 2; 1471 num_user_sgprs = SI_TES_NUM_USER_SGPR; 1472 } else 1473 unreachable("invalid shader selector type"); 1474 1475 /* VS is required to export at least one param. */ 1476 nparams = MAX2(shader->info.nr_param_exports, 1); 1477 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1); 1478 1479 if (sscreen->info.chip_class >= GFX10) { 1480 shader->ctx_reg.vs.spi_vs_out_config |= 1481 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0); 1482 } 1483 1484 shader->ctx_reg.vs.spi_shader_pos_format = 1485 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | 1486 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP 1487 : V_02870C_SPI_SHADER_NONE) | 1488 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP 1489 : V_02870C_SPI_SHADER_NONE) | 1490 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP 1491 : V_02870C_SPI_SHADER_NONE); 1492 unsigned late_alloc_wave64, cu_mask; 1493 ac_compute_late_alloc(&sscreen->info, false, false, 1494 shader->config.scratch_bytes_per_wave > 0, 1495 &late_alloc_wave64, &cu_mask); 1496 1497 shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(late_alloc_wave64 > 0) | 1498 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1); 1499 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, shader, false); 1500 1501 oc_lds_en = shader->selector->info.stage == MESA_SHADER_TESS_EVAL ? 1 : 0; 1502 1503 if (sscreen->info.chip_class >= GFX7) { 1504 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, 1505 S_00B118_CU_EN(cu_mask) | S_00B118_WAVE_LIMIT(0x3F)); 1506 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(late_alloc_wave64)); 1507 } 1508 1509 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8); 1510 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, 1511 S_00B124_MEM_BASE(sscreen->info.address32_hi >> 8)); 1512 1513 uint32_t rsrc1 = 1514 S_00B128_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) | 1515 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B128_DX10_CLAMP(1) | 1516 S_00B128_MEM_ORDERED(si_shader_mem_ordered(shader)) | 1517 S_00B128_FLOAT_MODE(shader->config.float_mode); 1518 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) | S_00B12C_OC_LDS_EN(oc_lds_en) | 1519 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0); 1520 1521 if (sscreen->info.chip_class >= GFX10) 1522 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5); 1523 else if (sscreen->info.chip_class == GFX9) 1524 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5); 1525 1526 if (sscreen->info.chip_class <= GFX9) 1527 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8); 1528 1529 if (!sscreen->use_ngg_streamout) { 1530 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) | 1531 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) | 1532 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) | 1533 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) | 1534 S_00B12C_SO_EN(!!shader->selector->so.num_outputs); 1535 } 1536 1537 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1); 1538 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2); 1539 1540 if (window_space) 1541 shader->ctx_reg.vs.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1); 1542 else 1543 shader->ctx_reg.vs.pa_cl_vte_cntl = 1544 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) | 1545 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) | 1546 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1); 1547 1548 if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL) 1549 si_set_tesseval_regs(sscreen, shader->selector, shader); 1550 1551 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader); 1552} 1553 1554static unsigned si_get_ps_num_interp(struct si_shader *ps) 1555{ 1556 struct si_shader_info *info = &ps->selector->info; 1557 unsigned num_colors = !!(info->colors_read & 0x0f) + !!(info->colors_read & 0xf0); 1558 unsigned num_interp = 1559 ps->selector->info.num_inputs + (ps->key.part.ps.prolog.color_two_side ? num_colors : 0); 1560 1561 assert(num_interp <= 32); 1562 return MIN2(num_interp, 32); 1563} 1564 1565static unsigned si_get_spi_shader_col_format(struct si_shader *shader) 1566{ 1567 unsigned spi_shader_col_format = shader->key.part.ps.epilog.spi_shader_col_format; 1568 unsigned value = 0, num_mrts = 0; 1569 unsigned i, num_targets = (util_last_bit(spi_shader_col_format) + 3) / 4; 1570 1571 /* Remove holes in spi_shader_col_format. */ 1572 for (i = 0; i < num_targets; i++) { 1573 unsigned spi_format = (spi_shader_col_format >> (i * 4)) & 0xf; 1574 1575 if (spi_format) { 1576 value |= spi_format << (num_mrts * 4); 1577 num_mrts++; 1578 } 1579 } 1580 1581 return value; 1582} 1583 1584static void si_emit_shader_ps(struct si_context *sctx) 1585{ 1586 struct si_shader *shader = sctx->queued.named.ps; 1587 if (!shader) 1588 return; 1589 1590 radeon_begin(&sctx->gfx_cs); 1591 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/ 1592 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA, 1593 shader->ctx_reg.ps.spi_ps_input_ena, 1594 shader->ctx_reg.ps.spi_ps_input_addr); 1595 1596 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL, 1597 shader->ctx_reg.ps.spi_baryc_cntl); 1598 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL, 1599 shader->ctx_reg.ps.spi_ps_in_control); 1600 1601 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */ 1602 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT, 1603 shader->ctx_reg.ps.spi_shader_z_format, 1604 shader->ctx_reg.ps.spi_shader_col_format); 1605 1606 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK, 1607 shader->ctx_reg.ps.cb_shader_mask); 1608 radeon_end_update_context_roll(sctx); 1609} 1610 1611static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader) 1612{ 1613 struct si_shader_info *info = &shader->selector->info; 1614 struct si_pm4_state *pm4; 1615 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask; 1616 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); 1617 uint64_t va; 1618 unsigned input_ena = shader->config.spi_ps_input_ena; 1619 1620 /* we need to enable at least one of them, otherwise we hang the GPU */ 1621 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) || G_0286CC_PERSP_CENTER_ENA(input_ena) || 1622 G_0286CC_PERSP_CENTROID_ENA(input_ena) || G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) || 1623 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) || G_0286CC_LINEAR_CENTER_ENA(input_ena) || 1624 G_0286CC_LINEAR_CENTROID_ENA(input_ena) || G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena)); 1625 /* POS_W_FLOAT_ENA requires one of the perspective weights. */ 1626 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) || G_0286CC_PERSP_SAMPLE_ENA(input_ena) || 1627 G_0286CC_PERSP_CENTER_ENA(input_ena) || G_0286CC_PERSP_CENTROID_ENA(input_ena) || 1628 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena)); 1629 1630 /* Validate interpolation optimization flags (read as implications). */ 1631 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp || 1632 (G_0286CC_PERSP_CENTER_ENA(input_ena) && G_0286CC_PERSP_CENTROID_ENA(input_ena))); 1633 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear || 1634 (G_0286CC_LINEAR_CENTER_ENA(input_ena) && G_0286CC_LINEAR_CENTROID_ENA(input_ena))); 1635 assert(!shader->key.part.ps.prolog.force_persp_center_interp || 1636 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena))); 1637 assert(!shader->key.part.ps.prolog.force_linear_center_interp || 1638 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena))); 1639 assert(!shader->key.part.ps.prolog.force_persp_sample_interp || 1640 (!G_0286CC_PERSP_CENTER_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena))); 1641 assert(!shader->key.part.ps.prolog.force_linear_sample_interp || 1642 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena))); 1643 1644 /* Validate cases when the optimizations are off (read as implications). */ 1645 assert(shader->key.part.ps.prolog.bc_optimize_for_persp || 1646 !G_0286CC_PERSP_CENTER_ENA(input_ena) || !G_0286CC_PERSP_CENTROID_ENA(input_ena)); 1647 assert(shader->key.part.ps.prolog.bc_optimize_for_linear || 1648 !G_0286CC_LINEAR_CENTER_ENA(input_ena) || !G_0286CC_LINEAR_CENTROID_ENA(input_ena)); 1649 1650 pm4 = si_get_shader_pm4_state(shader); 1651 if (!pm4) 1652 return; 1653 1654 /* If multiple state sets are allowed to be in a bin, break the batch on a new PS. */ 1655 if (sscreen->dpbb_allowed && 1656 (sscreen->pbb_context_states_per_bin > 1 || 1657 sscreen->pbb_persistent_states_per_bin > 1)) { 1658 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); 1659 si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); 1660 } 1661 1662 pm4->atom.emit = si_emit_shader_ps; 1663 1664 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION 1665 * Possible vaules: 1666 * 0 -> Position = pixel center 1667 * 1 -> Position = pixel centroid 1668 * 2 -> Position = at sample position 1669 * 1670 * From GLSL 4.5 specification, section 7.1: 1671 * "The variable gl_FragCoord is available as an input variable from 1672 * within fragment shaders and it holds the window relative coordinates 1673 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this 1674 * value can be for any location within the pixel, or one of the 1675 * fragment samples. The use of centroid does not further restrict 1676 * this value to be inside the current primitive." 1677 * 1678 * Meaning that centroid has no effect and we can return anything within 1679 * the pixel. Thus, return the value at sample position, because that's 1680 * the most accurate one shaders can get. 1681 */ 1682 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); 1683 1684 if (info->base.fs.pixel_center_integer) 1685 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1); 1686 1687 spi_shader_col_format = si_get_spi_shader_col_format(shader); 1688 cb_shader_mask = ac_get_cb_shader_mask(shader->key.part.ps.epilog.spi_shader_col_format); 1689 1690 /* Ensure that some export memory is always allocated, for two reasons: 1691 * 1692 * 1) Correctness: The hardware ignores the EXEC mask if no export 1693 * memory is allocated, so KILL and alpha test do not work correctly 1694 * without this. 1695 * 2) Performance: Every shader needs at least a NULL export, even when 1696 * it writes no color/depth output. The NULL export instruction 1697 * stalls without this setting. 1698 * 1699 * Don't add this to CB_SHADER_MASK. 1700 * 1701 * GFX10 supports pixel shaders without exports by setting both 1702 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export 1703 * instructions if any are present. 1704 */ 1705 if ((sscreen->info.chip_class <= GFX9 || info->base.fs.uses_discard || 1706 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) && 1707 !spi_shader_col_format && !info->writes_z && !info->writes_stencil && 1708 !info->writes_samplemask) 1709 spi_shader_col_format = V_028714_SPI_SHADER_32_R; 1710 1711 shader->ctx_reg.ps.spi_ps_input_ena = input_ena; 1712 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr; 1713 1714 unsigned num_interp = si_get_ps_num_interp(shader); 1715 1716 /* Set interpolation controls. */ 1717 spi_ps_in_control = S_0286D8_NUM_INTERP(num_interp) | 1718 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32); 1719 1720 shader->ctx_reg.ps.num_interp = num_interp; 1721 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl; 1722 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control; 1723 shader->ctx_reg.ps.spi_shader_z_format = 1724 ac_get_spi_shader_z_format(info->writes_z, info->writes_stencil, info->writes_samplemask); 1725 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format; 1726 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask; 1727 1728 va = shader->bo->gpu_address; 1729 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8); 1730 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, 1731 S_00B024_MEM_BASE(sscreen->info.address32_hi >> 8)); 1732 1733 uint32_t rsrc1 = 1734 S_00B028_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ps_wave_size == 32 ? 8 : 4)) | 1735 S_00B028_DX10_CLAMP(1) | S_00B028_MEM_ORDERED(si_shader_mem_ordered(shader)) | 1736 S_00B028_FLOAT_MODE(shader->config.float_mode); 1737 1738 if (sscreen->info.chip_class < GFX10) { 1739 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8); 1740 } 1741 1742 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1); 1743 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 1744 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) | 1745 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) | 1746 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0)); 1747} 1748 1749static void si_shader_init_pm4_state(struct si_screen *sscreen, struct si_shader *shader) 1750{ 1751 switch (shader->selector->info.stage) { 1752 case MESA_SHADER_VERTEX: 1753 if (shader->key.as_ls) 1754 si_shader_ls(sscreen, shader); 1755 else if (shader->key.as_es) 1756 si_shader_es(sscreen, shader); 1757 else if (shader->key.as_ngg) 1758 gfx10_shader_ngg(sscreen, shader); 1759 else 1760 si_shader_vs(sscreen, shader, NULL); 1761 break; 1762 case MESA_SHADER_TESS_CTRL: 1763 si_shader_hs(sscreen, shader); 1764 break; 1765 case MESA_SHADER_TESS_EVAL: 1766 if (shader->key.as_es) 1767 si_shader_es(sscreen, shader); 1768 else if (shader->key.as_ngg) 1769 gfx10_shader_ngg(sscreen, shader); 1770 else 1771 si_shader_vs(sscreen, shader, NULL); 1772 break; 1773 case MESA_SHADER_GEOMETRY: 1774 if (shader->key.as_ngg) 1775 gfx10_shader_ngg(sscreen, shader); 1776 else 1777 si_shader_gs(sscreen, shader); 1778 break; 1779 case MESA_SHADER_FRAGMENT: 1780 si_shader_ps(sscreen, shader); 1781 break; 1782 default: 1783 assert(0); 1784 } 1785} 1786 1787static void si_clear_vs_key_inputs(struct si_context *sctx, struct si_shader_key *key, 1788 struct si_vs_prolog_bits *prolog_key) 1789{ 1790 prolog_key->instance_divisor_is_one = 0; 1791 prolog_key->instance_divisor_is_fetched = 0; 1792 key->mono.vs_fetch_opencode = 0; 1793 memset(key->mono.vs_fix_fetch, 0, sizeof(key->mono.vs_fix_fetch)); 1794} 1795 1796void si_vs_key_update_inputs(struct si_context *sctx) 1797{ 1798 struct si_shader_selector *vs = sctx->shader.vs.cso; 1799 struct si_vertex_elements *elts = sctx->vertex_elements; 1800 struct si_shader_key *key = &sctx->shader.vs.key; 1801 1802 if (!vs) 1803 return; 1804 1805 if (vs->info.base.vs.blit_sgprs_amd) { 1806 si_clear_vs_key_inputs(sctx, key, &key->part.vs.prolog); 1807 key->opt.prefer_mono = 0; 1808 sctx->uses_nontrivial_vs_prolog = false; 1809 return; 1810 } 1811 1812 bool uses_nontrivial_vs_prolog = false; 1813 1814 if (elts->instance_divisor_is_one || elts->instance_divisor_is_fetched) 1815 uses_nontrivial_vs_prolog = true; 1816 1817 key->part.vs.prolog.instance_divisor_is_one = elts->instance_divisor_is_one; 1818 key->part.vs.prolog.instance_divisor_is_fetched = elts->instance_divisor_is_fetched; 1819 key->opt.prefer_mono = elts->instance_divisor_is_fetched; 1820 1821 unsigned count_mask = (1 << vs->info.num_inputs) - 1; 1822 unsigned fix = elts->fix_fetch_always & count_mask; 1823 unsigned opencode = elts->fix_fetch_opencode & count_mask; 1824 1825 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) { 1826 uint32_t mask = elts->fix_fetch_unaligned & count_mask; 1827 while (mask) { 1828 unsigned i = u_bit_scan(&mask); 1829 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1); 1830 unsigned vbidx = elts->vertex_buffer_index[i]; 1831 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx]; 1832 unsigned align_mask = (1 << log_hw_load_size) - 1; 1833 if (vb->buffer_offset & align_mask || vb->stride & align_mask) { 1834 fix |= 1 << i; 1835 opencode |= 1 << i; 1836 } 1837 } 1838 } 1839 1840 memset(key->mono.vs_fix_fetch, 0, sizeof(key->mono.vs_fix_fetch)); 1841 1842 while (fix) { 1843 unsigned i = u_bit_scan(&fix); 1844 uint8_t fix_fetch = elts->fix_fetch[i]; 1845 1846 key->mono.vs_fix_fetch[i].bits = fix_fetch; 1847 if (fix_fetch) 1848 uses_nontrivial_vs_prolog = true; 1849 } 1850 key->mono.vs_fetch_opencode = opencode; 1851 if (opencode) 1852 uses_nontrivial_vs_prolog = true; 1853 1854 sctx->uses_nontrivial_vs_prolog = uses_nontrivial_vs_prolog; 1855 1856 /* draw_vertex_state (display lists) requires a trivial VS prolog that ignores 1857 * the current vertex buffers and vertex elements. 1858 * 1859 * We just computed the prolog key because we needed to set uses_nontrivial_vs_prolog, 1860 * so that we know whether the VS prolog should be updated when we switch from 1861 * draw_vertex_state to draw_vbo. Now clear the VS prolog for draw_vertex_state. 1862 * This should happen rarely because the VS prolog should be trivial in most 1863 * cases. 1864 */ 1865 if (uses_nontrivial_vs_prolog && sctx->force_trivial_vs_prolog) 1866 si_clear_vs_key_inputs(sctx, key, &key->part.vs.prolog); 1867} 1868 1869void si_get_vs_key_inputs(struct si_context *sctx, struct si_shader_key *key, 1870 struct si_vs_prolog_bits *prolog_key) 1871{ 1872 prolog_key->instance_divisor_is_one = sctx->shader.vs.key.part.vs.prolog.instance_divisor_is_one; 1873 prolog_key->instance_divisor_is_fetched = sctx->shader.vs.key.part.vs.prolog.instance_divisor_is_fetched; 1874 1875 key->mono.vs_fetch_opencode = sctx->shader.vs.key.mono.vs_fetch_opencode; 1876 memcpy(key->mono.vs_fix_fetch, sctx->shader.vs.key.mono.vs_fix_fetch, 1877 sizeof(key->mono.vs_fix_fetch)); 1878} 1879 1880void si_update_ps_inputs_read_or_disabled(struct si_context *sctx) 1881{ 1882 struct si_shader_selector *ps = sctx->shader.ps.cso; 1883 1884 /* Find out if PS is disabled. */ 1885 bool ps_disabled = true; 1886 if (ps) { 1887 bool ps_modifies_zs = ps->info.base.fs.uses_discard || ps->info.writes_z || ps->info.writes_stencil || 1888 ps->info.writes_samplemask || 1889 sctx->queued.named.blend->alpha_to_coverage || 1890 sctx->queued.named.dsa->alpha_func != PIPE_FUNC_ALWAYS; 1891 unsigned ps_colormask = si_get_total_colormask(sctx); 1892 1893 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard || 1894 (!ps_colormask && !ps_modifies_zs && !ps->info.base.writes_memory); 1895 } 1896 1897 sctx->ps_inputs_read_or_disabled = ps_disabled ? 0 : ps->inputs_read; 1898} 1899 1900static void si_get_vs_key_outputs(struct si_context *sctx, struct si_shader_selector *vs, 1901 struct si_shader_key *key) 1902{ 1903 1904 key->opt.kill_clip_distances = vs->clipdist_mask & ~sctx->queued.named.rasterizer->clip_plane_enable; 1905 1906 /* Find out which VS outputs aren't used by the PS. */ 1907 uint64_t outputs_written = vs->outputs_written_before_ps; 1908 uint64_t linked = outputs_written & sctx->ps_inputs_read_or_disabled; 1909 1910 key->opt.kill_outputs = ~linked & outputs_written; 1911 1912 if (vs->info.stage != MESA_SHADER_GEOMETRY) { 1913 key->opt.ngg_culling = sctx->ngg_culling; 1914 key->mono.u.vs_export_prim_id = sctx->shader.ps.cso && sctx->shader.ps.cso->info.uses_primid; 1915 } else { 1916 key->opt.ngg_culling = 0; 1917 key->mono.u.vs_export_prim_id = 0; 1918 } 1919 1920 key->opt.kill_pointsize = vs->info.writes_psize && 1921 sctx->current_rast_prim != PIPE_PRIM_POINTS && 1922 !sctx->queued.named.rasterizer->polygon_mode_is_points; 1923} 1924 1925static void si_clear_vs_key_outputs(struct si_context *sctx, struct si_shader_selector *vs, 1926 struct si_shader_key *key) 1927{ 1928 key->opt.kill_clip_distances = 0; 1929 key->opt.kill_outputs = 0; 1930 key->opt.ngg_culling = 0; 1931 key->mono.u.vs_export_prim_id = 0; 1932 key->opt.kill_pointsize = 0; 1933} 1934 1935void si_ps_key_update_framebuffer(struct si_context *sctx) 1936{ 1937 struct si_shader_selector *sel = sctx->shader.ps.cso; 1938 struct si_shader_key *key = &sctx->shader.ps.key; 1939 1940 if (!sel) 1941 return; 1942 1943 if (sel->info.color0_writes_all_cbufs && 1944 sel->info.colors_written == 0x1) 1945 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1; 1946 else 1947 key->part.ps.epilog.last_cbuf = 0; 1948 1949 /* ps_uses_fbfetch is true only if the color buffer is bound. */ 1950 if (sctx->ps_uses_fbfetch) { 1951 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0]; 1952 struct pipe_resource *tex = cb0->texture; 1953 1954 /* 1D textures are allocated and used as 2D on GFX9. */ 1955 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1; 1956 key->mono.u.ps.fbfetch_is_1D = 1957 sctx->chip_class != GFX9 && 1958 (tex->target == PIPE_TEXTURE_1D || tex->target == PIPE_TEXTURE_1D_ARRAY); 1959 key->mono.u.ps.fbfetch_layered = 1960 tex->target == PIPE_TEXTURE_1D_ARRAY || tex->target == PIPE_TEXTURE_2D_ARRAY || 1961 tex->target == PIPE_TEXTURE_CUBE || tex->target == PIPE_TEXTURE_CUBE_ARRAY || 1962 tex->target == PIPE_TEXTURE_3D; 1963 } else { 1964 key->mono.u.ps.fbfetch_msaa = 0; 1965 key->mono.u.ps.fbfetch_is_1D = 0; 1966 key->mono.u.ps.fbfetch_layered = 0; 1967 } 1968} 1969 1970void si_ps_key_update_framebuffer_blend(struct si_context *sctx) 1971{ 1972 struct si_shader_selector *sel = sctx->shader.ps.cso; 1973 struct si_shader_key *key = &sctx->shader.ps.key; 1974 struct si_state_blend *blend = sctx->queued.named.blend; 1975 1976 if (!sel) 1977 return; 1978 1979 /* Select the shader color format based on whether 1980 * blending or alpha are needed. 1981 */ 1982 key->part.ps.epilog.spi_shader_col_format = 1983 (blend->blend_enable_4bit & blend->need_src_alpha_4bit & 1984 sctx->framebuffer.spi_shader_col_format_blend_alpha) | 1985 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit & 1986 sctx->framebuffer.spi_shader_col_format_blend) | 1987 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit & 1988 sctx->framebuffer.spi_shader_col_format_alpha) | 1989 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit & 1990 sctx->framebuffer.spi_shader_col_format); 1991 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit; 1992 1993 /* The output for dual source blending should have 1994 * the same format as the first output. 1995 */ 1996 if (blend->dual_src_blend) { 1997 key->part.ps.epilog.spi_shader_col_format |= 1998 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4; 1999 } 2000 2001 /* If alpha-to-coverage is enabled, we have to export alpha 2002 * even if there is no color buffer. 2003 */ 2004 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) && blend->alpha_to_coverage) 2005 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR; 2006 2007 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs 2008 * to the range supported by the type if a channel has less 2009 * than 16 bits and the export format is 16_ABGR. 2010 */ 2011 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) { 2012 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8; 2013 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10; 2014 } 2015 2016 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */ 2017 if (!key->part.ps.epilog.last_cbuf) { 2018 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit; 2019 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written; 2020 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written; 2021 } 2022 2023 /* Eliminate shader code computing output values that are unused. 2024 * This enables dead code elimination between shader parts. 2025 * Check if any output is eliminated. 2026 */ 2027 if (sel->colors_written_4bit & 2028 ~(sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_enabled_4bit)) 2029 key->opt.prefer_mono = 1; 2030 else 2031 key->opt.prefer_mono = 0; 2032} 2033 2034void si_ps_key_update_blend_rasterizer(struct si_context *sctx) 2035{ 2036 struct si_shader_key *key = &sctx->shader.ps.key; 2037 struct si_state_blend *blend = sctx->queued.named.blend; 2038 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 2039 2040 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one && rs->multisample_enable; 2041} 2042 2043void si_ps_key_update_rasterizer(struct si_context *sctx) 2044{ 2045 struct si_shader_selector *sel = sctx->shader.ps.cso; 2046 struct si_shader_key *key = &sctx->shader.ps.key; 2047 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 2048 2049 if (!sel) 2050 return; 2051 2052 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read; 2053 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.uses_interp_color; 2054 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color; 2055} 2056 2057void si_ps_key_update_dsa(struct si_context *sctx) 2058{ 2059 struct si_shader_key *key = &sctx->shader.ps.key; 2060 2061 key->part.ps.epilog.alpha_func = sctx->queued.named.dsa->alpha_func; 2062} 2063 2064static void si_ps_key_update_primtype_shader_rasterizer_framebuffer(struct si_context *sctx) 2065{ 2066 struct si_shader_key *key = &sctx->shader.ps.key; 2067 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 2068 2069 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim); 2070 bool is_line = util_prim_is_lines(sctx->current_rast_prim); 2071 2072 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly; 2073 key->part.ps.epilog.poly_line_smoothing = 2074 ((is_poly && rs->poly_smooth) || (is_line && rs->line_smooth)) && 2075 sctx->framebuffer.nr_samples <= 1; 2076} 2077 2078void si_ps_key_update_sample_shading(struct si_context *sctx) 2079{ 2080 struct si_shader_selector *sel = sctx->shader.ps.cso; 2081 struct si_shader_key *key = &sctx->shader.ps.key; 2082 2083 if (!sel) 2084 return; 2085 2086 if (sctx->ps_iter_samples > 1 && sel->info.reads_samplemask) 2087 key->part.ps.prolog.samplemask_log_ps_iter = util_logbase2(sctx->ps_iter_samples); 2088 else 2089 key->part.ps.prolog.samplemask_log_ps_iter = 0; 2090} 2091 2092void si_ps_key_update_framebuffer_rasterizer_sample_shading(struct si_context *sctx) 2093{ 2094 struct si_shader_selector *sel = sctx->shader.ps.cso; 2095 struct si_shader_key *key = &sctx->shader.ps.key; 2096 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 2097 2098 if (!sel) 2099 return; 2100 2101 bool uses_persp_center = sel->info.uses_persp_center || 2102 (!rs->flatshade && sel->info.uses_persp_center_color); 2103 bool uses_persp_centroid = sel->info.uses_persp_centroid || 2104 (!rs->flatshade && sel->info.uses_persp_centroid_color); 2105 bool uses_persp_sample = sel->info.uses_persp_sample || 2106 (!rs->flatshade && sel->info.uses_persp_sample_color); 2107 2108 if (rs->force_persample_interp && rs->multisample_enable && 2109 sctx->framebuffer.nr_samples > 1 && sctx->ps_iter_samples > 1) { 2110 key->part.ps.prolog.force_persp_sample_interp = 2111 uses_persp_center || uses_persp_centroid; 2112 2113 key->part.ps.prolog.force_linear_sample_interp = 2114 sel->info.uses_linear_center || sel->info.uses_linear_centroid; 2115 2116 key->part.ps.prolog.force_persp_center_interp = 0; 2117 key->part.ps.prolog.force_linear_center_interp = 0; 2118 key->part.ps.prolog.bc_optimize_for_persp = 0; 2119 key->part.ps.prolog.bc_optimize_for_linear = 0; 2120 key->mono.u.ps.interpolate_at_sample_force_center = 0; 2121 } else if (rs->multisample_enable && sctx->framebuffer.nr_samples > 1) { 2122 key->part.ps.prolog.force_persp_sample_interp = 0; 2123 key->part.ps.prolog.force_linear_sample_interp = 0; 2124 key->part.ps.prolog.force_persp_center_interp = 0; 2125 key->part.ps.prolog.force_linear_center_interp = 0; 2126 key->part.ps.prolog.bc_optimize_for_persp = 2127 uses_persp_center && uses_persp_centroid; 2128 key->part.ps.prolog.bc_optimize_for_linear = 2129 sel->info.uses_linear_center && sel->info.uses_linear_centroid; 2130 key->mono.u.ps.interpolate_at_sample_force_center = 0; 2131 } else { 2132 key->part.ps.prolog.force_persp_sample_interp = 0; 2133 key->part.ps.prolog.force_linear_sample_interp = 0; 2134 2135 /* Make sure SPI doesn't compute more than 1 pair 2136 * of (i,j), which is the optimization here. */ 2137 key->part.ps.prolog.force_persp_center_interp = uses_persp_center + 2138 uses_persp_centroid + 2139 uses_persp_sample > 1; 2140 2141 key->part.ps.prolog.force_linear_center_interp = sel->info.uses_linear_center + 2142 sel->info.uses_linear_centroid + 2143 sel->info.uses_linear_sample > 1; 2144 key->part.ps.prolog.bc_optimize_for_persp = 0; 2145 key->part.ps.prolog.bc_optimize_for_linear = 0; 2146 key->mono.u.ps.interpolate_at_sample_force_center = sel->info.uses_interp_at_sample; 2147 } 2148} 2149 2150/* Compute the key for the hw shader variant */ 2151static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_shader_selector *sel, 2152 struct si_shader_key *key) 2153{ 2154 struct si_context *sctx = (struct si_context *)ctx; 2155 2156 switch (sel->info.stage) { 2157 case MESA_SHADER_VERTEX: 2158 if (!sctx->shader.tes.cso && !sctx->shader.gs.cso) 2159 si_get_vs_key_outputs(sctx, sel, key); 2160 else 2161 si_clear_vs_key_outputs(sctx, sel, key); 2162 break; 2163 case MESA_SHADER_TESS_CTRL: 2164 if (sctx->chip_class >= GFX9) { 2165 si_get_vs_key_inputs(sctx, key, &key->part.tcs.ls_prolog); 2166 key->part.tcs.ls = sctx->shader.vs.cso; 2167 } 2168 break; 2169 case MESA_SHADER_TESS_EVAL: 2170 if (!sctx->shader.gs.cso) 2171 si_get_vs_key_outputs(sctx, sel, key); 2172 else 2173 si_clear_vs_key_outputs(sctx, sel, key); 2174 break; 2175 case MESA_SHADER_GEOMETRY: 2176 if (sctx->chip_class >= GFX9) { 2177 if (sctx->shader.tes.cso) { 2178 si_clear_vs_key_inputs(sctx, key, &key->part.gs.vs_prolog); 2179 key->part.gs.es = sctx->shader.tes.cso; 2180 } else { 2181 si_get_vs_key_inputs(sctx, key, &key->part.gs.vs_prolog); 2182 key->part.gs.es = sctx->shader.vs.cso; 2183 } 2184 2185 /* Only NGG can eliminate GS outputs, because the code is shared with VS. */ 2186 if (sctx->ngg) 2187 si_get_vs_key_outputs(sctx, sel, key); 2188 else 2189 si_clear_vs_key_outputs(sctx, sel, key); 2190 } 2191 break; 2192 case MESA_SHADER_FRAGMENT: 2193 si_ps_key_update_primtype_shader_rasterizer_framebuffer(sctx); 2194 break; 2195 default: 2196 assert(0); 2197 } 2198} 2199 2200static void si_build_shader_variant(struct si_shader *shader, int thread_index, bool low_priority) 2201{ 2202 struct si_shader_selector *sel = shader->selector; 2203 struct si_screen *sscreen = sel->screen; 2204 struct ac_llvm_compiler *compiler; 2205 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug; 2206 2207 if (thread_index >= 0) { 2208 if (low_priority) { 2209 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp)); 2210 compiler = &sscreen->compiler_lowp[thread_index]; 2211 } else { 2212 assert(thread_index < ARRAY_SIZE(sscreen->compiler)); 2213 compiler = &sscreen->compiler[thread_index]; 2214 } 2215 if (!debug->async) 2216 debug = NULL; 2217 } else { 2218 assert(!low_priority); 2219 compiler = shader->compiler_ctx_state.compiler; 2220 } 2221 2222 if (!compiler->passes) 2223 si_init_compiler(sscreen, compiler); 2224 2225 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) { 2226 PRINT_ERR("Failed to build shader variant (type=%u)\n", sel->info.stage); 2227 shader->compilation_failed = true; 2228 return; 2229 } 2230 2231 if (shader->compiler_ctx_state.is_debug_context) { 2232 FILE *f = open_memstream(&shader->shader_log, &shader->shader_log_size); 2233 if (f) { 2234 si_shader_dump(sscreen, shader, NULL, f, false); 2235 fclose(f); 2236 } 2237 } 2238 2239 si_shader_init_pm4_state(sscreen, shader); 2240} 2241 2242static void si_build_shader_variant_low_priority(void *job, void *gdata, int thread_index) 2243{ 2244 struct si_shader *shader = (struct si_shader *)job; 2245 2246 assert(thread_index >= 0); 2247 2248 si_build_shader_variant(shader, thread_index, true); 2249} 2250 2251static const struct si_shader_key zeroed; 2252 2253static bool si_check_missing_main_part(struct si_screen *sscreen, struct si_shader_selector *sel, 2254 struct si_compiler_ctx_state *compiler_state, 2255 const struct si_shader_key *key) 2256{ 2257 struct si_shader **mainp = si_get_main_shader_part(sel, key); 2258 2259 if (!*mainp) { 2260 struct si_shader *main_part = CALLOC_STRUCT(si_shader); 2261 2262 if (!main_part) 2263 return false; 2264 2265 /* We can leave the fence as permanently signaled because the 2266 * main part becomes visible globally only after it has been 2267 * compiled. */ 2268 util_queue_fence_init(&main_part->ready); 2269 2270 main_part->selector = sel; 2271 main_part->key.as_es = key->as_es; 2272 main_part->key.as_ls = key->as_ls; 2273 main_part->key.as_ngg = key->as_ngg; 2274 main_part->is_monolithic = false; 2275 2276 if (!si_compile_shader(sscreen, compiler_state->compiler, main_part, 2277 &compiler_state->debug)) { 2278 FREE(main_part); 2279 return false; 2280 } 2281 *mainp = main_part; 2282 } 2283 return true; 2284} 2285 2286/* A helper to copy *key to *local_key and return local_key. */ 2287static const struct si_shader_key * 2288use_local_key_copy(const struct si_shader_key *key, struct si_shader_key *local_key) 2289{ 2290 if (key != local_key) 2291 memcpy(local_key, key, sizeof(*key)); 2292 2293 return local_key; 2294} 2295 2296/** 2297 * Select a shader variant according to the shader key. 2298 * 2299 * \param optimized_or_none If the key describes an optimized shader variant and 2300 * the compilation isn't finished, don't select any 2301 * shader and return an error. 2302 */ 2303int si_shader_select_with_key(struct si_context *sctx, struct si_shader_ctx_state *state, 2304 const struct si_shader_key *key, int thread_index, 2305 bool optimized_or_none) 2306{ 2307 struct si_screen *sscreen = sctx->screen; 2308 struct si_shader_selector *sel = state->cso; 2309 struct si_shader_selector *previous_stage_sel = NULL; 2310 struct si_shader *current = state->current; 2311 struct si_shader *iter, *shader = NULL; 2312 /* si_shader_select_with_key must not modify 'key' because it would affect future shaders. 2313 * If we need to modify it for this specific shader (eg: to disable optimizations), we 2314 * use a copy. 2315 */ 2316 struct si_shader_key local_key; 2317 2318 if (unlikely(sscreen->debug_flags & DBG(NO_OPT_VARIANT))) { 2319 /* Disable shader variant optimizations. */ 2320 key = use_local_key_copy(key, &local_key); 2321 memset(&local_key.opt, 0, sizeof(key->opt)); 2322 } 2323 2324again: 2325 /* Check if we don't need to change anything. 2326 * This path is also used for most shaders that don't need multiple 2327 * variants, it will cost just a computation of the key and this 2328 * test. */ 2329 if (likely(current && memcmp(¤t->key, key, sizeof(*key)) == 0)) { 2330 if (unlikely(!util_queue_fence_is_signalled(¤t->ready))) { 2331 if (current->is_optimized) { 2332 if (optimized_or_none) 2333 return -1; 2334 2335 key = use_local_key_copy(key, &local_key); 2336 memset(&local_key.opt, 0, sizeof(key->opt)); 2337 goto current_not_ready; 2338 } 2339 2340 util_queue_fence_wait(¤t->ready); 2341 } 2342 2343 return current->compilation_failed ? -1 : 0; 2344 } 2345current_not_ready: 2346 2347 /* This must be done before the mutex is locked, because async GS 2348 * compilation calls this function too, and therefore must enter 2349 * the mutex first. 2350 * 2351 * Only wait if we are in a draw call. Don't wait if we are 2352 * in a compiler thread. 2353 */ 2354 if (thread_index < 0) 2355 util_queue_fence_wait(&sel->ready); 2356 2357 simple_mtx_lock(&sel->mutex); 2358 2359 /* Compute the size of the key without the uniform values. */ 2360 size_t s = (void*)&key->opt.inlined_uniform_values - (void*)key; 2361 int variant_count = 0; 2362 const int max_inline_uniforms_variants = 5; 2363 2364 /* Find the shader variant. */ 2365 for (iter = sel->first_variant; iter; iter = iter->next_variant) { 2366 if (memcmp(&iter->key, key, s) == 0) { 2367 /* Check the inlined uniform values separatly, and count 2368 * the number of variants based on them. 2369 */ 2370 if (key->opt.inline_uniforms && 2371 memcmp(iter->key.opt.inlined_uniform_values, 2372 key->opt.inlined_uniform_values, 2373 MAX_INLINABLE_UNIFORMS * 4) != 0) { 2374 if (variant_count++ > max_inline_uniforms_variants) { 2375 key = use_local_key_copy(key, &local_key); 2376 /* Too many variants. Disable inlining for this shader. */ 2377 local_key.opt.inline_uniforms = 0; 2378 memset(local_key.opt.inlined_uniform_values, 0, MAX_INLINABLE_UNIFORMS * 4); 2379 simple_mtx_unlock(&sel->mutex); 2380 goto again; 2381 } 2382 continue; 2383 } 2384 2385 simple_mtx_unlock(&sel->mutex); 2386 2387 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) { 2388 /* If it's an optimized shader and its compilation has 2389 * been started but isn't done, use the unoptimized 2390 * shader so as not to cause a stall due to compilation. 2391 */ 2392 if (iter->is_optimized) { 2393 if (optimized_or_none) 2394 return -1; 2395 2396 key = use_local_key_copy(key, &local_key); 2397 memset(&local_key.opt, 0, sizeof(key->opt)); 2398 goto again; 2399 } 2400 2401 util_queue_fence_wait(&iter->ready); 2402 } 2403 2404 if (iter->compilation_failed) { 2405 return -1; /* skip the draw call */ 2406 } 2407 2408 state->current = iter; 2409 return 0; 2410 } 2411 } 2412 2413 /* Build a new shader. */ 2414 shader = CALLOC_STRUCT(si_shader); 2415 if (!shader) { 2416 simple_mtx_unlock(&sel->mutex); 2417 return -ENOMEM; 2418 } 2419 2420 util_queue_fence_init(&shader->ready); 2421 2422 if (!sctx->compiler.passes) 2423 si_init_compiler(sctx->screen, &sctx->compiler); 2424 2425 shader->selector = sel; 2426 shader->key = *key; 2427 shader->compiler_ctx_state.compiler = &sctx->compiler; 2428 shader->compiler_ctx_state.debug = sctx->debug; 2429 shader->compiler_ctx_state.is_debug_context = sctx->is_debug; 2430 2431 /* If this is a merged shader, get the first shader's selector. */ 2432 if (sscreen->info.chip_class >= GFX9) { 2433 if (sel->info.stage == MESA_SHADER_TESS_CTRL) 2434 previous_stage_sel = key->part.tcs.ls; 2435 else if (sel->info.stage == MESA_SHADER_GEOMETRY) 2436 previous_stage_sel = key->part.gs.es; 2437 2438 /* We need to wait for the previous shader. */ 2439 if (previous_stage_sel && thread_index < 0) 2440 util_queue_fence_wait(&previous_stage_sel->ready); 2441 } 2442 2443 bool is_pure_monolithic = 2444 sscreen->use_monolithic_shaders || memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0; 2445 2446 /* Compile the main shader part if it doesn't exist. This can happen 2447 * if the initial guess was wrong. 2448 */ 2449 if (!is_pure_monolithic) { 2450 bool ok = true; 2451 2452 /* Make sure the main shader part is present. This is needed 2453 * for shaders that can be compiled as VS, LS, or ES, and only 2454 * one of them is compiled at creation. 2455 * 2456 * It is also needed for GS, which can be compiled as non-NGG 2457 * and NGG. 2458 * 2459 * For merged shaders, check that the starting shader's main 2460 * part is present. 2461 */ 2462 if (previous_stage_sel) { 2463 struct si_shader_key shader1_key = zeroed; 2464 2465 if (sel->info.stage == MESA_SHADER_TESS_CTRL) { 2466 shader1_key.as_ls = 1; 2467 } else if (sel->info.stage == MESA_SHADER_GEOMETRY) { 2468 shader1_key.as_es = 1; 2469 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */ 2470 } else { 2471 assert(0); 2472 } 2473 2474 simple_mtx_lock(&previous_stage_sel->mutex); 2475 ok = si_check_missing_main_part(sscreen, previous_stage_sel, &shader->compiler_ctx_state, 2476 &shader1_key); 2477 simple_mtx_unlock(&previous_stage_sel->mutex); 2478 } 2479 2480 if (ok) { 2481 ok = si_check_missing_main_part(sscreen, sel, &shader->compiler_ctx_state, key); 2482 } 2483 2484 if (!ok) { 2485 FREE(shader); 2486 simple_mtx_unlock(&sel->mutex); 2487 return -ENOMEM; /* skip the draw call */ 2488 } 2489 } 2490 2491 /* Keep the reference to the 1st shader of merged shaders, so that 2492 * Gallium can't destroy it before we destroy the 2nd shader. 2493 * 2494 * Set sctx = NULL, because it's unused if we're not releasing 2495 * the shader, and we don't have any sctx here. 2496 */ 2497 si_shader_selector_reference(NULL, &shader->previous_stage_sel, previous_stage_sel); 2498 2499 /* Monolithic-only shaders don't make a distinction between optimized 2500 * and unoptimized. */ 2501 shader->is_monolithic = 2502 is_pure_monolithic || memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0; 2503 2504 shader->is_optimized = !is_pure_monolithic && 2505 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0; 2506 2507 /* If it's an optimized shader, compile it asynchronously. */ 2508 if (shader->is_optimized && thread_index < 0) { 2509 /* Compile it asynchronously. */ 2510 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority, shader, &shader->ready, 2511 si_build_shader_variant_low_priority, NULL, 0); 2512 2513 /* Add only after the ready fence was reset, to guard against a 2514 * race with si_bind_XX_shader. */ 2515 if (!sel->last_variant) { 2516 sel->first_variant = shader; 2517 sel->last_variant = shader; 2518 } else { 2519 sel->last_variant->next_variant = shader; 2520 sel->last_variant = shader; 2521 } 2522 2523 /* Use the default (unoptimized) shader for now. */ 2524 key = use_local_key_copy(key, &local_key); 2525 memset(&local_key.opt, 0, sizeof(key->opt)); 2526 simple_mtx_unlock(&sel->mutex); 2527 2528 if (sscreen->options.sync_compile) 2529 util_queue_fence_wait(&shader->ready); 2530 2531 if (optimized_or_none) 2532 return -1; 2533 goto again; 2534 } 2535 2536 /* Reset the fence before adding to the variant list. */ 2537 util_queue_fence_reset(&shader->ready); 2538 2539 if (!sel->last_variant) { 2540 sel->first_variant = shader; 2541 sel->last_variant = shader; 2542 } else { 2543 sel->last_variant->next_variant = shader; 2544 sel->last_variant = shader; 2545 } 2546 2547 simple_mtx_unlock(&sel->mutex); 2548 2549 assert(!shader->is_optimized); 2550 si_build_shader_variant(shader, thread_index, false); 2551 2552 util_queue_fence_signal(&shader->ready); 2553 2554 if (!shader->compilation_failed) 2555 state->current = shader; 2556 2557 return shader->compilation_failed ? -1 : 0; 2558} 2559 2560int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state) 2561{ 2562 struct si_context *sctx = (struct si_context *)ctx; 2563 2564 si_shader_selector_key(ctx, state->cso, &state->key); 2565 return si_shader_select_with_key(sctx, state, &state->key, -1, false); 2566} 2567 2568static void si_parse_next_shader_property(const struct si_shader_info *info, bool streamout, 2569 struct si_shader_key *key) 2570{ 2571 gl_shader_stage next_shader = info->base.next_stage; 2572 2573 switch (info->stage) { 2574 case MESA_SHADER_VERTEX: 2575 switch (next_shader) { 2576 case MESA_SHADER_GEOMETRY: 2577 key->as_es = 1; 2578 break; 2579 case MESA_SHADER_TESS_CTRL: 2580 case MESA_SHADER_TESS_EVAL: 2581 key->as_ls = 1; 2582 break; 2583 default: 2584 /* If POSITION isn't written, it can only be a HW VS 2585 * if streamout is used. If streamout isn't used, 2586 * assume that it's a HW LS. (the next shader is TCS) 2587 * This heuristic is needed for separate shader objects. 2588 */ 2589 if (!info->writes_position && !streamout) 2590 key->as_ls = 1; 2591 } 2592 break; 2593 2594 case MESA_SHADER_TESS_EVAL: 2595 if (next_shader == MESA_SHADER_GEOMETRY || !info->writes_position) 2596 key->as_es = 1; 2597 break; 2598 2599 default:; 2600 } 2601} 2602 2603/** 2604 * Compile the main shader part or the monolithic shader as part of 2605 * si_shader_selector initialization. Since it can be done asynchronously, 2606 * there is no way to report compile failures to applications. 2607 */ 2608static void si_init_shader_selector_async(void *job, void *gdata, int thread_index) 2609{ 2610 struct si_shader_selector *sel = (struct si_shader_selector *)job; 2611 struct si_screen *sscreen = sel->screen; 2612 struct ac_llvm_compiler *compiler; 2613 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug; 2614 2615 assert(!debug->debug_message || debug->async); 2616 assert(thread_index >= 0); 2617 assert(thread_index < ARRAY_SIZE(sscreen->compiler)); 2618 compiler = &sscreen->compiler[thread_index]; 2619 2620 if (!compiler->passes) 2621 si_init_compiler(sscreen, compiler); 2622 2623 /* The GS copy shader is always pre-compiled. */ 2624 if (sel->info.stage == MESA_SHADER_GEOMETRY && 2625 (!sscreen->use_ngg || !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */ 2626 sel->tess_turns_off_ngg)) { 2627 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug); 2628 if (!sel->gs_copy_shader) { 2629 fprintf(stderr, "radeonsi: can't create GS copy shader\n"); 2630 return; 2631 } 2632 2633 si_shader_vs(sscreen, sel->gs_copy_shader, sel); 2634 } 2635 2636 /* Serialize NIR to save memory. Monolithic shader variants 2637 * have to deserialize NIR before compilation. 2638 */ 2639 if (sel->nir) { 2640 struct blob blob; 2641 size_t size; 2642 2643 blob_init(&blob); 2644 /* true = remove optional debugging data to increase 2645 * the likehood of getting more shader cache hits. 2646 * It also drops variable names, so we'll save more memory. 2647 */ 2648 nir_serialize(&blob, sel->nir, true); 2649 blob_finish_get_buffer(&blob, &sel->nir_binary, &size); 2650 sel->nir_size = size; 2651 } 2652 2653 /* Compile the main shader part for use with a prolog and/or epilog. 2654 * If this fails, the driver will try to compile a monolithic shader 2655 * on demand. 2656 */ 2657 if (!sscreen->use_monolithic_shaders) { 2658 struct si_shader *shader = CALLOC_STRUCT(si_shader); 2659 unsigned char ir_sha1_cache_key[20]; 2660 2661 if (!shader) { 2662 fprintf(stderr, "radeonsi: can't allocate a main shader part\n"); 2663 return; 2664 } 2665 2666 /* We can leave the fence signaled because use of the default 2667 * main part is guarded by the selector's ready fence. */ 2668 util_queue_fence_init(&shader->ready); 2669 2670 shader->selector = sel; 2671 shader->is_monolithic = false; 2672 si_parse_next_shader_property(&sel->info, sel->so.num_outputs != 0, &shader->key); 2673 2674 if (sscreen->use_ngg && (!sel->so.num_outputs || sscreen->use_ngg_streamout) && 2675 ((sel->info.stage == MESA_SHADER_VERTEX && !shader->key.as_ls) || 2676 sel->info.stage == MESA_SHADER_TESS_EVAL || sel->info.stage == MESA_SHADER_GEOMETRY)) 2677 shader->key.as_ngg = 1; 2678 2679 if (sel->nir) { 2680 si_get_ir_cache_key(sel, shader->key.as_ngg, shader->key.as_es, ir_sha1_cache_key); 2681 } 2682 2683 /* Try to load the shader from the shader cache. */ 2684 simple_mtx_lock(&sscreen->shader_cache_mutex); 2685 2686 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) { 2687 simple_mtx_unlock(&sscreen->shader_cache_mutex); 2688 si_shader_dump_stats_for_shader_db(sscreen, shader, debug); 2689 } else { 2690 simple_mtx_unlock(&sscreen->shader_cache_mutex); 2691 2692 /* Compile the shader if it hasn't been loaded from the cache. */ 2693 if (!si_compile_shader(sscreen, compiler, shader, debug)) { 2694 FREE(shader); 2695 fprintf(stderr, "radeonsi: can't compile a main shader part\n"); 2696 return; 2697 } 2698 2699 simple_mtx_lock(&sscreen->shader_cache_mutex); 2700 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true); 2701 simple_mtx_unlock(&sscreen->shader_cache_mutex); 2702 } 2703 2704 *si_get_main_shader_part(sel, &shader->key) = shader; 2705 2706 /* Unset "outputs_written" flags for outputs converted to 2707 * DEFAULT_VAL, so that later inter-shader optimizations don't 2708 * try to eliminate outputs that don't exist in the final 2709 * shader. 2710 * 2711 * This is only done if non-monolithic shaders are enabled. 2712 */ 2713 if ((sel->info.stage == MESA_SHADER_VERTEX || 2714 sel->info.stage == MESA_SHADER_TESS_EVAL || 2715 sel->info.stage == MESA_SHADER_GEOMETRY) && 2716 !shader->key.as_ls && !shader->key.as_es) { 2717 unsigned i; 2718 2719 for (i = 0; i < sel->info.num_outputs; i++) { 2720 unsigned semantic = sel->info.output_semantic[i]; 2721 unsigned ps_input_cntl = shader->info.vs_output_ps_input_cntl[semantic]; 2722 2723 /* OFFSET=0x20 means DEFAULT_VAL, which means VS doesn't export it. */ 2724 if (G_028644_OFFSET(ps_input_cntl) != 0x20) 2725 continue; 2726 2727 unsigned id; 2728 2729 /* Remove the output from the mask. */ 2730 if ((semantic <= VARYING_SLOT_VAR31 || semantic >= VARYING_SLOT_VAR0_16BIT) && 2731 semantic != VARYING_SLOT_POS && 2732 semantic != VARYING_SLOT_PSIZ && 2733 semantic != VARYING_SLOT_CLIP_VERTEX && 2734 semantic != VARYING_SLOT_EDGE) { 2735 id = si_shader_io_get_unique_index(semantic, true); 2736 sel->outputs_written_before_ps &= ~(1ull << id); 2737 } 2738 } 2739 } 2740 } 2741 2742 /* Free NIR. We only keep serialized NIR after this point. */ 2743 if (sel->nir) { 2744 ralloc_free(sel->nir); 2745 sel->nir = NULL; 2746 } 2747} 2748 2749void si_schedule_initial_compile(struct si_context *sctx, gl_shader_stage stage, 2750 struct util_queue_fence *ready_fence, 2751 struct si_compiler_ctx_state *compiler_ctx_state, void *job, 2752 util_queue_execute_func execute) 2753{ 2754 util_queue_fence_init(ready_fence); 2755 2756 struct util_async_debug_callback async_debug; 2757 bool debug = (sctx->debug.debug_message && !sctx->debug.async) || sctx->is_debug || 2758 si_can_dump_shader(sctx->screen, stage); 2759 2760 if (debug) { 2761 u_async_debug_init(&async_debug); 2762 compiler_ctx_state->debug = async_debug.base; 2763 } 2764 2765 util_queue_add_job(&sctx->screen->shader_compiler_queue, job, ready_fence, execute, NULL, 0); 2766 2767 if (debug) { 2768 util_queue_fence_wait(ready_fence); 2769 u_async_debug_drain(&async_debug, &sctx->debug); 2770 u_async_debug_cleanup(&async_debug); 2771 } 2772 2773 if (sctx->screen->options.sync_compile) 2774 util_queue_fence_wait(ready_fence); 2775} 2776 2777/* Return descriptor slot usage masks from the given shader info. */ 2778void si_get_active_slot_masks(const struct si_shader_info *info, uint64_t *const_and_shader_buffers, 2779 uint64_t *samplers_and_images) 2780{ 2781 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers; 2782 2783 num_shaderbufs = info->base.num_ssbos; 2784 num_constbufs = info->base.num_ubos; 2785 /* two 8-byte images share one 16-byte slot */ 2786 num_images = align(info->base.num_images, 2); 2787 num_msaa_images = align(util_last_bit(info->base.msaa_images), 2); 2788 num_samplers = BITSET_LAST_BIT(info->base.textures_used); 2789 2790 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */ 2791 start = si_get_shaderbuf_slot(num_shaderbufs - 1); 2792 *const_and_shader_buffers = u_bit_consecutive64(start, num_shaderbufs + num_constbufs); 2793 2794 /* The layout is: 2795 * - fmask[last] ... fmask[0] go to [15-last .. 15] 2796 * - image[last] ... image[0] go to [31-last .. 31] 2797 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2] 2798 * 2799 * FMASKs for images are placed separately, because MSAA images are rare, 2800 * and so we can benefit from a better cache hit rate if we keep image 2801 * descriptors together. 2802 */ 2803 if (num_msaa_images) 2804 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */ 2805 2806 start = si_get_image_slot(num_images - 1) / 2; 2807 *samplers_and_images = u_bit_consecutive64(start, num_images / 2 + num_samplers); 2808} 2809 2810static void *si_create_shader_selector(struct pipe_context *ctx, 2811 const struct pipe_shader_state *state) 2812{ 2813 struct si_screen *sscreen = (struct si_screen *)ctx->screen; 2814 struct si_context *sctx = (struct si_context *)ctx; 2815 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector); 2816 int i; 2817 2818 if (!sel) 2819 return NULL; 2820 2821 sel->screen = sscreen; 2822 sel->compiler_ctx_state.debug = sctx->debug; 2823 sel->compiler_ctx_state.is_debug_context = sctx->is_debug; 2824 2825 sel->so = state->stream_output; 2826 2827 if (state->type == PIPE_SHADER_IR_TGSI) { 2828 sel->nir = tgsi_to_nir(state->tokens, ctx->screen, true); 2829 } else { 2830 assert(state->type == PIPE_SHADER_IR_NIR); 2831 sel->nir = state->ir.nir; 2832 } 2833 2834 si_nir_scan_shader(sel->nir, &sel->info); 2835 2836 const enum pipe_shader_type type = pipe_shader_type_from_mesa(sel->info.stage); 2837 sel->pipe_shader_type = type; 2838 sel->const_and_shader_buf_descriptors_index = 2839 si_const_and_shader_buffer_descriptors_idx(type); 2840 sel->sampler_and_images_descriptors_index = 2841 si_sampler_and_image_descriptors_idx(type); 2842 2843 p_atomic_inc(&sscreen->num_shaders_created); 2844 si_get_active_slot_masks(&sel->info, &sel->active_const_and_shader_buffers, 2845 &sel->active_samplers_and_images); 2846 2847 /* Record which streamout buffers are enabled. */ 2848 for (i = 0; i < sel->so.num_outputs; i++) { 2849 sel->enabled_streamout_buffer_mask |= (1 << sel->so.output[i].output_buffer) 2850 << (sel->so.output[i].stream * 4); 2851 } 2852 2853 sel->num_vs_inputs = 2854 sel->info.stage == MESA_SHADER_VERTEX && !sel->info.base.vs.blit_sgprs_amd 2855 ? sel->info.num_inputs 2856 : 0; 2857 unsigned num_vbos_in_sgprs = si_num_vbos_in_user_sgprs_inline(sscreen->info.chip_class); 2858 sel->num_vbos_in_user_sgprs = MIN2(sel->num_vs_inputs, num_vbos_in_sgprs); 2859 2860 /* The prolog is a no-op if there are no inputs. */ 2861 sel->vs_needs_prolog = sel->info.stage == MESA_SHADER_VERTEX && sel->info.num_inputs && 2862 !sel->info.base.vs.blit_sgprs_amd; 2863 2864 if (sel->info.stage == MESA_SHADER_VERTEX || 2865 sel->info.stage == MESA_SHADER_TESS_CTRL || 2866 sel->info.stage == MESA_SHADER_TESS_EVAL || 2867 sel->info.stage == MESA_SHADER_GEOMETRY) { 2868 if (sel->info.stage == MESA_SHADER_TESS_CTRL) { 2869 /* Always reserve space for these. */ 2870 sel->patch_outputs_written |= 2871 (1ull << si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_INNER)) | 2872 (1ull << si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_OUTER)); 2873 } 2874 for (i = 0; i < sel->info.num_outputs; i++) { 2875 unsigned semantic = sel->info.output_semantic[i]; 2876 2877 if (semantic == VARYING_SLOT_TESS_LEVEL_INNER || 2878 semantic == VARYING_SLOT_TESS_LEVEL_OUTER || 2879 (semantic >= VARYING_SLOT_PATCH0 && semantic < VARYING_SLOT_TESS_MAX)) { 2880 sel->patch_outputs_written |= 1ull << si_shader_io_get_unique_index_patch(semantic); 2881 } else if ((semantic <= VARYING_SLOT_VAR31 || semantic >= VARYING_SLOT_VAR0_16BIT) && 2882 semantic != VARYING_SLOT_EDGE) { 2883 sel->outputs_written |= 1ull << si_shader_io_get_unique_index(semantic, false); 2884 2885 /* Ignore outputs that are not passed from VS to PS. */ 2886 if (semantic != VARYING_SLOT_POS && 2887 semantic != VARYING_SLOT_PSIZ && 2888 semantic != VARYING_SLOT_CLIP_VERTEX) { 2889 sel->outputs_written_before_ps |= 1ull 2890 << si_shader_io_get_unique_index(semantic, true); 2891 } 2892 } 2893 } 2894 } 2895 2896 switch (sel->info.stage) { 2897 case MESA_SHADER_GEOMETRY: 2898 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */ 2899 sel->rast_prim = sel->info.base.gs.output_primitive; 2900 if (util_rast_prim_is_triangles(sel->rast_prim)) 2901 sel->rast_prim = PIPE_PRIM_TRIANGLES; 2902 2903 sel->gsvs_vertex_size = sel->info.num_outputs * 16; 2904 sel->max_gsvs_emit_size = sel->gsvs_vertex_size * sel->info.base.gs.vertices_out; 2905 sel->gs_input_verts_per_prim = 2906 u_vertices_per_prim(sel->info.base.gs.input_primitive); 2907 2908 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation so 2909 * we can't split workgroups. Disable ngg if any of the following conditions is true: 2910 * - num_invocations * gs.vertices_out > 256 2911 * - LDS usage is too high 2912 */ 2913 sel->tess_turns_off_ngg = sscreen->info.chip_class >= GFX10 && 2914 (sel->info.base.gs.invocations * sel->info.base.gs.vertices_out > 256 || 2915 sel->info.base.gs.invocations * sel->info.base.gs.vertices_out * 2916 (sel->info.num_outputs * 4 + 1) > 6500 /* max dw per GS primitive */); 2917 break; 2918 2919 case MESA_SHADER_VERTEX: 2920 case MESA_SHADER_TESS_CTRL: 2921 case MESA_SHADER_TESS_EVAL: 2922 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16; 2923 sel->lshs_vertex_stride = sel->esgs_itemsize; 2924 2925 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex 2926 * will start on a different bank. (except for the maximum 32*16). 2927 */ 2928 if (sel->lshs_vertex_stride < 32 * 16) 2929 sel->lshs_vertex_stride += 4; 2930 2931 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank 2932 * conflicts, i.e. each vertex will start at a different bank. 2933 */ 2934 if (sctx->chip_class >= GFX9) 2935 sel->esgs_itemsize += 4; 2936 2937 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0); 2938 2939 sel->tcs_vgpr_only_inputs = ~sel->info.base.tess.tcs_cross_invocation_inputs_read & 2940 ~sel->info.base.inputs_read_indirectly & 2941 sel->info.base.inputs_read; 2942 2943 /* Only for TES: */ 2944 if (sel->info.stage == MESA_SHADER_TESS_EVAL) { 2945 if (sel->info.base.tess.point_mode) 2946 sel->rast_prim = PIPE_PRIM_POINTS; 2947 else if (sel->info.base.tess.primitive_mode == GL_LINES) 2948 sel->rast_prim = PIPE_PRIM_LINE_STRIP; 2949 else 2950 sel->rast_prim = PIPE_PRIM_TRIANGLES; 2951 } else { 2952 sel->rast_prim = PIPE_PRIM_TRIANGLES; 2953 } 2954 break; 2955 2956 case MESA_SHADER_FRAGMENT: 2957 for (i = 0; i < sel->info.num_inputs; i++) { 2958 unsigned semantic = sel->info.input[i].semantic; 2959 2960 if ((semantic <= VARYING_SLOT_VAR31 || semantic >= VARYING_SLOT_VAR0_16BIT) && 2961 semantic != VARYING_SLOT_PNTC) { 2962 sel->inputs_read |= 1ull << si_shader_io_get_unique_index(semantic, true); 2963 } 2964 } 2965 2966 for (i = 0; i < 8; i++) 2967 if (sel->info.colors_written & (1 << i)) 2968 sel->colors_written_4bit |= 0xf << (4 * i); 2969 2970 for (i = 0; i < sel->info.num_inputs; i++) { 2971 if (sel->info.input[i].semantic == VARYING_SLOT_COL0) 2972 sel->color_attr_index[0] = i; 2973 else if (sel->info.input[i].semantic == VARYING_SLOT_COL1) 2974 sel->color_attr_index[1] = i; 2975 } 2976 break; 2977 default:; 2978 } 2979 2980 bool ngg_culling_allowed = 2981 sscreen->info.chip_class >= GFX10 && 2982 sscreen->use_ngg_culling && 2983 (sel->info.stage == MESA_SHADER_VERTEX || 2984 sel->info.stage == MESA_SHADER_TESS_EVAL) && 2985 sel->info.writes_position && 2986 !sel->info.writes_viewport_index && /* cull only against viewport 0 */ 2987 !sel->info.base.writes_memory && !sel->so.num_outputs && 2988 (sel->info.stage != MESA_SHADER_VERTEX || 2989 (!sel->info.base.vs.blit_sgprs_amd && 2990 !sel->info.base.vs.window_space_position)); 2991 2992 sel->ngg_cull_vert_threshold = UINT_MAX; /* disabled (changed below) */ 2993 2994 if (ngg_culling_allowed) { 2995 if (sel->info.stage == MESA_SHADER_VERTEX) { 2996 if (sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING_ALL)) 2997 sel->ngg_cull_vert_threshold = 0; /* always enabled */ 2998 else if (sscreen->options.shader_culling || 2999 sscreen->info.chip_class == GFX10_3 || 3000 (sscreen->info.chip_class == GFX10 && 3001 sscreen->info.is_pro_graphics)) { 3002 sel->ngg_cull_vert_threshold = 128; 3003 } 3004 } else if (sel->info.stage == MESA_SHADER_TESS_EVAL) { 3005 if (sel->rast_prim != PIPE_PRIM_POINTS && 3006 (sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING_ALL) || 3007 sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING_TESS) || 3008 sscreen->info.chip_class == GFX10_3)) 3009 sel->ngg_cull_vert_threshold = 0; /* always enabled */ 3010 } 3011 } 3012 3013 sel->clipdist_mask = sel->info.writes_clipvertex ? SIX_BITS : 3014 u_bit_consecutive(0, sel->info.base.clip_distance_array_size); 3015 sel->culldist_mask = u_bit_consecutive(0, sel->info.base.cull_distance_array_size) << 3016 sel->info.base.clip_distance_array_size; 3017 3018 /* DB_SHADER_CONTROL */ 3019 sel->db_shader_control = S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) | 3020 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) | 3021 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) | 3022 S_02880C_KILL_ENABLE(sel->info.base.fs.uses_discard); 3023 3024 if (sel->info.stage == MESA_SHADER_FRAGMENT) { 3025 switch (sel->info.base.fs.depth_layout) { 3026 case FRAG_DEPTH_LAYOUT_GREATER: 3027 sel->db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z); 3028 break; 3029 case FRAG_DEPTH_LAYOUT_LESS: 3030 sel->db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z); 3031 break; 3032 default:; 3033 } 3034 3035 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following: 3036 * 3037 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP 3038 * --|-----------|------------|------------|--------------------|-------------------|------------- 3039 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0 3040 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0 3041 * 2 | false | true | n/a | LateZ | 1 | 0 3042 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0 3043 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1 3044 * 3045 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register. 3046 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense. 3047 * 3048 * Don't use ReZ without profiling !!! 3049 * 3050 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex 3051 * shaders. 3052 */ 3053 if (sel->info.base.fs.early_fragment_tests) { 3054 /* Cases 3, 4. */ 3055 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) | 3056 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) | 3057 S_02880C_EXEC_ON_NOOP(sel->info.base.writes_memory); 3058 } else if (sel->info.base.writes_memory) { 3059 /* Case 2. */ 3060 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) | S_02880C_EXEC_ON_HIER_FAIL(1); 3061 } else { 3062 /* Case 1. */ 3063 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 3064 } 3065 3066 if (sel->info.base.fs.post_depth_coverage) 3067 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1); 3068 } 3069 3070 (void)simple_mtx_init(&sel->mutex, mtx_plain); 3071 3072 si_schedule_initial_compile(sctx, sel->info.stage, &sel->ready, &sel->compiler_ctx_state, 3073 sel, si_init_shader_selector_async); 3074 return sel; 3075} 3076 3077static void *si_create_shader(struct pipe_context *ctx, const struct pipe_shader_state *state) 3078{ 3079 struct si_context *sctx = (struct si_context *)ctx; 3080 struct si_screen *sscreen = (struct si_screen *)ctx->screen; 3081 bool cache_hit; 3082 struct si_shader_selector *sel = (struct si_shader_selector *)util_live_shader_cache_get( 3083 ctx, &sscreen->live_shader_cache, state, &cache_hit); 3084 3085 if (sel && cache_hit && sctx->debug.debug_message) { 3086 if (sel->main_shader_part) 3087 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part, &sctx->debug); 3088 if (sel->main_shader_part_ls) 3089 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ls, &sctx->debug); 3090 if (sel->main_shader_part_es) 3091 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_es, &sctx->debug); 3092 if (sel->main_shader_part_ngg) 3093 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg, &sctx->debug); 3094 if (sel->main_shader_part_ngg_es) 3095 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg_es, &sctx->debug); 3096 } 3097 return sel; 3098} 3099 3100static void si_update_streamout_state(struct si_context *sctx) 3101{ 3102 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso; 3103 3104 if (!shader_with_so) 3105 return; 3106 3107 sctx->streamout.enabled_stream_buffers_mask = shader_with_so->enabled_streamout_buffer_mask; 3108 sctx->streamout.stride_in_dw = shader_with_so->so.stride; 3109} 3110 3111static void si_update_clip_regs(struct si_context *sctx, struct si_shader_selector *old_hw_vs, 3112 struct si_shader *old_hw_vs_variant, 3113 struct si_shader_selector *next_hw_vs, 3114 struct si_shader *next_hw_vs_variant) 3115{ 3116 if (next_hw_vs && 3117 (!old_hw_vs || 3118 (old_hw_vs->info.stage == MESA_SHADER_VERTEX && old_hw_vs->info.base.vs.window_space_position) != 3119 (next_hw_vs->info.stage == MESA_SHADER_VERTEX && next_hw_vs->info.base.vs.window_space_position) || 3120 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask || 3121 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask || !old_hw_vs_variant || 3122 !next_hw_vs_variant || 3123 old_hw_vs_variant->pa_cl_vs_out_cntl != next_hw_vs_variant->pa_cl_vs_out_cntl)) 3124 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs); 3125} 3126 3127static void si_update_rasterized_prim(struct si_context *sctx) 3128{ 3129 enum pipe_prim_type rast_prim; 3130 3131 if (sctx->shader.gs.cso) { 3132 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */ 3133 rast_prim = sctx->shader.gs.cso->rast_prim; 3134 } else if (sctx->shader.tes.cso) { 3135 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */ 3136 rast_prim = sctx->shader.tes.cso->rast_prim; 3137 } else { 3138 /* Determined by draw calls. */ 3139 return; 3140 } 3141 3142 if (rast_prim != sctx->current_rast_prim) { 3143 if (util_prim_is_points_or_lines(sctx->current_rast_prim) != 3144 util_prim_is_points_or_lines(rast_prim)) 3145 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband); 3146 3147 sctx->current_rast_prim = rast_prim; 3148 } 3149} 3150 3151static void si_update_common_shader_state(struct si_context *sctx, struct si_shader_selector *sel, 3152 enum pipe_shader_type type) 3153{ 3154 si_set_active_descriptors_for_shader(sctx, sel); 3155 3156 sctx->uses_bindless_samplers = si_shader_uses_bindless_samplers(sctx->shader.vs.cso) || 3157 si_shader_uses_bindless_samplers(sctx->shader.gs.cso) || 3158 si_shader_uses_bindless_samplers(sctx->shader.ps.cso) || 3159 si_shader_uses_bindless_samplers(sctx->shader.tcs.cso) || 3160 si_shader_uses_bindless_samplers(sctx->shader.tes.cso); 3161 sctx->uses_bindless_images = si_shader_uses_bindless_images(sctx->shader.vs.cso) || 3162 si_shader_uses_bindless_images(sctx->shader.gs.cso) || 3163 si_shader_uses_bindless_images(sctx->shader.ps.cso) || 3164 si_shader_uses_bindless_images(sctx->shader.tcs.cso) || 3165 si_shader_uses_bindless_images(sctx->shader.tes.cso); 3166 3167 if (type == PIPE_SHADER_VERTEX || type == PIPE_SHADER_TESS_EVAL || type == PIPE_SHADER_GEOMETRY) 3168 sctx->ngg_culling = 0; /* this will be enabled on the first draw if needed */ 3169 3170 si_invalidate_inlinable_uniforms(sctx, type); 3171 sctx->do_update_shaders = true; 3172} 3173 3174static void si_bind_vs_shader(struct pipe_context *ctx, void *state) 3175{ 3176 struct si_context *sctx = (struct si_context *)ctx; 3177 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso; 3178 struct si_shader *old_hw_vs_variant = si_get_vs(sctx)->current; 3179 struct si_shader_selector *sel = state; 3180 3181 if (sctx->shader.vs.cso == sel) 3182 return; 3183 3184 sctx->shader.vs.cso = sel; 3185 sctx->shader.vs.current = sel ? sel->first_variant : NULL; 3186 sctx->num_vs_blit_sgprs = sel ? sel->info.base.vs.blit_sgprs_amd : 0; 3187 sctx->vs_uses_draw_id = sel ? sel->info.uses_drawid : false; 3188 sctx->fixed_func_tcs_shader.key.mono.u.ff_tcs_inputs_to_copy = sel ? sel->outputs_written : 0; 3189 3190 if (si_update_ngg(sctx)) 3191 si_shader_change_notify(sctx); 3192 3193 si_update_common_shader_state(sctx, sel, PIPE_SHADER_VERTEX); 3194 si_select_draw_vbo(sctx); 3195 si_update_vs_viewport_state(sctx); 3196 si_update_streamout_state(sctx); 3197 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, si_get_vs(sctx)->cso, 3198 si_get_vs(sctx)->current); 3199 si_update_rasterized_prim(sctx); 3200 si_vs_key_update_inputs(sctx); 3201} 3202 3203static void si_update_tess_uses_prim_id(struct si_context *sctx) 3204{ 3205 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id = 3206 (sctx->shader.tes.cso && sctx->shader.tes.cso->info.uses_primid) || 3207 (sctx->shader.tcs.cso && sctx->shader.tcs.cso->info.uses_primid) || 3208 (sctx->shader.gs.cso && sctx->shader.gs.cso->info.uses_primid) || 3209 (sctx->shader.ps.cso && !sctx->shader.gs.cso && sctx->shader.ps.cso->info.uses_primid); 3210} 3211 3212bool si_update_ngg(struct si_context *sctx) 3213{ 3214 if (!sctx->screen->use_ngg) { 3215 assert(!sctx->ngg); 3216 return false; 3217 } 3218 3219 bool new_ngg = true; 3220 3221 if (sctx->shader.gs.cso && sctx->shader.tes.cso && sctx->shader.gs.cso->tess_turns_off_ngg) { 3222 new_ngg = false; 3223 } else if (!sctx->screen->use_ngg_streamout) { 3224 struct si_shader_selector *last = si_get_vs(sctx)->cso; 3225 3226 if ((last && last->so.num_outputs) || sctx->streamout.prims_gen_query_enabled) 3227 new_ngg = false; 3228 } 3229 3230 if (new_ngg != sctx->ngg) { 3231 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14. 3232 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring 3233 * pointers are set. 3234 */ 3235 if (sctx->screen->info.has_vgt_flush_ngg_legacy_bug && !new_ngg) { 3236 sctx->flags |= SI_CONTEXT_VGT_FLUSH; 3237 if (sctx->chip_class == GFX10) { 3238 /* Workaround for https://gitlab.freedesktop.org/mesa/mesa/-/issues/2941 */ 3239 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); 3240 } 3241 } 3242 3243 sctx->ngg = new_ngg; 3244 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */ 3245 si_select_draw_vbo(sctx); 3246 return true; 3247 } 3248 return false; 3249} 3250 3251static void si_bind_gs_shader(struct pipe_context *ctx, void *state) 3252{ 3253 struct si_context *sctx = (struct si_context *)ctx; 3254 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso; 3255 struct si_shader *old_hw_vs_variant = si_get_vs(sctx)->current; 3256 struct si_shader_selector *sel = state; 3257 bool enable_changed = !!sctx->shader.gs.cso != !!sel; 3258 bool ngg_changed; 3259 3260 if (sctx->shader.gs.cso == sel) 3261 return; 3262 3263 sctx->shader.gs.cso = sel; 3264 sctx->shader.gs.current = sel ? sel->first_variant : NULL; 3265 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL; 3266 3267 si_update_common_shader_state(sctx, sel, PIPE_SHADER_GEOMETRY); 3268 si_select_draw_vbo(sctx); 3269 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */ 3270 3271 ngg_changed = si_update_ngg(sctx); 3272 if (ngg_changed || enable_changed) 3273 si_shader_change_notify(sctx); 3274 if (enable_changed) { 3275 if (sctx->ia_multi_vgt_param_key.u.uses_tess) 3276 si_update_tess_uses_prim_id(sctx); 3277 } 3278 si_update_vs_viewport_state(sctx); 3279 si_update_streamout_state(sctx); 3280 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, si_get_vs(sctx)->cso, 3281 si_get_vs(sctx)->current); 3282 si_update_rasterized_prim(sctx); 3283} 3284 3285static void si_bind_tcs_shader(struct pipe_context *ctx, void *state) 3286{ 3287 struct si_context *sctx = (struct si_context *)ctx; 3288 struct si_shader_selector *sel = state; 3289 bool enable_changed = !!sctx->shader.tcs.cso != !!sel; 3290 3291 if (sctx->shader.tcs.cso == sel) 3292 return; 3293 3294 sctx->shader.tcs.cso = sel; 3295 sctx->shader.tcs.current = sel ? sel->first_variant : NULL; 3296 sctx->shader.tcs.key.part.tcs.epilog.invoc0_tess_factors_are_def = 3297 sel ? sel->info.tessfactors_are_def_in_all_invocs : 0; 3298 si_update_tess_uses_prim_id(sctx); 3299 3300 si_update_common_shader_state(sctx, sel, PIPE_SHADER_TESS_CTRL); 3301 3302 if (enable_changed) 3303 sctx->last_tcs = NULL; /* invalidate derived tess state */ 3304} 3305 3306static void si_bind_tes_shader(struct pipe_context *ctx, void *state) 3307{ 3308 struct si_context *sctx = (struct si_context *)ctx; 3309 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso; 3310 struct si_shader *old_hw_vs_variant = si_get_vs(sctx)->current; 3311 struct si_shader_selector *sel = state; 3312 bool enable_changed = !!sctx->shader.tes.cso != !!sel; 3313 3314 if (sctx->shader.tes.cso == sel) 3315 return; 3316 3317 sctx->shader.tes.cso = sel; 3318 sctx->shader.tes.current = sel ? sel->first_variant : NULL; 3319 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL; 3320 si_update_tess_uses_prim_id(sctx); 3321 3322 sctx->shader.tcs.key.part.tcs.epilog.prim_mode = 3323 sctx->fixed_func_tcs_shader.key.part.tcs.epilog.prim_mode = 3324 sel ? sel->info.base.tess.primitive_mode : 0; 3325 3326 sctx->shader.tcs.key.part.tcs.epilog.tes_reads_tess_factors = 3327 sctx->fixed_func_tcs_shader.key.part.tcs.epilog.tes_reads_tess_factors = 3328 sel ? sel->info.reads_tess_factors : 0; 3329 3330 si_update_common_shader_state(sctx, sel, PIPE_SHADER_TESS_EVAL); 3331 si_select_draw_vbo(sctx); 3332 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */ 3333 3334 bool ngg_changed = si_update_ngg(sctx); 3335 if (ngg_changed || enable_changed) 3336 si_shader_change_notify(sctx); 3337 if (enable_changed) 3338 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */ 3339 si_update_vs_viewport_state(sctx); 3340 si_update_streamout_state(sctx); 3341 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, si_get_vs(sctx)->cso, 3342 si_get_vs(sctx)->current); 3343 si_update_rasterized_prim(sctx); 3344} 3345 3346void si_update_ps_kill_enable(struct si_context *sctx) 3347{ 3348 if (!sctx->shader.ps.cso) 3349 return; 3350 3351 unsigned db_shader_control = sctx->shader.ps.cso->db_shader_control | 3352 S_02880C_KILL_ENABLE(sctx->queued.named.dsa->alpha_func != PIPE_FUNC_ALWAYS); 3353 3354 if (sctx->ps_db_shader_control != db_shader_control) { 3355 sctx->ps_db_shader_control = db_shader_control; 3356 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 3357 if (sctx->screen->dpbb_allowed) 3358 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state); 3359 } 3360} 3361 3362void si_update_vrs_flat_shading(struct si_context *sctx) 3363{ 3364 if (sctx->chip_class >= GFX10_3 && sctx->shader.ps.cso) { 3365 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 3366 struct si_shader_info *info = &sctx->shader.ps.cso->info; 3367 bool allow_flat_shading = info->allow_flat_shading; 3368 3369 if (allow_flat_shading && 3370 (rs->line_smooth || rs->poly_smooth || rs->poly_stipple_enable || 3371 (!rs->flatshade && info->uses_interp_color))) 3372 allow_flat_shading = false; 3373 3374 if (sctx->allow_flat_shading != allow_flat_shading) { 3375 sctx->allow_flat_shading = allow_flat_shading; 3376 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 3377 } 3378 } 3379} 3380 3381static void si_bind_ps_shader(struct pipe_context *ctx, void *state) 3382{ 3383 struct si_context *sctx = (struct si_context *)ctx; 3384 struct si_shader_selector *old_sel = sctx->shader.ps.cso; 3385 struct si_shader_selector *sel = state; 3386 3387 /* skip if supplied shader is one already in use */ 3388 if (old_sel == sel) 3389 return; 3390 3391 sctx->shader.ps.cso = sel; 3392 sctx->shader.ps.current = sel ? sel->first_variant : NULL; 3393 3394 si_update_common_shader_state(sctx, sel, PIPE_SHADER_FRAGMENT); 3395 if (sel) { 3396 if (sctx->ia_multi_vgt_param_key.u.uses_tess) 3397 si_update_tess_uses_prim_id(sctx); 3398 3399 if (!old_sel || old_sel->info.colors_written != sel->info.colors_written) 3400 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state); 3401 3402 if (sctx->screen->has_out_of_order_rast && 3403 (!old_sel || old_sel->info.base.writes_memory != sel->info.base.writes_memory || 3404 old_sel->info.base.fs.early_fragment_tests != 3405 sel->info.base.fs.early_fragment_tests)) 3406 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config); 3407 } 3408 si_update_ps_colorbuf0_slot(sctx); 3409 3410 si_ps_key_update_framebuffer(sctx); 3411 si_ps_key_update_framebuffer_blend(sctx); 3412 si_ps_key_update_blend_rasterizer(sctx); 3413 si_ps_key_update_rasterizer(sctx); 3414 si_ps_key_update_dsa(sctx); 3415 si_ps_key_update_sample_shading(sctx); 3416 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx); 3417 si_update_ps_inputs_read_or_disabled(sctx); 3418 si_update_ps_kill_enable(sctx); 3419 si_update_vrs_flat_shading(sctx); 3420} 3421 3422static void si_delete_shader(struct si_context *sctx, struct si_shader *shader) 3423{ 3424 if (shader->is_optimized) { 3425 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority, &shader->ready); 3426 } 3427 3428 util_queue_fence_destroy(&shader->ready); 3429 3430 /* If destroyed shaders were not unbound, the next compiled 3431 * shader variant could get the same pointer address and so 3432 * binding it to the same shader stage would be considered 3433 * a no-op, causing random behavior. 3434 */ 3435 int state_index = -1; 3436 3437 switch (shader->selector->info.stage) { 3438 case MESA_SHADER_VERTEX: 3439 if (shader->key.as_ls) { 3440 if (sctx->chip_class <= GFX8) 3441 state_index = SI_STATE_IDX(ls); 3442 } else if (shader->key.as_es) { 3443 if (sctx->chip_class <= GFX8) 3444 state_index = SI_STATE_IDX(es); 3445 } else if (shader->key.as_ngg) { 3446 state_index = SI_STATE_IDX(gs); 3447 } else { 3448 state_index = SI_STATE_IDX(vs); 3449 } 3450 break; 3451 case MESA_SHADER_TESS_CTRL: 3452 state_index = SI_STATE_IDX(hs); 3453 break; 3454 case MESA_SHADER_TESS_EVAL: 3455 if (shader->key.as_es) { 3456 if (sctx->chip_class <= GFX8) 3457 state_index = SI_STATE_IDX(es); 3458 } else if (shader->key.as_ngg) { 3459 state_index = SI_STATE_IDX(gs); 3460 } else { 3461 state_index = SI_STATE_IDX(vs); 3462 } 3463 break; 3464 case MESA_SHADER_GEOMETRY: 3465 if (shader->is_gs_copy_shader) 3466 state_index = SI_STATE_IDX(vs); 3467 else 3468 state_index = SI_STATE_IDX(gs); 3469 break; 3470 case MESA_SHADER_FRAGMENT: 3471 state_index = SI_STATE_IDX(ps); 3472 break; 3473 default:; 3474 } 3475 3476 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL); 3477 si_shader_destroy(shader); 3478 si_pm4_free_state(sctx, &shader->pm4, state_index); 3479} 3480 3481static void si_destroy_shader_selector(struct pipe_context *ctx, void *cso) 3482{ 3483 struct si_context *sctx = (struct si_context *)ctx; 3484 struct si_shader_selector *sel = (struct si_shader_selector *)cso; 3485 struct si_shader *p = sel->first_variant, *c; 3486 enum pipe_shader_type type = pipe_shader_type_from_mesa(sel->info.stage); 3487 3488 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready); 3489 3490 if (sctx->shaders[type].cso == sel) { 3491 sctx->shaders[type].cso = NULL; 3492 sctx->shaders[type].current = NULL; 3493 } 3494 3495 while (p) { 3496 c = p->next_variant; 3497 si_delete_shader(sctx, p); 3498 p = c; 3499 } 3500 3501 if (sel->main_shader_part) 3502 si_delete_shader(sctx, sel->main_shader_part); 3503 if (sel->main_shader_part_ls) 3504 si_delete_shader(sctx, sel->main_shader_part_ls); 3505 if (sel->main_shader_part_es) 3506 si_delete_shader(sctx, sel->main_shader_part_es); 3507 if (sel->main_shader_part_ngg) 3508 si_delete_shader(sctx, sel->main_shader_part_ngg); 3509 if (sel->gs_copy_shader) 3510 si_delete_shader(sctx, sel->gs_copy_shader); 3511 3512 util_queue_fence_destroy(&sel->ready); 3513 simple_mtx_destroy(&sel->mutex); 3514 ralloc_free(sel->nir); 3515 free(sel->nir_binary); 3516 free(sel); 3517} 3518 3519static void si_delete_shader_selector(struct pipe_context *ctx, void *state) 3520{ 3521 struct si_context *sctx = (struct si_context *)ctx; 3522 struct si_shader_selector *sel = (struct si_shader_selector *)state; 3523 3524 si_shader_selector_reference(sctx, &sel, NULL); 3525} 3526 3527/** 3528 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that. 3529 */ 3530static void si_cs_preamble_add_vgt_flush(struct si_context *sctx) 3531{ 3532 /* We shouldn't get here if registers are shadowed. */ 3533 assert(!sctx->shadowed_regs); 3534 3535 if (sctx->cs_preamble_has_vgt_flush) 3536 return; 3537 3538 /* Done by Vulkan before VGT_FLUSH. */ 3539 si_pm4_cmd_add(sctx->cs_preamble_state, PKT3(PKT3_EVENT_WRITE, 0, 0)); 3540 si_pm4_cmd_add(sctx->cs_preamble_state, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); 3541 3542 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */ 3543 si_pm4_cmd_add(sctx->cs_preamble_state, PKT3(PKT3_EVENT_WRITE, 0, 0)); 3544 si_pm4_cmd_add(sctx->cs_preamble_state, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); 3545 sctx->cs_preamble_has_vgt_flush = true; 3546} 3547 3548/** 3549 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that. 3550 */ 3551static void si_emit_vgt_flush(struct radeon_cmdbuf *cs) 3552{ 3553 radeon_begin(cs); 3554 3555 /* This is required before VGT_FLUSH. */ 3556 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); 3557 radeon_emit(EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); 3558 3559 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */ 3560 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); 3561 radeon_emit(EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); 3562 radeon_end(); 3563} 3564 3565/* Initialize state related to ESGS / GSVS ring buffers */ 3566bool si_update_gs_ring_buffers(struct si_context *sctx) 3567{ 3568 struct si_shader_selector *es = 3569 sctx->shader.tes.cso ? sctx->shader.tes.cso : sctx->shader.vs.cso; 3570 struct si_shader_selector *gs = sctx->shader.gs.cso; 3571 struct si_pm4_state *pm4; 3572 3573 /* Chip constants. */ 3574 unsigned num_se = sctx->screen->info.max_se; 3575 unsigned wave_size = 64; 3576 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */ 3577 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16. 3578 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2). 3579 */ 3580 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se; 3581 unsigned alignment = 256 * num_se; 3582 /* The maximum size is 63.999 MB per SE. */ 3583 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se; 3584 3585 /* Calculate the minimum size. */ 3586 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse * wave_size, alignment); 3587 3588 /* These are recommended sizes, not minimum sizes. */ 3589 unsigned esgs_ring_size = 3590 max_gs_waves * 2 * wave_size * es->esgs_itemsize * gs->gs_input_verts_per_prim; 3591 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * gs->max_gsvs_emit_size; 3592 3593 min_esgs_ring_size = align(min_esgs_ring_size, alignment); 3594 esgs_ring_size = align(esgs_ring_size, alignment); 3595 gsvs_ring_size = align(gsvs_ring_size, alignment); 3596 3597 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size); 3598 gsvs_ring_size = MIN2(gsvs_ring_size, max_size); 3599 3600 /* Some rings don't have to be allocated if shaders don't use them. 3601 * (e.g. no varyings between ES and GS or GS and VS) 3602 * 3603 * GFX9 doesn't have the ESGS ring. 3604 */ 3605 bool update_esgs = sctx->chip_class <= GFX8 && esgs_ring_size && 3606 (!sctx->esgs_ring || sctx->esgs_ring->width0 < esgs_ring_size); 3607 bool update_gsvs = 3608 gsvs_ring_size && (!sctx->gsvs_ring || sctx->gsvs_ring->width0 < gsvs_ring_size); 3609 3610 if (!update_esgs && !update_gsvs) 3611 return true; 3612 3613 if (update_esgs) { 3614 pipe_resource_reference(&sctx->esgs_ring, NULL); 3615 sctx->esgs_ring = 3616 pipe_aligned_buffer_create(sctx->b.screen, 3617 SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL, 3618 PIPE_USAGE_DEFAULT, 3619 esgs_ring_size, sctx->screen->info.pte_fragment_size); 3620 if (!sctx->esgs_ring) 3621 return false; 3622 } 3623 3624 if (update_gsvs) { 3625 pipe_resource_reference(&sctx->gsvs_ring, NULL); 3626 sctx->gsvs_ring = 3627 pipe_aligned_buffer_create(sctx->b.screen, 3628 SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL, 3629 PIPE_USAGE_DEFAULT, 3630 gsvs_ring_size, sctx->screen->info.pte_fragment_size); 3631 if (!sctx->gsvs_ring) 3632 return false; 3633 } 3634 3635 /* Set ring bindings. */ 3636 if (sctx->esgs_ring) { 3637 assert(sctx->chip_class <= GFX8); 3638 si_set_ring_buffer(sctx, SI_ES_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, true, 3639 true, 4, 64, 0); 3640 si_set_ring_buffer(sctx, SI_GS_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false, 3641 false, 0, 0, 0); 3642 } 3643 if (sctx->gsvs_ring) { 3644 si_set_ring_buffer(sctx, SI_RING_GSVS, sctx->gsvs_ring, 0, sctx->gsvs_ring->width0, false, 3645 false, 0, 0, 0); 3646 } 3647 3648 if (sctx->shadowed_regs) { 3649 /* These registers will be shadowed, so set them only once. */ 3650 struct radeon_cmdbuf *cs = &sctx->gfx_cs; 3651 3652 assert(sctx->chip_class >= GFX7); 3653 3654 si_emit_vgt_flush(cs); 3655 3656 radeon_begin(cs); 3657 3658 /* Set the GS registers. */ 3659 if (sctx->esgs_ring) { 3660 assert(sctx->chip_class <= GFX8); 3661 radeon_set_uconfig_reg(R_030900_VGT_ESGS_RING_SIZE, 3662 sctx->esgs_ring->width0 / 256); 3663 } 3664 if (sctx->gsvs_ring) { 3665 radeon_set_uconfig_reg(R_030904_VGT_GSVS_RING_SIZE, 3666 sctx->gsvs_ring->width0 / 256); 3667 } 3668 radeon_end(); 3669 return true; 3670 } 3671 3672 /* The codepath without register shadowing. */ 3673 /* Create the "cs_preamble_gs_rings" state. */ 3674 pm4 = CALLOC_STRUCT(si_pm4_state); 3675 if (!pm4) 3676 return false; 3677 3678 if (sctx->chip_class >= GFX7) { 3679 if (sctx->esgs_ring) { 3680 assert(sctx->chip_class <= GFX8); 3681 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE, sctx->esgs_ring->width0 / 256); 3682 } 3683 if (sctx->gsvs_ring) 3684 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE, sctx->gsvs_ring->width0 / 256); 3685 } else { 3686 if (sctx->esgs_ring) 3687 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE, sctx->esgs_ring->width0 / 256); 3688 if (sctx->gsvs_ring) 3689 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE, sctx->gsvs_ring->width0 / 256); 3690 } 3691 3692 /* Set the state. */ 3693 if (sctx->cs_preamble_gs_rings) 3694 si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0); 3695 sctx->cs_preamble_gs_rings = pm4; 3696 3697 si_cs_preamble_add_vgt_flush(sctx); 3698 3699 /* Flush the context to re-emit both cs_preamble states. */ 3700 sctx->initial_gfx_cs_size = 0; /* force flush */ 3701 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); 3702 3703 return true; 3704} 3705 3706static void si_shader_lock(struct si_shader *shader) 3707{ 3708 simple_mtx_lock(&shader->selector->mutex); 3709 if (shader->previous_stage_sel) { 3710 assert(shader->previous_stage_sel != shader->selector); 3711 simple_mtx_lock(&shader->previous_stage_sel->mutex); 3712 } 3713} 3714 3715static void si_shader_unlock(struct si_shader *shader) 3716{ 3717 if (shader->previous_stage_sel) 3718 simple_mtx_unlock(&shader->previous_stage_sel->mutex); 3719 simple_mtx_unlock(&shader->selector->mutex); 3720} 3721 3722/** 3723 * @returns 1 if \p sel has been updated to use a new scratch buffer 3724 * 0 if not 3725 * < 0 if there was a failure 3726 */ 3727static int si_update_scratch_buffer(struct si_context *sctx, struct si_shader *shader) 3728{ 3729 uint64_t scratch_va = sctx->scratch_buffer->gpu_address; 3730 3731 if (!shader) 3732 return 0; 3733 3734 /* This shader doesn't need a scratch buffer */ 3735 if (shader->config.scratch_bytes_per_wave == 0) 3736 return 0; 3737 3738 /* Prevent race conditions when updating: 3739 * - si_shader::scratch_bo 3740 * - si_shader::binary::code 3741 * - si_shader::previous_stage::binary::code. 3742 */ 3743 si_shader_lock(shader); 3744 3745 /* This shader is already configured to use the current 3746 * scratch buffer. */ 3747 if (shader->scratch_bo == sctx->scratch_buffer) { 3748 si_shader_unlock(shader); 3749 return 0; 3750 } 3751 3752 assert(sctx->scratch_buffer); 3753 3754 /* Replace the shader bo with a new bo that has the relocs applied. */ 3755 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) { 3756 si_shader_unlock(shader); 3757 return -1; 3758 } 3759 3760 /* Update the shader state to use the new shader bo. */ 3761 si_shader_init_pm4_state(sctx->screen, shader); 3762 3763 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer); 3764 3765 si_shader_unlock(shader); 3766 return 1; 3767} 3768 3769static struct si_shader *si_get_tcs_current(struct si_context *sctx) 3770{ 3771 if (!sctx->shader.tes.cso) 3772 return NULL; /* tessellation disabled */ 3773 3774 return sctx->shader.tcs.cso ? sctx->shader.tcs.current : sctx->fixed_func_tcs_shader.current; 3775} 3776 3777static bool si_update_scratch_relocs(struct si_context *sctx) 3778{ 3779 struct si_shader *tcs = si_get_tcs_current(sctx); 3780 int r; 3781 3782 /* Update the shaders, so that they are using the latest scratch. 3783 * The scratch buffer may have been changed since these shaders were 3784 * last used, so we still need to try to update them, even if they 3785 * require scratch buffers smaller than the current size. 3786 */ 3787 r = si_update_scratch_buffer(sctx, sctx->shader.ps.current); 3788 if (r < 0) 3789 return false; 3790 if (r == 1) 3791 si_pm4_bind_state(sctx, ps, sctx->shader.ps.current); 3792 3793 r = si_update_scratch_buffer(sctx, sctx->shader.gs.current); 3794 if (r < 0) 3795 return false; 3796 if (r == 1) 3797 si_pm4_bind_state(sctx, gs, sctx->shader.gs.current); 3798 3799 r = si_update_scratch_buffer(sctx, tcs); 3800 if (r < 0) 3801 return false; 3802 if (r == 1) 3803 si_pm4_bind_state(sctx, hs, tcs); 3804 3805 /* VS can be bound as LS, ES, or VS. */ 3806 r = si_update_scratch_buffer(sctx, sctx->shader.vs.current); 3807 if (r < 0) 3808 return false; 3809 if (r == 1) { 3810 if (sctx->shader.vs.current->key.as_ls) 3811 si_pm4_bind_state(sctx, ls, sctx->shader.vs.current); 3812 else if (sctx->shader.vs.current->key.as_es) 3813 si_pm4_bind_state(sctx, es, sctx->shader.vs.current); 3814 else if (sctx->shader.vs.current->key.as_ngg) 3815 si_pm4_bind_state(sctx, gs, sctx->shader.vs.current); 3816 else 3817 si_pm4_bind_state(sctx, vs, sctx->shader.vs.current); 3818 } 3819 3820 /* TES can be bound as ES or VS. */ 3821 r = si_update_scratch_buffer(sctx, sctx->shader.tes.current); 3822 if (r < 0) 3823 return false; 3824 if (r == 1) { 3825 if (sctx->shader.tes.current->key.as_es) 3826 si_pm4_bind_state(sctx, es, sctx->shader.tes.current); 3827 else if (sctx->shader.tes.current->key.as_ngg) 3828 si_pm4_bind_state(sctx, gs, sctx->shader.tes.current); 3829 else 3830 si_pm4_bind_state(sctx, vs, sctx->shader.tes.current); 3831 } 3832 3833 return true; 3834} 3835 3836bool si_update_spi_tmpring_size(struct si_context *sctx, unsigned bytes) 3837{ 3838 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer. 3839 * There are 2 cases to handle: 3840 * 3841 * - If the current needed size is less than the maximum seen size, 3842 * use the maximum seen size, so that WAVESIZE remains the same. 3843 * 3844 * - If the current needed size is greater than the maximum seen size, 3845 * the scratch buffer is reallocated, so we can increase WAVESIZE. 3846 * 3847 * Shaders that set SCRATCH_EN=0 don't allocate scratch space. 3848 * Otherwise, the number of waves that can use scratch is 3849 * SPI_TMPRING_SIZE.WAVES. 3850 */ 3851 sctx->max_seen_scratch_bytes_per_wave = MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes); 3852 3853 unsigned scratch_needed_size = sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves; 3854 unsigned spi_tmpring_size; 3855 3856 if (scratch_needed_size > 0) { 3857 if (!sctx->scratch_buffer || scratch_needed_size > sctx->scratch_buffer->b.b.width0) { 3858 /* Create a bigger scratch buffer */ 3859 si_resource_reference(&sctx->scratch_buffer, NULL); 3860 3861 sctx->scratch_buffer = si_aligned_buffer_create( 3862 &sctx->screen->b, 3863 SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL, 3864 PIPE_USAGE_DEFAULT, scratch_needed_size, 3865 sctx->screen->info.pte_fragment_size); 3866 if (!sctx->scratch_buffer) 3867 return false; 3868 3869 si_context_add_resource_size(sctx, &sctx->scratch_buffer->b.b); 3870 } 3871 3872 if (!si_update_scratch_relocs(sctx)) 3873 return false; 3874 } 3875 3876 /* The LLVM shader backend should be reporting aligned scratch_sizes. */ 3877 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size && 3878 "scratch size should already be aligned correctly."); 3879 3880 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) | 3881 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10); 3882 if (spi_tmpring_size != sctx->spi_tmpring_size) { 3883 sctx->spi_tmpring_size = spi_tmpring_size; 3884 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state); 3885 } 3886 return true; 3887} 3888 3889void si_init_tess_factor_ring(struct si_context *sctx) 3890{ 3891 assert(!sctx->tess_rings); 3892 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0); 3893 3894 /* The address must be aligned to 2^19, because the shader only 3895 * receives the high 13 bits. 3896 */ 3897 sctx->tess_rings = pipe_aligned_buffer_create( 3898 sctx->b.screen, SI_RESOURCE_FLAG_32BIT | SI_RESOURCE_FLAG_DRIVER_INTERNAL, PIPE_USAGE_DEFAULT, 3899 sctx->screen->tess_offchip_ring_size + sctx->screen->tess_factor_ring_size, 1 << 19); 3900 if (!sctx->tess_rings) 3901 return; 3902 3903 if (sctx->screen->info.has_tmz_support) { 3904 sctx->tess_rings_tmz = pipe_aligned_buffer_create( 3905 sctx->b.screen, 3906 PIPE_RESOURCE_FLAG_ENCRYPTED | SI_RESOURCE_FLAG_32BIT | SI_RESOURCE_FLAG_DRIVER_INTERNAL, 3907 PIPE_USAGE_DEFAULT, 3908 sctx->screen->tess_offchip_ring_size + sctx->screen->tess_factor_ring_size, 1 << 19); 3909 } 3910 3911 uint64_t factor_va = 3912 si_resource(sctx->tess_rings)->gpu_address + sctx->screen->tess_offchip_ring_size; 3913 3914 if (sctx->shadowed_regs) { 3915 /* These registers will be shadowed, so set them only once. */ 3916 /* TODO: tmz + shadowed_regs support */ 3917 struct radeon_cmdbuf *cs = &sctx->gfx_cs; 3918 3919 assert(sctx->chip_class >= GFX7); 3920 3921 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(sctx->tess_rings), 3922 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS); 3923 si_emit_vgt_flush(cs); 3924 3925 /* Set tessellation registers. */ 3926 radeon_begin(cs); 3927 radeon_set_uconfig_reg(R_030938_VGT_TF_RING_SIZE, 3928 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4)); 3929 radeon_set_uconfig_reg(R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8); 3930 if (sctx->chip_class >= GFX10) { 3931 radeon_set_uconfig_reg(R_030984_VGT_TF_MEMORY_BASE_HI_UMD, 3932 S_030984_BASE_HI(factor_va >> 40)); 3933 } else if (sctx->chip_class == GFX9) { 3934 radeon_set_uconfig_reg(R_030944_VGT_TF_MEMORY_BASE_HI, 3935 S_030944_BASE_HI(factor_va >> 40)); 3936 } 3937 radeon_set_uconfig_reg(R_03093C_VGT_HS_OFFCHIP_PARAM, 3938 sctx->screen->vgt_hs_offchip_param); 3939 radeon_end(); 3940 return; 3941 } 3942 3943 /* The codepath without register shadowing. */ 3944 si_cs_preamble_add_vgt_flush(sctx); 3945 3946 /* Append these registers to the init config state. */ 3947 if (sctx->chip_class >= GFX7) { 3948 si_pm4_set_reg(sctx->cs_preamble_state, R_030938_VGT_TF_RING_SIZE, 3949 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4)); 3950 si_pm4_set_reg(sctx->cs_preamble_state, R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8); 3951 if (sctx->chip_class >= GFX10) 3952 si_pm4_set_reg(sctx->cs_preamble_state, R_030984_VGT_TF_MEMORY_BASE_HI_UMD, 3953 S_030984_BASE_HI(factor_va >> 40)); 3954 else if (sctx->chip_class == GFX9) 3955 si_pm4_set_reg(sctx->cs_preamble_state, R_030944_VGT_TF_MEMORY_BASE_HI, 3956 S_030944_BASE_HI(factor_va >> 40)); 3957 si_pm4_set_reg(sctx->cs_preamble_state, R_03093C_VGT_HS_OFFCHIP_PARAM, 3958 sctx->screen->vgt_hs_offchip_param); 3959 } else { 3960 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 3961 3962 si_pm4_set_reg(pm4, R_008988_VGT_TF_RING_SIZE, 3963 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4)); 3964 si_pm4_set_reg(pm4, R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8); 3965 si_pm4_set_reg(pm4, R_0089B0_VGT_HS_OFFCHIP_PARAM, 3966 sctx->screen->vgt_hs_offchip_param); 3967 sctx->cs_preamble_tess_rings = pm4; 3968 3969 if (sctx->screen->info.has_tmz_support) { 3970 pm4 = CALLOC_STRUCT(si_pm4_state); 3971 uint64_t factor_va_tmz = 3972 si_resource(sctx->tess_rings_tmz)->gpu_address + sctx->screen->tess_offchip_ring_size; 3973 si_pm4_set_reg(pm4, R_008988_VGT_TF_RING_SIZE, 3974 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4)); 3975 si_pm4_set_reg(pm4, R_0089B8_VGT_TF_MEMORY_BASE, factor_va_tmz >> 8); 3976 si_pm4_set_reg(pm4, R_0089B0_VGT_HS_OFFCHIP_PARAM, 3977 sctx->screen->vgt_hs_offchip_param); 3978 sctx->cs_preamble_tess_rings_tmz = pm4; 3979 } 3980 } 3981 3982 /* Flush the context to re-emit the cs_preamble state. 3983 * This is done only once in a lifetime of a context. 3984 */ 3985 sctx->initial_gfx_cs_size = 0; /* force flush */ 3986 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); 3987} 3988 3989struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen, union si_vgt_stages_key key) 3990{ 3991 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 3992 uint32_t stages = 0; 3993 3994 if (key.u.tess) { 3995 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) | S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1); 3996 3997 if (key.u.gs) 3998 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) | S_028B54_GS_EN(1); 3999 else if (key.u.ngg) 4000 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS); 4001 else 4002 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS); 4003 } else if (key.u.gs) { 4004 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) | S_028B54_GS_EN(1); 4005 } else if (key.u.ngg) { 4006 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL); 4007 } 4008 4009 if (key.u.ngg) { 4010 stages |= S_028B54_PRIMGEN_EN(1) | 4011 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) | 4012 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough) | 4013 S_028B54_PRIMGEN_PASSTHRU_NO_MSG(key.u.ngg_passthrough && 4014 screen->info.family >= CHIP_DIMGREY_CAVEFISH); 4015 } else if (key.u.gs) 4016 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); 4017 4018 if (screen->info.chip_class >= GFX9) 4019 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2); 4020 4021 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) { 4022 stages |= S_028B54_HS_W32_EN(1) | 4023 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */ 4024 S_028B54_VS_W32_EN(1); 4025 } 4026 4027 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages); 4028 return pm4; 4029} 4030 4031static void si_emit_scratch_state(struct si_context *sctx) 4032{ 4033 struct radeon_cmdbuf *cs = &sctx->gfx_cs; 4034 4035 radeon_begin(cs); 4036 radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size); 4037 radeon_end(); 4038 4039 if (sctx->scratch_buffer) { 4040 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->scratch_buffer, RADEON_USAGE_READWRITE, 4041 RADEON_PRIO_SCRATCH_BUFFER); 4042 } 4043} 4044 4045void si_init_screen_live_shader_cache(struct si_screen *sscreen) 4046{ 4047 util_live_shader_cache_init(&sscreen->live_shader_cache, si_create_shader_selector, 4048 si_destroy_shader_selector); 4049} 4050 4051void si_init_shader_functions(struct si_context *sctx) 4052{ 4053 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state; 4054 4055 sctx->b.create_vs_state = si_create_shader; 4056 sctx->b.create_tcs_state = si_create_shader; 4057 sctx->b.create_tes_state = si_create_shader; 4058 sctx->b.create_gs_state = si_create_shader; 4059 sctx->b.create_fs_state = si_create_shader; 4060 4061 sctx->b.bind_vs_state = si_bind_vs_shader; 4062 sctx->b.bind_tcs_state = si_bind_tcs_shader; 4063 sctx->b.bind_tes_state = si_bind_tes_shader; 4064 sctx->b.bind_gs_state = si_bind_gs_shader; 4065 sctx->b.bind_fs_state = si_bind_ps_shader; 4066 4067 sctx->b.delete_vs_state = si_delete_shader_selector; 4068 sctx->b.delete_tcs_state = si_delete_shader_selector; 4069 sctx->b.delete_tes_state = si_delete_shader_selector; 4070 sctx->b.delete_gs_state = si_delete_shader_selector; 4071 sctx->b.delete_fs_state = si_delete_shader_selector; 4072} 4073