1 /* $NetBSD: if_aumac.c,v 1.53 2024/06/29 12:11:11 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.53 2024/06/29 12:11:11 riastradh Exp $"); 50 51 52 53 #include <sys/param.h> 54 #include <sys/bus.h> 55 #include <sys/callout.h> 56 #include <sys/device.h> 57 #include <sys/endian.h> 58 #include <sys/errno.h> 59 #include <sys/intr.h> 60 #include <sys/ioctl.h> 61 #include <sys/kernel.h> 62 #include <sys/mbuf.h> 63 #include <sys/socket.h> 64 65 #include <uvm/uvm.h> /* for PAGE_SIZE */ 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_media.h> 70 #include <net/if_ether.h> 71 72 #include <net/bpf.h> 73 #include <sys/rndsource.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 78 #include <mips/alchemy/include/aureg.h> 79 #include <mips/alchemy/include/auvar.h> 80 #include <mips/alchemy/include/aubusvar.h> 81 #include <mips/alchemy/dev/if_aumacreg.h> 82 83 /* 84 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 85 * must consist of a single DMA segment, and must be aligned to a 2K 86 * boundary. Therefore, this driver does not perform DMA directly 87 * to/from mbufs. Instead, we copy the data to/from buffers allocated 88 * at device attach time. 89 * 90 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 91 * there's little point in not making assumptions based on the CPU type. 92 * We also program the Au1X00 cache to be DMA coherent, so the buffers 93 * are accessed via KSEG0 addresses. 94 */ 95 #define AUMAC_NTXDESC 4 96 #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 97 98 #define AUMAC_NRXDESC 4 99 #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 100 101 #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 102 #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 103 104 #define AUMAC_TXBUF_OFFSET 0 105 #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 106 #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 107 108 struct aumac_buf { 109 vaddr_t buf_vaddr; /* virtual address of buffer */ 110 bus_addr_t buf_paddr; /* DMA address of buffer */ 111 }; 112 113 /* 114 * Software state per device. 115 */ 116 struct aumac_softc { 117 device_t sc_dev; /* generic device information */ 118 bus_space_tag_t sc_st; /* bus space tag */ 119 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 120 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 121 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 122 struct ethercom sc_ethercom; /* Ethernet common data */ 123 void *sc_sdhook; /* shutdown hook */ 124 125 int sc_irq; 126 void *sc_ih; /* interrupt cookie */ 127 128 struct mii_data sc_mii; /* MII/media information */ 129 130 struct callout sc_tick_ch; /* tick callout */ 131 132 /* Transmit and receive buffers */ 133 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 134 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 135 void *sc_bufaddr; 136 137 int sc_txfree; /* number of free Tx descriptors */ 138 int sc_txnext; /* next Tx descriptor to use */ 139 int sc_txdirty; /* first dirty Tx descriptor */ 140 141 int sc_rxptr; /* next ready Rx descriptor */ 142 143 krndsource_t rnd_source; 144 145 #ifdef AUMAC_EVENT_COUNTERS 146 struct evcnt sc_ev_txstall; /* Tx stalled */ 147 struct evcnt sc_ev_rxstall; /* Rx stalled */ 148 struct evcnt sc_ev_txintr; /* Tx interrupts */ 149 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 150 #endif 151 152 uint32_t sc_control; /* MAC_CONTROL contents */ 153 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 154 }; 155 156 #ifdef AUMAC_EVENT_COUNTERS 157 #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 158 #else 159 #define AUMAC_EVCNT_INCR(ev) /* nothing */ 160 #endif 161 162 #define AUMAC_INIT_RXDESC(sc, x) \ 163 do { \ 164 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 165 MACDMA_RX_STAT((x)), 0); \ 166 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 167 MACDMA_RX_ADDR((x)), \ 168 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 169 } while (/*CONSTCOND*/0) 170 171 static void aumac_start(struct ifnet *); 172 static void aumac_watchdog(struct ifnet *); 173 static int aumac_ioctl(struct ifnet *, u_long, void *); 174 static int aumac_init(struct ifnet *); 175 static void aumac_stop(struct ifnet *, int); 176 177 static void aumac_shutdown(void *); 178 179 static void aumac_tick(void *); 180 181 static void aumac_set_filter(struct aumac_softc *); 182 183 static void aumac_powerup(struct aumac_softc *); 184 static void aumac_powerdown(struct aumac_softc *); 185 186 static int aumac_intr(void *); 187 static int aumac_txintr(struct aumac_softc *); 188 static int aumac_rxintr(struct aumac_softc *); 189 190 static int aumac_mii_readreg(device_t, int, int, uint16_t *); 191 static int aumac_mii_writereg(device_t, int, int, uint16_t); 192 static void aumac_mii_statchg(struct ifnet *); 193 static int aumac_mii_wait(struct aumac_softc *, const char *); 194 195 static int aumac_match(device_t, struct cfdata *, void *); 196 static void aumac_attach(device_t, device_t, void *); 197 198 int aumac_copy_small = 0; 199 200 CFATTACH_DECL_NEW(aumac, sizeof(struct aumac_softc), 201 aumac_match, aumac_attach, NULL, NULL); 202 203 static int 204 aumac_match(device_t parent, struct cfdata *cf, void *aux) 205 { 206 struct aubus_attach_args *aa = aux; 207 208 if (strcmp(aa->aa_name, cf->cf_name) == 0) 209 return 1; 210 211 return 0; 212 } 213 214 static void 215 aumac_attach(device_t parent, device_t self, void *aux) 216 { 217 const uint8_t *enaddr; 218 prop_data_t ea; 219 struct aumac_softc *sc = device_private(self); 220 struct aubus_attach_args *aa = aux; 221 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 222 struct mii_data * const mii = &sc->sc_mii; 223 struct pglist pglist; 224 paddr_t bufaddr; 225 vaddr_t vbufaddr; 226 int i; 227 228 callout_init(&sc->sc_tick_ch, 0); 229 230 aprint_normal(": Au1X00 10/100 Ethernet\n"); 231 aprint_naive("\n"); 232 233 sc->sc_dev = self; 234 sc->sc_st = aa->aa_st; 235 236 /* Get the MAC address. */ 237 ea = prop_dictionary_get(device_properties(self), "mac-address"); 238 if (ea == NULL) { 239 aprint_error_dev(self, "unable to get mac-addr property\n"); 240 return; 241 } 242 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 243 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 244 enaddr = prop_data_data_nocopy(ea); 245 246 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 247 248 /* Map the device. */ 249 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 250 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 251 aprint_error_dev(self, "unable to map MAC registers\n"); 252 return; 253 } 254 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 255 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 256 aprint_error_dev(self, "unable to map MACEN registers\n"); 257 return; 258 } 259 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 260 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 261 aprint_error_dev(self, "unable to map MACDMA registers\n"); 262 return; 263 } 264 265 /* Make sure the MAC is powered off. */ 266 aumac_powerdown(sc); 267 268 /* Hook up the interrupt handler. */ 269 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 270 aumac_intr, sc); 271 if (sc->sc_ih == NULL) { 272 aprint_error_dev(self, 273 "unable to register interrupt handler\n"); 274 return; 275 } 276 sc->sc_irq = aa->aa_irq[0]; 277 au_intr_disable(sc->sc_irq); 278 279 /* 280 * Allocate space for the transmit and receive buffers. 281 */ 282 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 283 &pglist, 1, 0)) 284 return; 285 286 bufaddr = VM_PAGE_TO_PHYS(TAILQ_FIRST(&pglist)); 287 vbufaddr = MIPS_PHYS_TO_KSEG0(bufaddr); 288 289 for (i = 0; i < AUMAC_NTXDESC; i++) { 290 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 291 292 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 293 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 294 } 295 296 for (i = 0; i < AUMAC_NRXDESC; i++) { 297 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 298 299 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 300 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 301 } 302 303 /* 304 * Power up the MAC before accessing any MAC registers (including 305 * MII configuration. 306 */ 307 aumac_powerup(sc); 308 309 /* 310 * Initialize the media structures and probe the MII. 311 */ 312 mii->mii_ifp = ifp; 313 mii->mii_readreg = aumac_mii_readreg; 314 mii->mii_writereg = aumac_mii_writereg; 315 mii->mii_statchg = aumac_mii_statchg; 316 sc->sc_ethercom.ec_mii = mii; 317 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 318 319 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 320 MII_OFFSET_ANY, 0); 321 322 if (LIST_FIRST(&mii->mii_phys) == NULL) { 323 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 324 0, NULL); 325 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 326 } else 327 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 328 329 strcpy(ifp->if_xname, device_xname(self)); 330 ifp->if_softc = sc; 331 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 332 ifp->if_ioctl = aumac_ioctl; 333 ifp->if_start = aumac_start; 334 ifp->if_watchdog = aumac_watchdog; 335 ifp->if_init = aumac_init; 336 ifp->if_stop = aumac_stop; 337 IFQ_SET_READY(&ifp->if_snd); 338 339 /* Attach the interface. */ 340 if_attach(ifp); 341 if_deferred_start_init(ifp, NULL); 342 ether_ifattach(ifp, enaddr); 343 344 rnd_attach_source(&sc->rnd_source, device_xname(self), 345 RND_TYPE_NET, RND_FLAG_DEFAULT); 346 347 #ifdef AUMAC_EVENT_COUNTERS 348 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 349 NULL, device_xname(self), "txstall"); 350 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 351 NULL, device_xname(self), "rxstall"); 352 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 353 NULL, device_xname(self), "txintr"); 354 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 355 NULL, device_xname(self), "rxintr"); 356 #endif 357 358 /* Make sure the interface is shutdown during reboot. */ 359 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 360 if (sc->sc_sdhook == NULL) 361 aprint_error_dev(self, 362 "WARNING: unable to establish shutdown hook\n"); 363 return; 364 } 365 366 /* 367 * aumac_shutdown: 368 * 369 * Make sure the interface is stopped at reboot time. 370 */ 371 static void 372 aumac_shutdown(void *arg) 373 { 374 struct aumac_softc *sc = arg; 375 376 aumac_stop(&sc->sc_ethercom.ec_if, 1); 377 378 /* 379 * XXX aumac_stop leaves device powered up at the moment 380 * XXX but this still isn't enough to keep yamon happy... :-( 381 */ 382 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 383 } 384 385 /* 386 * aumac_start: [ifnet interface function] 387 * 388 * Start packet transmission on the interface. 389 */ 390 static void 391 aumac_start(struct ifnet *ifp) 392 { 393 struct aumac_softc *sc = ifp->if_softc; 394 struct mbuf *m; 395 int nexttx; 396 397 if ((ifp->if_flags & IFF_RUNNING) == 0) 398 return; 399 400 /* 401 * Loop through the send queue, setting up transmit descriptors 402 * unitl we drain the queue, or use up all available transmit 403 * descriptors. 404 */ 405 for (;;) { 406 /* Grab a packet off the queue. */ 407 IFQ_POLL(&ifp->if_snd, m); 408 if (m == NULL) 409 return; 410 411 /* Get a spare descriptor. */ 412 if (sc->sc_txfree == 0) { 413 /* No more slots left. */ 414 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 415 return; 416 } 417 nexttx = sc->sc_txnext; 418 419 IFQ_DEQUEUE(&ifp->if_snd, m); 420 421 /* 422 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 423 */ 424 425 m_copydata(m, 0, m->m_pkthdr.len, 426 (void *)sc->sc_txbufs[nexttx].buf_vaddr); 427 428 /* Zero out the remainder of any short packets. */ 429 if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 430 memset((char *)sc->sc_txbufs[nexttx].buf_vaddr + 431 m->m_pkthdr.len, 0, 432 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 433 434 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 435 MACDMA_TX_STAT(nexttx), 0); 436 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 437 MACDMA_TX_LEN(nexttx), 438 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 439 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 440 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 441 MACDMA_TX_ADDR(nexttx), 442 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 443 /* XXX - needed?? we should be coherent */ 444 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 445 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 446 447 /* Advance the Tx pointer. */ 448 sc->sc_txfree--; 449 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 450 451 /* Pass the packet to any BPF listeners. */ 452 bpf_mtap(ifp, m, BPF_D_OUT); 453 454 m_freem(m); 455 456 /* Set a watchdog timer in case the chip flakes out. */ 457 ifp->if_timer = 5; 458 } 459 /* NOTREACHED */ 460 } 461 462 /* 463 * aumac_watchdog: [ifnet interface function] 464 * 465 * Watchdog timer handler. 466 */ 467 static void 468 aumac_watchdog(struct ifnet *ifp) 469 { 470 struct aumac_softc *sc = ifp->if_softc; 471 472 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 473 (void) aumac_init(ifp); 474 475 /* Try to get more packets going. */ 476 aumac_start(ifp); 477 } 478 479 /* 480 * aumac_ioctl: [ifnet interface function] 481 * 482 * Handle control requests from the operator. 483 */ 484 static int 485 aumac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 486 { 487 struct aumac_softc *sc = ifp->if_softc; 488 int s, error; 489 490 s = splnet(); 491 492 error = ether_ioctl(ifp, cmd, data); 493 if (error == ENETRESET) { 494 /* 495 * Multicast list has changed; set the hardware filter 496 * accordingly. 497 */ 498 if (ifp->if_flags & IFF_RUNNING) 499 aumac_set_filter(sc); 500 error = 0; 501 } 502 503 /* Try to get more packets going. */ 504 aumac_start(ifp); 505 506 splx(s); 507 return error; 508 } 509 510 /* 511 * aumac_intr: 512 * 513 * Interrupt service routine. 514 */ 515 static int 516 aumac_intr(void *arg) 517 { 518 struct aumac_softc *sc = arg; 519 int status; 520 521 /* 522 * There aren't really any interrupt status bits on the 523 * Au1X00 MAC, and each MAC has a dedicated interrupt 524 * in the CPU's built-in interrupt controller. Just 525 * check for new incoming packets, and then Tx completions 526 * (for status updating). 527 */ 528 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 529 return 0; 530 531 status = aumac_rxintr(sc); 532 status += aumac_txintr(sc); 533 534 rnd_add_uint32(&sc->rnd_source, status); 535 536 return status; 537 } 538 539 /* 540 * aumac_txintr: 541 * 542 * Helper; handle transmit interrupts. 543 */ 544 static int 545 aumac_txintr(struct aumac_softc *sc) 546 { 547 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 548 uint32_t stat; 549 int i; 550 int pkts = 0; 551 552 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 553 i = AUMAC_NEXTTX(i)) { 554 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 555 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 556 break; 557 pkts++; 558 559 /* ACK interrupt. */ 560 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 561 MACDMA_TX_ADDR(i), 0); 562 563 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 564 MACDMA_TX_STAT(i)); 565 566 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 567 if (stat & TX_STAT_FA) { 568 /* XXX STATS */ 569 if_statinc_ref(ifp, nsr, if_oerrors); 570 } else { 571 if_statinc_ref(ifp, nsr, if_opackets); 572 } 573 574 if (stat & TX_STAT_EC) { 575 if_statadd_ref(ifp, nsr, if_collisions, 16); 576 } else if (TX_STAT_CC(stat)) { 577 if_statadd_ref(ifp, nsr, if_collisions, 578 TX_STAT_CC(stat)); 579 } 580 IF_STAT_PUTREF(ifp); 581 582 sc->sc_txfree++; 583 584 /* Try to queue more packets. */ 585 if_schedule_deferred_start(ifp); 586 } 587 588 if (pkts) 589 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 590 591 /* Update the dirty descriptor pointer. */ 592 sc->sc_txdirty = i; 593 594 /* 595 * If there are no more pending transmissions, cancel the watchdog 596 * timer. 597 */ 598 if (sc->sc_txfree == AUMAC_NTXDESC) 599 ifp->if_timer = 0; 600 601 return pkts; 602 } 603 604 /* 605 * aumac_rxintr: 606 * 607 * Helper; handle receive interrupts. 608 */ 609 static int 610 aumac_rxintr(struct aumac_softc *sc) 611 { 612 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 613 struct mbuf *m; 614 uint32_t stat; 615 int i, len; 616 int pkts = 0; 617 618 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 619 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 620 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 621 break; 622 pkts++; 623 624 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 625 MACDMA_RX_STAT(i)); 626 627 #define PRINTERR(str) \ 628 do { \ 629 error++; \ 630 printf("%s: %s\n", device_xname(sc->sc_dev), str); \ 631 } while (0) 632 633 if (stat & RX_STAT_ERRS) { 634 int error = 0; 635 636 #if 0 /* 637 * Missed frames are a semi-frequent occurrence with this hardware, 638 * and reporting of them just makes everything run slower and fills 639 * the system log. Be silent. 640 * 641 * Additionally, this missed bit indicates an error with the previous 642 * packet, and not with this one! So PRINTERR is definitely wrong 643 * here. 644 * 645 * These should probably all be converted to evcnt counters anyway. 646 */ 647 if (stat & RX_STAT_MI) 648 PRINTERR("missed frame"); 649 #endif 650 if (stat & RX_STAT_UC) 651 PRINTERR("unknown control frame"); 652 if (stat & RX_STAT_LE) 653 PRINTERR("short frame"); 654 if (stat & RX_STAT_CR) 655 PRINTERR("CRC error"); 656 if (stat & RX_STAT_ME) 657 PRINTERR("medium error"); 658 if (stat & RX_STAT_CS) 659 PRINTERR("late collision"); 660 if (stat & RX_STAT_FL) 661 PRINTERR("frame too big"); 662 if (stat & RX_STAT_RF) 663 PRINTERR("runt frame (collision)"); 664 if (stat & RX_STAT_WT) 665 PRINTERR("watch dog"); 666 if (stat & RX_STAT_DB) { 667 if (stat & (RX_STAT_CS | RX_STAT_RF | 668 RX_STAT_CR)) { 669 if (!error) 670 goto pktok; 671 } else 672 PRINTERR("dribbling bit"); 673 } 674 #undef PRINTERR 675 if_statinc(ifp, if_ierrors); 676 677 dropit: 678 /* reuse the current descriptor */ 679 AUMAC_INIT_RXDESC(sc, i); 680 continue; 681 } 682 pktok: 683 len = RX_STAT_L(stat); 684 685 /* 686 * The Au1X00 MAC includes the CRC with every packet; 687 * trim it off here. 688 */ 689 len -= ETHER_CRC_LEN; 690 691 /* 692 * Truncate the packet if it's too big to fit in 693 * a single mbuf cluster. 694 */ 695 if (len > MCLBYTES - 2) 696 len = MCLBYTES - 2; 697 698 MGETHDR(m, M_DONTWAIT, MT_DATA); 699 if (m == NULL) { 700 printf("%s: unable to allocate Rx mbuf\n", 701 device_xname(sc->sc_dev)); 702 goto dropit; 703 } 704 if (len > MHLEN - 2) { 705 MCLGET(m, M_DONTWAIT); 706 if ((m->m_flags & M_EXT) == 0) { 707 printf("%s: unable to allocate Rx cluster\n", 708 device_xname(sc->sc_dev)); 709 m_freem(m); 710 goto dropit; 711 } 712 } 713 714 m->m_data += 2; /* align payload */ 715 memcpy(mtod(m, void *), 716 (void *)sc->sc_rxbufs[i].buf_vaddr, len); 717 AUMAC_INIT_RXDESC(sc, i); 718 719 m_set_rcvif(m, ifp); 720 m->m_pkthdr.len = m->m_len = len; 721 722 /* Pass it on. */ 723 if_percpuq_enqueue(ifp->if_percpuq, m); 724 } 725 if (pkts) 726 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 727 if (pkts == AUMAC_NRXDESC) 728 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 729 730 /* Update the receive pointer. */ 731 sc->sc_rxptr = i; 732 733 return pkts; 734 } 735 736 /* 737 * aumac_tick: 738 * 739 * One second timer, used to tick the MII. 740 */ 741 static void 742 aumac_tick(void *arg) 743 { 744 struct aumac_softc *sc = arg; 745 int s; 746 747 s = splnet(); 748 mii_tick(&sc->sc_mii); 749 splx(s); 750 751 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 752 } 753 754 /* 755 * aumac_init: [ifnet interface function] 756 * 757 * Initialize the interface. Must be called at splnet(). 758 */ 759 static int 760 aumac_init(struct ifnet *ifp) 761 { 762 struct aumac_softc *sc = ifp->if_softc; 763 int i, error = 0; 764 765 /* Cancel any pending I/O, reset MAC. */ 766 aumac_stop(ifp, 0); 767 768 /* Set up the transmit ring. */ 769 for (i = 0; i < AUMAC_NTXDESC; i++) { 770 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 771 MACDMA_TX_STAT(i), 0); 772 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 773 MACDMA_TX_LEN(i), 0); 774 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 775 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 776 } 777 sc->sc_txfree = AUMAC_NTXDESC; 778 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 779 MACDMA_TX_ADDR(0))); 780 sc->sc_txdirty = sc->sc_txnext; 781 782 /* Set up the receive ring. */ 783 for (i = 0; i < AUMAC_NRXDESC; i++) 784 AUMAC_INIT_RXDESC(sc, i); 785 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 786 MACDMA_RX_ADDR(0))); 787 788 /* 789 * Power up the MAC. 790 */ 791 aumac_powerup(sc); 792 793 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 794 #if _BYTE_ORDER == _BIG_ENDIAN 795 sc->sc_control |= CONTROL_EM; 796 #endif 797 798 /* Set the media. */ 799 if ((error = ether_mediachange(ifp)) != 0) 800 goto out; 801 802 /* 803 * Set the receive filter. This will actually start the transmit 804 * and receive processes. 805 */ 806 aumac_set_filter(sc); 807 808 /* Start the one second clock. */ 809 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 810 811 /* ...all done! */ 812 ifp->if_flags |= IFF_RUNNING; 813 814 au_intr_enable(sc->sc_irq); 815 out: 816 if (error) 817 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 818 return error; 819 } 820 821 /* 822 * aumac_stop: [ifnet interface function] 823 * 824 * Stop transmission on the interface. 825 */ 826 static void 827 aumac_stop(struct ifnet *ifp, int disable) 828 { 829 struct aumac_softc *sc = ifp->if_softc; 830 831 /* Stop the one-second clock. */ 832 callout_stop(&sc->sc_tick_ch); 833 834 /* Down the MII. */ 835 mii_down(&sc->sc_mii); 836 837 /* Stop the transmit and receive processes. */ 838 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 839 840 /* Power down/reset the MAC. */ 841 aumac_powerdown(sc); 842 843 au_intr_disable(sc->sc_irq); 844 845 /* Mark the interface as down and cancel the watchdog timer. */ 846 ifp->if_flags &= ~IFF_RUNNING; 847 ifp->if_timer = 0; 848 } 849 850 /* 851 * aumac_powerdown: 852 * 853 * Power down the MAC. 854 */ 855 static void 856 aumac_powerdown(struct aumac_softc *sc) 857 { 858 859 /* Disable the MAC clocks, and place the device in reset. */ 860 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 861 862 // delay(10000); 863 } 864 865 /* 866 * aumac_powerup: 867 * 868 * Bring the device out of reset. 869 */ 870 static void 871 aumac_powerup(struct aumac_softc *sc) 872 { 873 874 /* Enable clocks to the MAC. */ 875 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP | MACEN_CE); 876 877 /* Enable MAC, coherent transactions, pass only valid frames. */ 878 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 879 MACEN_E2 | MACEN_E1 | MACEN_E0 | MACEN_CE); 880 881 delay(20000); 882 } 883 884 /* 885 * aumac_set_filter: 886 * 887 * Set up the receive filter. 888 */ 889 static void 890 aumac_set_filter(struct aumac_softc *sc) 891 { 892 struct ethercom *ec = &sc->sc_ethercom; 893 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 894 struct ether_multi *enm; 895 struct ether_multistep step; 896 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 897 uint32_t mchash[2], crc; 898 899 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 900 901 /* Stop the receiver. */ 902 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 903 sc->sc_control & ~CONTROL_RE); 904 905 if (ifp->if_flags & IFF_PROMISC) { 906 sc->sc_control |= CONTROL_PR; 907 goto allmulti; 908 } 909 910 /* Set the station address. */ 911 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 912 enaddr[4] | (enaddr[5] << 8)); 913 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 914 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 915 (enaddr[3] << 24)); 916 917 sc->sc_control |= CONTROL_HP; 918 919 mchash[0] = mchash[1] = 0; 920 921 /* 922 * Set up the multicast address filter by passing all multicast 923 * addresses through a CRC generator, and then using the high 924 * order 6 bits as an index into the 64-bit multicast hash table. 925 * The high order bits select the word, while the rest of the bits 926 * select the bit within the word. 927 */ 928 ETHER_LOCK(ec); 929 ETHER_FIRST_MULTI(step, ec, enm); 930 while (enm != NULL) { 931 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 932 /* 933 * We must listen to a range of multicast addresses. 934 * For now, just accept all multicasts, rather than 935 * trying to set only those filter bits needed to match 936 * the range. (At this time, the only use of address 937 * ranges is for IP multicast routing, for which the 938 * range is large enough to require all bits set.) 939 */ 940 ETHER_UNLOCK(ec); 941 goto allmulti; 942 } 943 944 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 945 946 /* Just want the 6 most significant bits. */ 947 crc >>= 26; 948 949 /* Set the corresponding bit in the filter. */ 950 mchash[crc >> 5] |= 1U << (crc & 0x1f); 951 952 ETHER_NEXT_MULTI(step, enm); 953 } 954 ETHER_UNLOCK(ec); 955 956 ifp->if_flags &= ~IFF_ALLMULTI; 957 958 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 959 mchash[1]); 960 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 961 mchash[0]); 962 963 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 964 sc->sc_control); 965 return; 966 967 allmulti: 968 sc->sc_control |= CONTROL_PM; 969 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 970 sc->sc_control); 971 } 972 973 /* 974 * aumac_mii_wait: 975 * 976 * Wait for the MII interface to not be busy. 977 */ 978 static int 979 aumac_mii_wait(struct aumac_softc *sc, const char *msg) 980 { 981 int i; 982 983 for (i = 0; i < 10000; i++) { 984 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 985 MAC_MIICTRL) & MIICTRL_MB) == 0) 986 return 0; 987 delay(10); 988 } 989 990 printf("%s: MII failed to %s\n", device_xname(sc->sc_dev), msg); 991 return ETIMEDOUT; 992 } 993 994 /* 995 * aumac_mii_readreg: [mii interface function] 996 * 997 * Read a PHY register on the MII. 998 */ 999 static int 1000 aumac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1001 { 1002 struct aumac_softc *sc = device_private(self); 1003 int rv; 1004 1005 if ((rv = aumac_mii_wait(sc, "become ready")) != 0) 1006 return rv; 1007 1008 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1009 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1010 1011 if ((rv = aumac_mii_wait(sc, "complete")) != 0) 1012 return rv; 1013 1014 *val = bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) 1015 & MIIDATA_MASK; 1016 return 0; 1017 } 1018 1019 /* 1020 * aumac_mii_writereg: [mii interface function] 1021 * 1022 * Write a PHY register on the MII. 1023 */ 1024 static int 1025 aumac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1026 { 1027 struct aumac_softc *sc = device_private(self); 1028 int rv; 1029 1030 if ((rv = aumac_mii_wait(sc, "become ready")) != 0) 1031 return rv; 1032 1033 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1034 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1035 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1036 1037 return aumac_mii_wait(sc, "complete"); 1038 } 1039 1040 /* 1041 * aumac_mii_statchg: [mii interface function] 1042 * 1043 * Callback from MII layer when media changes. 1044 */ 1045 static void 1046 aumac_mii_statchg(struct ifnet *ifp) 1047 { 1048 struct aumac_softc *sc = ifp->if_softc; 1049 1050 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1051 sc->sc_control |= CONTROL_F; 1052 else 1053 sc->sc_control &= ~CONTROL_F; 1054 1055 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1056 sc->sc_control); 1057 } 1058
Indexes created Mon Sep 22 05:09:51 GMT 2025