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      1 /*	$NetBSD: sbbuswatch.c,v 1.4 2017/07/24 09:56:46 mrg Exp $	*/
      2 /*
      3  * Copyright (c) 2010, The NetBSD Foundation, Inc.  All rights reserved.
      4  *
      5  * This code is derived from software contributed to The NetBSD Foundation
      6  * by Cliff Neighbors.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     19  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     20  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     21  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     27  * POSSIBILITY OF SUCH DAMAGE.
     28  */
     29 
     30 #include <sys/param.h>
     31 #include <sys/systm.h>
     32 #include <sys/cpu.h>
     33 
     34 #include <mips/cpu.h>
     35 #include <mips/locore.h>
     36 
     37 #include <mips/sibyte/include/sb1250_int.h>
     38 #include <mips/sibyte/include/sb1250_regs.h>
     39 #include <mips/sibyte/dev/sbbuswatchvar.h>
     40 
     41 #include <evbmips/sbmips/systemsw.h>
     42 
     43 #define READ_REG(rp)            mips3_ld((register_t)(rp))
     44 #define WRITE_REG(rp, val)      mips3_sd((register_t)(rp), (val))
     45 
     46 static void sibyte_bus_watch_intr(void *, uint32_t, vaddr_t);
     47 
     48 void
     49 sibyte_bus_watch_init(void)
     50 {
     51 	(void)READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
     52 	WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
     53 	WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
     54 
     55 	(void)cpu_intr_establish(K_INT_BAD_ECC, IPL_DDB,
     56 		sibyte_bus_watch_intr, (void *)K_INT_BAD_ECC);
     57 	(void)cpu_intr_establish(K_INT_COR_ECC, IPL_DDB,
     58 		sibyte_bus_watch_intr, (void *)K_INT_COR_ECC);
     59 	(void)cpu_intr_establish(K_INT_IO_BUS, IPL_DDB,
     60 		sibyte_bus_watch_intr, (void *)K_INT_IO_BUS);
     61 }
     62 
     63 int
     64 sibyte_bus_watch_check(unsigned int cause)
     65 {
     66 	uint64_t err_ctl;
     67 	uint64_t cache_err_i;
     68 	uint64_t cache_err_d;
     69 	uint64_t cache_err_dpa;
     70 	uint64_t bus_err_dpa;
     71 	uint32_t bus_err_status;
     72 	uint32_t l2_errors;
     73 	uint32_t mem_io_errors;
     74 
     75 	bus_err_status = READ_REG(
     76 		MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
     77 
     78 	if (bus_err_status == 0)
     79 		return 0;
     80 
     81 	l2_errors = READ_REG(
     82 		MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS));
     83 	if (l2_errors != 0)
     84 		WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
     85 
     86 	mem_io_errors = READ_REG(
     87 		MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS));
     88 	if (mem_io_errors != 0)
     89 		WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
     90 
     91 	asm volatile("dmfc0 %0, $26, 0;" : "=r"(err_ctl));
     92 	asm volatile("dmfc0 %0, $26, 1;" : "=r"(bus_err_dpa));
     93 	asm volatile("dmfc0 %0, $27, 0;" : "=r"(cache_err_i));
     94 	asm volatile("dmfc0 %0, $27, 1;" : "=r"(cache_err_d));
     95 	asm volatile("dmfc0 %0, $27, 3;" : "=r"(cache_err_dpa));
     96 
     97 	printf("bus_err_status=%#x\n", bus_err_status);
     98 	printf("l2_errors=%#x\n", l2_errors);
     99 	printf("mem_io_errors=%#x\n", mem_io_errors);
    100 	printf("err_ctl=%#"PRIx64"\n", err_ctl);
    101 	printf("bus_err_dpa=%#"PRIx64"\n", bus_err_dpa);
    102 	printf("cache_err_i=%#"PRIx64"\n", cache_err_i);
    103 	printf("cache_err_d=%#"PRIx64"\n", cache_err_d);
    104 	printf("cache_err_dpa=%#"PRIx64"\n", cache_err_dpa);
    105 
    106 	return -1;
    107 }
    108 
    109 static void
    110 sibyte_bus_watch_intr(void *arg, uint32_t status, vaddr_t pc)
    111 {
    112 	printf("%s: %p\n", __func__, arg);
    113 	(void)sibyte_bus_watch_check(0);
    114 }
    115