| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_fb.c | 144 u32 tiling_flags = 0, domain; local
173 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
179 if (tiling_flags) {
181 tiling_flags);
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| amdgpu_display.c | 166 u64 tiling_flags; local
221 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
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| amdgpu_object.h | 95 u64 tiling_flags; member in struct:amdgpu_bo
270 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
271 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
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| amdgpu_dce_v10_0.c | 1862 uint64_t fb_location, tiling_flags; local
1900 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1903 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1997 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1998 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1999 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2000 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1)
[all...] |
| amdgpu_dce_v11_0.c | 1904 uint64_t fb_location, tiling_flags; local
1942 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1945 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2035 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2038 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2039 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2040 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2041 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2042 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2055 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1)
[all...] |
| amdgpu_dce_v6_0.c | 1822 uint64_t fb_location, tiling_flags; local
1859 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1942 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1945 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1946 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1947 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1948 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1949 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1957 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1961 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG)
[all...] |
| amdgpu_dce_v8_0.c | 1791 uint64_t fb_location, tiling_flags; local
1829 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1832 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1914 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1917 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1918 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1919 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1920 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1921 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1930 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_fb.c | 147 u32 tiling_flags = 0; local
174 tiling_flags = RADEON_TILING_MACRO;
179 tiling_flags |= RADEON_TILING_SWAP_32BIT;
182 tiling_flags |= RADEON_TILING_SWAP_16BIT;
188 if (tiling_flags) {
190 tiling_flags | RADEON_TILING_SURFACE,
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| radeon_legacy_crtc.c | 391 uint32_t tiling_flags; local
438 tiling_flags = 0;
479 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
482 if (tiling_flags & RADEON_TILING_MICRO)
499 if (tiling_flags & RADEON_TILING_MACRO) {
515 if (tiling_flags & RADEON_TILING_MACRO) {
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| radeon_atombios_crtc.c | 1160 uint32_t fb_format, fb_pitch_pixels, tiling_flags; local
1188 tiling_flags = 0;
1198 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1282 if (tiling_flags & RADEON_TILING_MACRO) {
1283 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1356 } else if (tiling_flags & RADEON_TILING_MICRO)
1483 uint32_t fb_format, fb_pitch_pixels, tiling_flags; local
1510 tiling_flags = 0;
1520 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1597 if (tiling_flags & RADEON_TILING_MACRO
[all...] |
| radeon_display.c | 498 uint32_t tiling_flags, pitch_pixels; local
544 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
552 if (tiling_flags & RADEON_TILING_MACRO) {
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| radeon.h | 368 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
483 uint32_t tiling_flags; member in struct:radeon_bo_list
515 u32 tiling_flags; member in struct:radeon_bo
1982 uint32_t tiling_flags, uint32_t pitch,
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| /src/sys/external/bsd/drm2/dist/include/uapi/drm/ |
| radeon_drm.h | 860 __u32 tiling_flags; member in struct:drm_radeon_gem_set_tiling
866 __u32 tiling_flags; member in struct:drm_radeon_gem_get_tiling
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