1 /* $NetBSD: armadaxp_start.S,v 1.5 2018/10/15 16:54:54 skrll Exp $ */ 2 /******************************************************************************* 3 Copyright (C) Marvell International Ltd. and its affiliates 4 5 Developed by Semihalf 6 7 ******************************************************************************** 8 Marvell BSD License 9 10 If you received this File from Marvell, you may opt to use, redistribute and/or 11 modify this File under the following licensing terms. 12 Redistribution and use in source and binary forms, with or without modification, 13 are permitted provided that the following conditions are met: 14 15 * Redistributions of source code must retain the above copyright notice, 16 this list of conditions and the following disclaimer. 17 18 * Redistributions in binary form must reproduce the above copyright 19 notice, this list of conditions and the following disclaimer in the 20 documentation and/or other materials provided with the distribution. 21 22 * Neither the name of Marvell nor the names of its contributors may be 23 used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 27 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 29 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 30 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 32 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 33 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 37 *******************************************************************************/ 38 39 #include "opt_cputypes.h" 40 41 #include <machine/asm.h> 42 #include <arm/armreg.h> 43 #include <evbarm/marvell/marvellreg.h> 44 #include <evbarm/marvell/marvellvar.h> 45 #include "assym.h" 46 47 RCSID("$NetBSD: armadaxp_start.S,v 1.5 2018/10/15 16:54:54 skrll Exp $") 48 49 #ifdef KERNEL_BASES_EQUAL 50 #error KERNEL_BASE_VIRT should not equal KERNEL_BASE_PHYS 51 #endif 52 53 /* 54 * We don't want to hard-code some basic things like RAM start etc. 55 * Hence, it is important to set the following options to resanoable values 56 * in std.armadaxp configuration file. 57 */ 58 #if !defined(STARTUP_PAGETABLE_ADDR) 59 #error STARTUP_PAGETABLE_ADDR not defined. Please define it in std.armadaxp 60 #elif !defined(MEMSTART) 61 #error MEMSTART not defined. Please define it in std.armadaxp 62 #endif 63 64 .section .start,"ax",%progbits 65 66 .global _C_LABEL(armadaxp_start) 67 _C_LABEL(armadaxp_start): 68 /* Move into supervisor mode and disable IRQs/FIQs. */ 69 cpsid if, #PSR_SVC32_MODE 70 71 /* Disable MMU for a while */ 72 mrc p15, 0, r2, c1, c0, 0 73 movw r1, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\ 74 CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_IC_ENABLE |\ 75 CPU_CONTROL_BPRD_ENABLE) 76 bic r2, r2, r1 77 mcr p15, 0, r2, c1, c0, 0 78 dsb 79 isb 80 81 /* Save U-Boot arguments */ 82 adr r4, uboot_regs_pa 83 stmia r4!, {r0, r1, r2, r3} 84 85 /* build page table from scratch */ 86 movw r0, #:lower16:STARTUP_PAGETABLE_ADDR 87 movt r0, #:upper16:STARTUP_PAGETABLE_ADDR 88 adr r4, mmu_init_table 89 b 3f 90 91 2: str r3, [r0, r2] 92 add r2, r2, #4 93 add r3, r3, #(L1_S_SIZE) 94 adds r1, r1, #-1 95 bhi 2b 96 3: 97 ldmia r4!, {r1,r2,r3} /* # of sections, VA, PA|attr */ 98 cmp r1, #0 99 bne 2b 100 101 mcr p15, 0, r0, c2, c0, 0 // Set TTBR0 102 #ifdef ARM_MMU_EXTENDED 103 mcr p15, 0, r0, c2, c0, 1 // Set TTBR1 104 mov r0, #TTBCR_S_N_1 105 #else 106 mov r0, #0 107 #endif 108 mcr p15, 0, r0, c2, c0, 2 // TTBCR write 109 110 mov r0, #0 111 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 112 113 mcr p15, 0, r0, c13, c0, 1 // CONTEXTIDR write: Set ASID to 0 114 115 /* Set the Domain Access register. Very important! */ 116 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 117 mcr p15, 0, r0, c3, c0, 0 // DACR write 118 119 #define CPU_CONTROL_SET (CPU_CONTROL_XP_ENABLE | CPU_CONTROL_IC_ENABLE \ 120 | CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE) 121 122 /* Enable MMU */ 123 mrc p15, 0, r0, c1, c0, 0 124 movw r1, #:lower16:CPU_CONTROL_SET 125 #if (CPU_CONTROL_SET & 0xffff) != 0 126 movt r1, #:upper16:CPU_CONTROL_SET 127 #endif 128 orr r0, r0, r1 129 mcr p15, 0, r0, c1, c0, 0 130 isb 131 dsb 132 133 /* Jump to kernel code in TRUE VA */ 134 movw ip, #:lower16:start 135 movt ip, #:upper16:start 136 bx ip 137 138 /* NOTREACHED */ 139 140 .global _C_LABEL(uboot_regs_pa) 141 uboot_regs_pa: 142 .space 16 /* r0, r1, r2, r3 */ 143 144 #define MMU_INIT(va,pa,n_sec,attr) \ 145 .word n_sec ; \ 146 .word 4*((va & 0xffffffff)>>L1_S_SHIFT) ; \ 147 .word (pa & 0xfffff000)|(attr) ; 148 149 mmu_init_table: 150 /* fill all table VA==PA */ 151 /* map SDRAM VA==PA, WT cacheable */ 152 MMU_INIT(MEMSTART, MEMSTART, 64, L1_TYPE_S|L1_S_C|L1_S_AP_KRW) 153 154 /* map VA 0x80000000..0x83ffffff to PA */ 155 MMU_INIT(KERNEL_BASE, MEMSTART, 64, L1_TYPE_S|L1_S_C|L1_S_AP_KRW) 156 157 /* 158 * In case of early start debugging it might be useful to map 159 * SoC registers (for UART access). 160 */ 161 MMU_INIT(MARVELL_INTERREGS_PBASE, MARVELL_INTERREGS_PBASE, 1, 162 L1_TYPE_S|L1_S_PROTO|L1_S_AP_KRW) 163 MMU_INIT(MARVELL_INTERREGS_VBASE, MARVELL_INTERREGS_PBASE, 1, 164 L1_TYPE_S|L1_S_PROTO|L1_S_AP_KRW) 165 166 /* end of table */ 167 MMU_INIT(0, 0, 0, 0) 168
Indexes created Tue Oct 14 15:09:51 GMT 2025