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      1 /*	$NetBSD: wired_map.h,v 1.5 2024/06/02 12:11:36 andvar Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2005 Tadpole Computer Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Garrett D'Amore for Tadpole Computer Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. The name of Tadpole Computer Inc. may not be used to endorse
     18  *    or promote products derived from this software without specific
     19  *    prior written permission.
     20  *
     21  * THIS SOFTWARE IS PROVIDED BY TADPOLE COMPUTER INC. ``AS IS'' AND
     22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     24  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL TADPOLE COMPUTER INC.
     25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     31  * POSSIBILITY OF SUCH DAMAGE.
     32  */
     33 
     34 #ifndef _MIPS_WIRED_MAP_H
     35 #define	_MIPS_WIRED_MAP_H
     36 
     37 /*
     38  * Certain machines have peripheral busses which are only accessible
     39  * using the TLB.
     40  *
     41  * For example, certain Alchemy parts place PCI and PCMCIA busses at
     42  * physical address spaces which are beyond the normal 32-bit range.
     43  * In order to access these spaces TLB entries mapping 36-bit physical
     44  * addresses to 32-bit logical addresses must be used.
     45  *
     46  * Note that all wired mappings are must be 32 MB aligned.  This is
     47  * because we use 32 MB mappings in the TLB.  Changing this might get
     48  * us more efficient use of the address space, but it would greatly
     49  * complicate the code, and would also probably consume additional TLB
     50  * entries.
     51  *
     52  * Note that within a single 32 MB region, you can have multiple
     53  * decoders, but they must decode uniquely within the same 32MB of
     54  * physical address space.
     55  *
     56  * BEWARE: The start of KSEG2 (0xC0000000) is used by the NetBSD kernel
     57  * for context switching and is associated with wired entry 0.  So you
     58  * cannot use that, as I discovered the hard way.
     59  *
     60  * Note also that at the moment this is not supported on the MIPS-I
     61  * ISA (but it shouldn't need it anyway.)
     62  */
     63 
     64 #ifndef MIPS3_WIRED_SIZE
     65 #define	MIPS3_WIRED_SIZE	MIPS3_PG_SIZE_MASK_TO_SIZE(MIPS3_PG_SIZE_16M)
     66 #endif
     67 #define	MIPS3_WIRED_OFFMASK	(MIPS3_WIRED_SIZE - 1)
     68 
     69 #define	MIPS3_WIRED_ENTRY_SIZE(pgsize)	((pgsize) * 2)
     70 #define	MIPS3_WIRED_ENTRY_OFFMASK(pgsize) (MIPS3_WIRED_ENTRY_SIZE(pgsize) - 1)
     71 
     72 /*
     73  * This defines the maximum number of wired TLB entries that the wired
     74  * map will be allowed to consume.  It can (and probably will!)
     75  * consume fewer, but it will not consume more.  Note that NetBSD also
     76  * uses one wired entry for context switching (see TLB_WIRED_UPAGES),
     77  * and that is not included in this number.
     78  */
     79 #ifndef MIPS3_NWIRED_ENTRY
     80 #define	MIPS3_NWIRED_ENTRY	8	/* upper limit */
     81 #endif
     82 
     83 struct wired_map_entry {
     84 	paddr_t	pa0;
     85 	paddr_t	pa1;
     86 	vaddr_t	va;
     87 	vsize_t	pgmask;
     88 };
     89 
     90 extern struct wired_map_entry mips3_wired_map[];
     91 extern int mips3_nwired_page;
     92 
     93 /*
     94  * Wire down a region of the specified size.
     95  */
     96 bool	mips3_wired_enter_region(vaddr_t, paddr_t, vsize_t);
     97 
     98 /*
     99  * Wire down a single page using specified page size.
    100  */
    101 bool	mips3_wired_enter_page(vaddr_t, paddr_t, vsize_t);
    102 
    103 #endif	/* _MIPS_WIRED_MAP_H */
    104