| /src/crypto/external/apache2/openssl/dist/crypto/sha/asm/ |
| sha256-riscv64-zvkb-zvknha_or_zvknhb.pl | 63 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
175 @{[vadd_vv $V5, $V10, $V1]}
176 @{[vsha2cl_vv $V7, $V6, $V5]}
177 @{[vsha2ch_vv $V6, $V7, $V5]}
178 @{[vmerge_vvm $V5, $V3, $V2, $V0]}
179 @{[vsha2ms_vv $V1, $V5, $V4]} # Generate W[19:16]
182 @{[vadd_vv $V5, $V11, $V2]}
183 @{[vsha2cl_vv $V7, $V6, $V5]}
184 @{[vsha2ch_vv $V6, $V7, $V5]}
185 @{[vmerge_vvm $V5, $V4, $V3, $V0]
[all...] |
| sha512-riscv64-zvkb-zvknhb.pl | 63 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
|
| /src/crypto/external/apache2/openssl/dist/crypto/modes/asm/ |
| ghash-riscv64-zvkb-zvbc.pl | 69 my ($V0,$V1,$V2,$V3,$V4,$V5,$V6) = ("v0","v1","v2","v3","v4","v5","v6");
125 my ($V0,$V1,$V2,$V3,$V4,$V5,$V6) = ("v0","v1","v2","v3","v4","v5","v6");
146 @{[vlse64_v $V5, $Xi, $TMP4]} # vlse64.v v5, (a0), t4
147 @{[vrev8_v $V5, $V5]} # vrev8.v v5, v5
[all...] |
| aes-gcm-riscv64-zvkb-zvkg-zvkned.pl | 89 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
103 @{[vaesem_vs $V28, $V5]}
135 @{[vaesem_vs $V28, $V5]}
179 @{[vaesem_vs $V28, $V5]}
253 @{[vle32_v $V5, $KEYP]}
308 @{[vle32_v $V5, $TMP_REG]}
366 @{[vle32_v $V5, $TMP_REG]}
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonDepArch.h | 24 enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67, V68 };
29 static constexpr StringLiteral ArchValsTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v68" };
35 static constexpr StringLiteral CpuNickTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v67t", "v68" };
39 {"generic", Hexagon::ArchEnum::V5},
40 {"hexagonv5", Hexagon::ArchEnum::V5},
64 {llvm::ELF::EF_HEXAGON_MACH_V5, "V5"},
|
| HexagonSubtarget.h | 141 return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
144 return getHexagonArchVersion() == Hexagon::ArchEnum::V5;
|
| HexagonRegisterInfo.cpp | 81 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
|
| /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.base/ |
| max-depth.c | 222 struct V5 : virtual V2 { int v5 = 1; } v5; variable in typeref:struct:V2
224 struct V7 : virtual V4, virtual V5, virtual V6 { int v7 = 1; } v7;
|
| /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.base/ |
| max-depth.c | 222 struct V5 : virtual V2 { int v5 = 1; } v5; variable in typeref:struct:V2
224 struct V7 : virtual V4, virtual V5, virtual V6 { int v7 = 1; } v7;
|
| /src/crypto/external/apache2/openssl/dist/crypto/aes/asm/ |
| aes-riscv64-zvkb-zvkned.pl | 74 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
152 @{[vle32_v $V5, $KEYP]}
190 @{[vaesem_vs $V24, $V5]}
224 @{[vle32_v $V5, $KEYP]}
266 @{[vaesem_vs $V24, $V5]}
302 @{[vle32_v $V5, $KEYP]}
348 @{[vaesem_vs $V24, $V5]}
|
| aes-riscv64-zvbb-zvkg-zvkned.pl | 76 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
283 @{[vle32_v $V5, $KEY1]}
313 @{[vle32_v $V5, $KEY1]}
346 @{[vaesem_vs $V24, $V5]}
367 @{[vaesdm_vs $V24, $V5]}
384 @{[vaesem_vs $V24, $V5]}
413 @{[vaesdm_vs $V24, $V5]}
|
| aes-riscv64-zvkned.pl | 61 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
81 @{[vle32_v $V5, $KEYP]}
113 @{[vle32_v $V5, $KEYP]}
149 @{[vle32_v $V5, $KEYP]}
182 @{[vaesem_vs $V24, $V5]} # with round key w[16,19]
203 @{[vaesdm_vs $V24, $V5]} # with round key w[16,19]
220 @{[vaesem_vs $V24, $V5]} # with round key w[16,19]
245 @{[vaesdm_vs $V24, $V5]} # with round key w[16,19]
262 @{[vaesem_vs $V24, $V5]} # with round key w[16,19]
291 @{[vaesdm_vs $V24, $V5]} # with round key w[16,19
[all...] |
| /src/crypto/external/apache2/openssl/dist/crypto/chacha/asm/ |
| chacha-riscv64-v-zbb.pl | 92 $V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7, $V8, $V9, $V10,
297 @{[vmv_v_x $V5, $KEY1]}
339 $V1, $V5, $V9, $V13,
349 $V0, $V5, $V10, $V15,
389 @{[vadd_vx $V5, $V5, $T1]}
411 @{[vxor_vv $V21, $V21, $V5]}
|
| /src/crypto/external/apache2/openssl/dist/crypto/sm3/asm/ |
| sm3-riscv64-zvksh.pl | 67 my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
|
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| cpustate.h | 97 V5,
|
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| cpustate.h | 97 V5,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCTargetDesc.cpp | 104 SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7,
|
| /src/sys/external/bsd/acpica/dist/tools/examples/ |
| extables.c | 347 CMOS RTC Not Present (V5) : 0
370 Hardware Reduced (V5) : 0
371 Low Power S0 Idle (V5) : 0
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCTargetDesc.cpp | 65 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
353 case Hexagon::ArchEnum::V5:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 578 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/Disassembler/ |
| VEDisassembler.cpp | 99 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 4233 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4701 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5935 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
6536 PPC::V2, PPC::V3, PPC::V4, PPC::V5,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 8168 .Case("{v5}", RISCV::V5)
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-arm.c | 9282 /* ARM V5 breakpoint instruction (argument parse)
9342 /* ARM V5 branch-link-exchange instruction (argument parse)
11891 /* ARM V5 Thumb BLX (argument parse)
23442 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23471 /* Arm mode bx is marked as both v4T and v5 because it's still required
23472 on a hypothetical non-thumb v5 core. */
23660 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
23664 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
24401 /* Note: bx (and blx) are required on V5, even if the processor does
30670 /* For V5 or later processors we default to using VFP; but the use
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-arm.c | 9285 /* ARM V5 breakpoint instruction (argument parse)
9345 /* ARM V5 branch-link-exchange instruction (argument parse)
11894 /* ARM V5 Thumb BLX (argument parse)
23445 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23474 /* Arm mode bx is marked as both v4T and v5 because it's still required
23475 on a hypothetical non-thumb v5 core. */
23663 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
23667 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
24404 /* Note: bx (and blx) are required on V5, even if the processor does
30677 /* For V5 or later processors we default to using VFP; but the use
[all...] |
