| /src/crypto/external/apache2/openssl/dist/crypto/bn/asm/ |
| armv4-mont.pl | 306 my @ACC=map("q$_",(6..13));
342 vmull.u32 @ACC[0],$Bi,${A0}[0]
343 vmull.u32 @ACC[1],$Bi,${A0}[1]
344 vmull.u32 @ACC[2],$Bi,${A1}[0]
345 vshl.i64 $Ni,@ACC[0]#hi,#16
346 vmull.u32 @ACC[3],$Bi,${A1}[1]
348 vadd.u64 $Ni,$Ni,@ACC[0]#lo
352 vmull.u32 @ACC[4],$Bi,${A2}[0]
354 vmull.u32 @ACC[5],$Bi,${A2}[1]
355 vmull.u32 @ACC[6],$Bi,${A3}[0
[all...] |
| armv8-mont.pl | 301 my @ACC=map("v$_",(6..13));
329 eor @ACC[0].16b,@ACC[0].16b,@ACC[0].16b
331 eor @ACC[1].16b,@ACC[1].16b,@ACC[1].16b
333 eor @ACC[2].16b,@ACC[2].16b,@ACC[2].16
[all...] |
| /src/crypto/external/bsd/openssl/dist/crypto/bn/asm/ |
| armv4-mont.pl | 306 my @ACC=map("q$_",(6..13));
342 vmull.u32 @ACC[0],$Bi,${A0}[0]
343 vmull.u32 @ACC[1],$Bi,${A0}[1]
344 vmull.u32 @ACC[2],$Bi,${A1}[0]
345 vshl.i64 $Ni,@ACC[0]#hi,#16
346 vmull.u32 @ACC[3],$Bi,${A1}[1]
348 vadd.u64 $Ni,$Ni,@ACC[0]#lo
352 vmull.u32 @ACC[4],$Bi,${A2}[0]
354 vmull.u32 @ACC[5],$Bi,${A2}[1]
355 vmull.u32 @ACC[6],$Bi,${A3}[0
[all...] |
| armv8-mont.pl | 299 my @ACC=map("v$_",(6..13));
325 eor @ACC[0].16b,@ACC[0].16b,@ACC[0].16b
327 eor @ACC[1].16b,@ACC[1].16b,@ACC[1].16b
329 eor @ACC[2].16b,@ACC[2].16b,@ACC[2].16
[all...] |
| /src/crypto/external/bsd/openssl.old/dist/crypto/bn/asm/ |
| armv4-mont.pl | 297 my @ACC=map("q$_",(6..13));
333 vmull.u32 @ACC[0],$Bi,${A0}[0]
334 vmull.u32 @ACC[1],$Bi,${A0}[1]
335 vmull.u32 @ACC[2],$Bi,${A1}[0]
336 vshl.i64 $Ni,@ACC[0]#hi,#16
337 vmull.u32 @ACC[3],$Bi,${A1}[1]
339 vadd.u64 $Ni,$Ni,@ACC[0]#lo
343 vmull.u32 @ACC[4],$Bi,${A2}[0]
345 vmull.u32 @ACC[5],$Bi,${A2}[1]
346 vmull.u32 @ACC[6],$Bi,${A3}[0
[all...] |
| /src/external/apache2/llvm/lib/libLLVMFrontendOpenACC/ |
| Makefile | 9 SRCS+= ACC.cpp
|
| /src/external/apache2/llvm/dist/clang/tools/libclang/ |
| CXCompilationDatabase.cpp | 81 AllocatedCXCompileCommands *ACC =
84 return ACC->CCmd.size();
93 AllocatedCXCompileCommands *ACC =
96 if (I >= ACC->CCmd.size())
99 return &ACC->CCmd[I];
|
| /src/external/gpl3/gdb/dist/sim/ppc/ |
| e500_expression.h | 31 ACC = ((uint64_t)(sh) << 32) | (sl & 0xffffffff); \
41 ACC = ((uint64_t)(sh) << 32) | ((sl) & 0xffffffff); \
51 ACC = (d); \
64 ACC = ((uint64_t)(rh) << 32) | ((rl) & 0xffffffff)
66 #define EV_ACCLOW (ACC & 0xffffffff)
67 #define EV_ACCHIGH ((ACC >> 32) & 0xffffffff)
|
| e500_registers.h | 71 accreg acc; member in struct:e500_regs
75 #define ACC cpu_registers(processor)->e500.acc
|
| /src/external/gpl3/gdb.old/dist/sim/ppc/ |
| e500_expression.h | 31 ACC = ((uint64_t)(sh) << 32) | (sl & 0xffffffff); \
41 ACC = ((uint64_t)(sh) << 32) | ((sl) & 0xffffffff); \
51 ACC = (d); \
64 ACC = ((uint64_t)(rh) << 32) | ((rl) & 0xffffffff)
66 #define EV_ACCLOW (ACC & 0xffffffff)
67 #define EV_ACCHIGH ((ACC >> 32) & 0xffffffff)
|
| e500_registers.h | 71 accreg acc; member in struct:e500_regs
75 #define ACC cpu_registers(processor)->e500.acc
|
| /src/external/gpl3/gdb/dist/sim/d10v/ |
| simops.c | 426 ((int)(ACC (OP[i]) >> 32) & 0xff),
427 ((unsigned long) ACC (OP[i])) & 0xffffffff);
613 tmp = SEXT40 (ACC (OP[0]));
657 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
680 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
731 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
744 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
760 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1))
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/d10v/ |
| simops.c | 426 ((int)(ACC (OP[i]) >> 32) & 0xff),
427 ((unsigned long) ACC (OP[i])) & 0xffffffff);
613 tmp = SEXT40 (ACC (OP[0]));
657 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
680 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
731 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
744 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
760 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1))
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/mips/ |
| mdmx.c | 717 typedef void (*OB_ACC)(signed24 *acc, uint8_t ts, uint8_t tt);
791 qh_vector_acc(signed48 a[], uint64_t v1, uint64_t v2, QH_ACC acc)
800 (*acc)(&a[i], h1, h2);
805 qh_map_acc(signed48 a[], uint64_t v1, int16_t h2, QH_ACC acc)
813 (*acc)(&a[i], h1, h2);
818 ob_vector_acc(signed24 a[], uint64_t v1, uint64_t v2, OB_ACC acc)
827 (*acc)(&a[i], b1, b2);
832 ob_map_acc(signed24 a[], uint64_t v1, uint8_t b2, OB_ACC acc)
840 (*acc)(&a[i], b1, b2);
863 qh_map_acc(ACC.qh, op1, QH_ELEM(op2, fmtsel), qh_acc[op])
[all...] |
| /src/external/gpl3/gdb/dist/sim/mips/ |
| mdmx.c | 717 typedef void (*OB_ACC)(signed24 *acc, uint8_t ts, uint8_t tt);
791 qh_vector_acc(signed48 a[], uint64_t v1, uint64_t v2, QH_ACC acc)
800 (*acc)(&a[i], h1, h2);
805 qh_map_acc(signed48 a[], uint64_t v1, int16_t h2, QH_ACC acc)
813 (*acc)(&a[i], h1, h2);
818 ob_vector_acc(signed24 a[], uint64_t v1, uint64_t v2, OB_ACC acc)
827 (*acc)(&a[i], b1, b2);
832 ob_map_acc(signed24 a[], uint64_t v1, uint8_t b2, OB_ACC acc)
840 (*acc)(&a[i], b1, b2);
863 qh_map_acc(ACC.qh, op1, QH_ELEM(op2, fmtsel), qh_acc[op])
[all...] |
| /src/external/gpl3/binutils/dist/gas/config/ |
| rx-parse.y | 145 %type <regno> REG FLAG CREG BCND BMCND SCCND ACC DREG DREGH DREGL DCREG DCMP
149 %token REG FLAG CREG ACC DREG DREGH DREGL DCREG
710 | MULHI REG ',' REG ',' ACC
714 | MULLO REG ',' REG ',' ACC
718 | MACHI REG ',' REG ',' ACC
722 | MACLO REG ',' REG ',' ACC
730 | MVTACHI REG ',' ACC
734 | MVTACLO REG ',' ACC
753 | RACW '#' EXPR ',' ACC
867 | EMACA REG ',' REG ',' ACC
[all...] |
| rx-parse.h | 60 ACC = 261, /* ACC */
229 #define ACC 261
|
| m68k-parse.h | 86 ACC, /* Accumulator Reg0 (EMAC or ACC on MAC). */
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| rx-parse.y | 145 %type <regno> REG FLAG CREG BCND BMCND SCCND ACC DREG DREGH DREGL DCREG DCMP
149 %token REG FLAG CREG ACC DREG DREGH DREGL DCREG
710 | MULHI REG ',' REG ',' ACC
714 | MULLO REG ',' REG ',' ACC
718 | MACHI REG ',' REG ',' ACC
722 | MACLO REG ',' REG ',' ACC
730 | MVTACHI REG ',' ACC
734 | MVTACLO REG ',' ACC
753 | RACW '#' EXPR ',' ACC
867 | EMACA REG ',' REG ',' ACC
[all...] |
| rx-parse.h | 60 ACC = 261, /* ACC */
229 #define ACC 261
|
| m68k-parse.h | 86 ACC, /* Accumulator Reg0 (EMAC or ACC on MAC). */
|
| /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/ |
| ExprEngineCXX.cpp | 291 const auto *ACC = cast<ArgumentConstructionContext>(CC);
292 const Expr *E = ACC->getCallLikeExpr();
293 unsigned Idx = ACC->getIndex();
448 const auto *ACC = cast<ArgumentConstructionContext>(CC);
449 if (const auto *BTE = ACC->getCXXBindTemporaryExpr())
453 State, {ACC->getCallLikeExpr(), ACC->getIndex()}, LCtx, V);
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| m32r-opc.c | 643 /* machi $src1,$src2,$acc */
646 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
655 /* maclo $src1,$src2,$acc */
658 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
667 /* macwhi $src1,$src2,$acc */
670 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
679 /* macwlo $src1,$src2,$acc */
682 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
697 /* mulhi $src1,$src2,$acc */
700 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| m32r-opc.c | 643 /* machi $src1,$src2,$acc */
646 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
655 /* maclo $src1,$src2,$acc */
658 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
667 /* macwhi $src1,$src2,$acc */
670 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
679 /* macwlo $src1,$src2,$acc */
682 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
697 /* mulhi $src1,$src2,$acc */
700 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| m32r-opc.c | 643 /* machi $src1,$src2,$acc */
646 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
655 /* maclo $src1,$src2,$acc */
658 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
667 /* macwhi $src1,$src2,$acc */
670 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
679 /* macwlo $src1,$src2,$acc */
682 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
697 /* mulhi $src1,$src2,$acc */
700 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }
[all...] |
