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    Searched refs:ADDR_SURF_BANK_WIDTH_1 (Results 1 - 25 of 32) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v6_0.c 428 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
436 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
463 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
471 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
479 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
491 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
499 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
507 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
    [all...]
amdgpu_gfx_v8_0.c 2232 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2236 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2240 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2244 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2264 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2268 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2272 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2412 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2416 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2420 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
    [all...]
amdgpu_gfx_v7_0.c 1166 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1174 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1178 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1182 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1186 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1190 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1202 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1206 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1210 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
    [all...]
sid.h 1207 # define ADDR_SURF_BANK_WIDTH_1 0
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_si.c 2532 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2541 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2550 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2559 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2568 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2577 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2586 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2595 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2604 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2613 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
    [all...]
radeon_cik.c 2462 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2466 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2470 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2474 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2478 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2482 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2486 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2490 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2494 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2498 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
    [all...]
cikd.h 1263 # define ADDR_SURF_BANK_WIDTH_1 0
sid.h 1209 # define ADDR_SURF_BANK_WIDTH_1 0
evergreend.h 2220 # define ADDR_SURF_BANK_WIDTH_1 0
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
bif_5_1_enum.h 960 ADDR_SURF_BANK_WIDTH_1 = 0x0,
bif_5_0_enum.h 1090 ADDR_SURF_BANK_WIDTH_1 = 0x0,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
gmc_8_2_enum.h 960 ADDR_SURF_BANK_WIDTH_1 = 0x0,
gmc_8_1_enum.h 1090 ADDR_SURF_BANK_WIDTH_1 = 0x0,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_8_0_enum.h 960 ADDR_SURF_BANK_WIDTH_1 = 0x0,
smu_7_1_0_enum.h 1119 ADDR_SURF_BANK_WIDTH_1 = 0x0,
smu_7_1_1_enum.h 1120 ADDR_SURF_BANK_WIDTH_1 = 0x0,
smu_7_1_2_enum.h 1138 ADDR_SURF_BANK_WIDTH_1 = 0x0,
smu_7_1_3_enum.h 1174 ADDR_SURF_BANK_WIDTH_1 = 0x0,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_6_0_enum.h 973 ADDR_SURF_BANK_WIDTH_1 = 0x0,
uvd_5_0_enum.h 1103 ADDR_SURF_BANK_WIDTH_1 = 0x0,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_8_0_enum.h 1045 ADDR_SURF_BANK_WIDTH_1 = 0x0,
dce_10_0_enum.h 1665 ADDR_SURF_BANK_WIDTH_1 = 0x0,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_enum.h 1255 ADDR_SURF_BANK_WIDTH_1 = 0x0,
oss_3_0_1_enum.h 1356 ADDR_SURF_BANK_WIDTH_1 = 0x0,
oss_3_0_enum.h 1389 ADDR_SURF_BANK_WIDTH_1 = 0x0,

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