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    Searched refs:AFMT_INFOFRAME_CONTROL0 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 61 SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
146 SE_SF(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
650 uint32_t AFMT_INFOFRAME_CONTROL0;
amdgpu_dce_stream_encoder.c 661 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1475 /* AFMT_INFOFRAME_CONTROL0 */
1476 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 364 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
rv770d.h 864 #define AFMT_INFOFRAME_CONTROL0 0x760c
evergreend.h 723 #define AFMT_INFOFRAME_CONTROL0 0x7134
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_stream_encoder.c 593 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1411 /* AFMT_INFOFRAME_CONTROL0 */
1412 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
dcn10_stream_encoder.h 47 SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
116 uint32_t AFMT_INFOFRAME_CONTROL0;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1654 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
amdgpu_dce_v11_0.c 1696 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
amdgpu_dce_v6_0.c 1536 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

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