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    Searched refs:AMDGPU_TILING_GET (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1903 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1997 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1998 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1999 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2000 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
amdgpu_dce_v11_0.c 1945 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2035 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2038 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2039 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2040 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2041 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2042 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2055 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
amdgpu_dce_v6_0.c 1942 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1945 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1946 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1947 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1948 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1949 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1957 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1961 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
amdgpu_dce_v8_0.c 1832 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1914 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1917 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1918 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1919 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1920 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1921 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1930 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
amdgpu_object.c 1165 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm.c 3135 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
3154 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
3155 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
3191 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
3262 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
3265 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
3266 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
3267 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
3268 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
3269 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS)
    [all...]
  /src/sys/external/bsd/drm2/dist/include/uapi/drm/
amdgpu_drm.h 354 #define AMDGPU_TILING_GET(value, field) \

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