1 /* $NetBSD: specialreg.h,v 1.223 2026/09/29 22:31:52 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 1991 The Regents of the University of California. 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. Neither the name of the University nor the names of its contributors 42 * may be used to endorse or promote products derived from this software 43 * without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 * 57 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 58 */ 59 60 /* 61 * CR0 62 */ 63 #define CR0_PE 0x00000001 /* Protected mode Enable */ 64 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 65 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 66 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 67 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 68 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 69 #define CR0_WP 0x00010000 /* Write Protect (honor PTE_W in all modes) */ 70 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 71 #define CR0_NW 0x20000000 /* Not Write-through */ 72 #define CR0_CD 0x40000000 /* Cache Disable */ 73 #define CR0_PG 0x80000000 /* PaGing enable */ 74 75 /* 76 * Cyrix 486 DLC special registers, accessible as IO ports 77 */ 78 #define CCR0 0xc0 /* configuration control register 0 */ 79 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 80 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 81 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 82 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 83 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 84 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 85 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 86 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 87 #define CCR1 0xc1 /* configuration control register 1 */ 88 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 89 90 /* 91 * CR3 92 */ 93 #define CR3_PCID __BITS(11,0) 94 #define CR3_PA __BITS(62,12) 95 #define CR3_NO_TLB_FLUSH __BIT(63) 96 97 /* 98 * CR4 99 */ 100 #define CR4_VME 0x00000001 /* Virtual 8086 mode extension enable */ 101 #define CR4_PVI 0x00000002 /* Protected mode virtual interrupt enable */ 102 #define CR4_TSD 0x00000004 /* Restrict RDTSC instruction to cpl 0 */ 103 #define CR4_DE 0x00000008 /* Debugging extension */ 104 #define CR4_PSE 0x00000010 /* Large (4MB) page size enable */ 105 #define CR4_PAE 0x00000020 /* Physical address extension enable */ 106 #define CR4_MCE 0x00000040 /* Machine check enable */ 107 #define CR4_PGE 0x00000080 /* Page global enable */ 108 #define CR4_PCE 0x00000100 /* Enable RDPMC instruction for all cpls */ 109 #define CR4_OSFXSR 0x00000200 /* Enable fxsave/fxrestor and SSE */ 110 #define CR4_OSXMMEXCPT 0x00000400 /* Enable unmasked SSE exceptions */ 111 #define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */ 112 #define CR4_LA57 0x00001000 /* 57-bit linear addresses */ 113 #define CR4_VMXE 0x00002000 /* Enable VMX operations */ 114 #define CR4_SMXE 0x00004000 /* Enable SMX operations */ 115 #define CR4_FSGSBASE 0x00010000 /* Enable *FSBASE and *GSBASE instructions */ 116 #define CR4_PCIDE 0x00020000 /* Enable Process Context IDentifiers */ 117 #define CR4_OSXSAVE 0x00040000 /* Enable xsave and xrestore */ 118 #define CR4_SMEP 0x00100000 /* Enable SMEP support */ 119 #define CR4_SMAP 0x00200000 /* Enable SMAP support */ 120 #define CR4_PKE 0x00400000 /* Enable Protection Keys for user pages */ 121 #define CR4_CET 0x00800000 /* Enable CET */ 122 #define CR4_PKS 0x01000000 /* Enable Protection Keys for kern pages */ 123 124 /* 125 * Extended Control Register XCR0, also known as XFEATURE_ENABLED_MASK, 126 * with access via XGETBV/XSETBV instructions and support indicated by 127 * CPUID[EAX=0x0d, ECX=0].EAX/EDX. 128 * 129 * References: 130 * 131 * - Intel 64 and IA-32 Architectures Software Developer's Manual, 132 * Volume 3: System Programming Guide, Intel, Order Number: 133 * 325384-087US, March 2025, Sec. 2.6 `Extended Control Registers 134 * (Including XCR0)', pp. 2-20 -- 2-22. 135 * 136 * - AMD64 Architecture Programmer's Manual, Volume 2: System 137 * Programming, Advanced Micro Devices, Publication no. 24593, 138 * Rev. 3.42, March 2024, Sec. 11.5.2 `XFEATURE_ENABLED_MASK', 139 * p. 355. 140 * 141 * XXX Missing reference for XCR0_PT, XCR0_HDC, XCR0_LBR, XCR0_HWP. 142 */ 143 #define XCR0_X87 __BIT(0) /* x87 FPU/MMX state */ 144 #define XCR0_SSE __BIT(1) /* SSE state */ 145 #define XCR0_YMM_Hi128 __BIT(2) /* AVX-256 (ymmn registers) */ 146 #define XCR0_BNDREGS __BIT(3) /* Memory protection ext bounds */ 147 #define XCR0_BNDCSR __BIT(4) /* Memory protection ext state */ 148 #define XCR0_Opmask __BIT(5) /* AVX-512 Opmask */ 149 #define XCR0_ZMM_Hi256 __BIT(6) /* AVX-512 upper 256 bits low regs */ 150 #define XCR0_Hi16_ZMM __BIT(7) /* AVX-512 512 bits upper registers */ 151 #define XCR0_PT __BIT(8) /* Processor Trace state */ 152 #define XCR0_PKRU __BIT(9) /* Protection Key state */ 153 #define XCR0_CET_U __BIT(11) /* User CET state */ 154 #define XCR0_CET_S __BIT(12) /* Kern CET state */ 155 #define XCR0_HDC __BIT(13) /* Hardware Duty Cycle state */ 156 #define XCR0_LBR __BIT(15) /* Last Branch Record */ 157 #define XCR0_HWP __BIT(16) /* Hardware P-states */ 158 #define XCR0_TILECFG __BIT(17) /* Intel AMX TILECFG state in XSAVE */ 159 #define XCR0_TILEDATA __BIT(18) /* Intel AMX TILEDATA state in XSAVE */ 160 #define XCR0_LWP __BIT(62) /* AMD Lightweight Profiling (LWP) */ 161 #define XCR0_X __BIT(63) /* AMD: reserved for XCR0 expansion */ 162 163 #define XCR0_FLAGS1 "\177\020" \ 164 "b\000" "x87\0" \ 165 "b\001" "SSE\0" \ 166 "b\002" "AVX\0" \ 167 "b\003" "BNDREGS\0" \ 168 "b\004" "BNDCSR\0" \ 169 "b\005" "Opmask\0" \ 170 "b\006" "ZMM_Hi256\0" \ 171 "b\007" "Hi16_ZMM\0" \ 172 "b\010" "PT\0" \ 173 "b\011" "PKRU\0" \ 174 "b\013" "CET_U\0" \ 175 "b\014" "CET_S\0" \ 176 "b\015" "HDC\0" \ 177 "b\017" "LBR\0" \ 178 "b\020" "HWP\0" \ 179 "b\021" "TILECFG\0" \ 180 "b\022" "TILEDATA\0" \ 181 "b\076" "LWP\0" \ 182 "b\077" "X\0" 183 184 /* 185 * XCR0_FPU: Known FPU bits, only these get enabled. The save area is 186 * sized for all the fields below. 187 * 188 * Any bits added to this will expand the extended CPU state that we 189 * may have to save and restore with XSAVE for userland processes, 190 * either in the kernel when preempting threads, or on the user's stack 191 * when delivering a signal. 192 * 193 * The kernel can dyanmically allocate larger sizes (on amd64, anyway, 194 * though not currently on i386 or Xen PV). But if the XSAVE area is 195 * expanded so much that it and mcontext_t exceed MINSIGSTKSZ 196 * (currently 8192), a userland ABI change and compatibility layer is 197 * required to accommodate that, because existing programs may use 198 * sigaltstack(2) with stacks sized for the old MINSIGSTKSZ. 199 * 200 * The current stack requirement is 3160 bytes of space plus up to 201 * 63+15+8=86 bytes of padding for alignment (could be reduced by 202 * around 512 bytes by having mcontext_t overlap with the XSAVE area a 203 * little in machdep.c cpu_getmcontext_xsave, but we don't do that 204 * right now): 205 * 206 * - mcontext_t (728 bytes: general registers and 512-byte FXSAVE area) 207 * - XSAVE header (576 bytes: 512 bytes of FXSAVE, 64 bytes of metadata) 208 * - AVX state: ymm0..ymm15 high 128-bit halves (256 bytes) 209 * - AVX-512 state: 210 * . k0..k7 opmask registers (64 bytes) 211 * . zmm0..zmm15 high 256-bit halves (512 bytes) 212 * . zmm16..zmm31 registers (1024 bytes) 213 * 214 * Likely future extensions that would expand the state beyond 215 * MINSIGSTKSZ: 216 * 217 * - AMX (Advanced Matrix Extensions) and ACE (AI Compute Extensions) 218 * state: 219 * . [AMX/ACE] TILECFG (64 bytes) 220 * . [AMX/ACE] TILEDATA (8192 bytes) 221 * . [ACE] SCALEDATA (128 bytes) 222 * 223 * As a precaution against ABI breakage, x86/identcpu.c will panic at 224 * boot if the XSAVE state size enabled in XCR0 exceeds MINSIGSTKSZ. 225 * 226 * References: 227 * 228 * - Intel 64 and IA-32 Architectures Software Developer's Manual, 229 * Volume 1: Basic Architecture, Intel, Order Number: 253665-092US, 230 * June 2026, Sec. 13.1 `XSAVE-Supported Features and State-Component 231 * Bitmaps', pp. 13-1 -- 13-2. 232 * https://web.archive.org/web/20260709150417/https://cdrdv2-public.intel.com/922477/253665-092-sdm-vol-1.pdf 233 * 234 * - AI Compute Extensions (ACE) Specification, x86 Ecosystem Advisory 235 * Group, Version 1.15, 2026-05-15, Sec 15.4.1 `XSAVE State 236 * Components', p. 86. 237 * https://web.archive.org/web/20260619062626/https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public_1_15.pdf 238 */ 239 #if defined __i386__ || defined XENPV /* XXX XENPV PR kern/59371 */ 240 #define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ 241 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) 242 #else 243 #define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ 244 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) 245 #endif 246 247 /* 248 * Maximum size of XSAVE state that we can handle without ABI changes 249 * to userland. Must match usage in cpu_getmcontext. Extra 8 is neeed 250 * on amd64 to have space for return address in 16-byte-aligned stack 251 * frame. 252 */ 253 #ifdef __x86_64__ 254 #define XSAVE_MAX_BYTES \ 255 (MINSIGSTKSZ - (8 + STACK_ALIGNBYTES + \ 256 sizeof(struct sigframe_siginfo) + (XSAVE_ALIGN - 1))) 257 #else 258 #define XSAVE_MAX_BYTES \ 259 (MINSIGSTKSZ - (STACK_ALIGNBYTES + \ 260 sizeof(struct sigframe_siginfo) + (XSAVE_ALIGN - 1))) 261 #endif 262 263 /* 264 * XSAVE component indices, internal to NetBSD. 265 */ 266 #define XSAVE_X87 0 267 #define XSAVE_SSE 1 268 #define XSAVE_YMM_Hi128 2 269 #define XSAVE_BNDREGS 3 270 #define XSAVE_BNDCSR 4 271 #define XSAVE_Opmask 5 272 #define XSAVE_ZMM_Hi256 6 273 #define XSAVE_Hi16_ZMM 7 274 275 /* 276 * Highest XSAVE component enabled by XCR0_FPU. 277 */ 278 #define XSAVE_MAX_COMPONENT XSAVE_Hi16_ZMM 279 280 /* 281 * "features" bits. 282 * CPUID Fn00000001 283 */ 284 /* %edx */ 285 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 286 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 287 #define CPUID_DE 0x00000004 /* has debugging extension */ 288 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 289 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 290 #define CPUID_MSR 0x00000020 /* has model specific registers */ 291 #define CPUID_PAE 0x00000040 /* has physical address extension */ 292 #define CPUID_MCE 0x00000080 /* has machine check exception */ 293 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 294 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 295 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 296 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 297 #define CPUID_PGE 0x00002000 /* has page global extension */ 298 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 299 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 300 #define CPUID_PAT 0x00010000 /* Page Attribute Table */ 301 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 302 #define CPUID_PSN 0x00040000 /* Processor Serial Number */ 303 #define CPUID_CLFSH 0x00080000 /* CLFLUSH instruction supported */ 304 #define CPUID_DS 0x00200000 /* Debug Store */ 305 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 306 #define CPUID_MMX 0x00800000 /* MMX supported */ 307 #define CPUID_FXSR 0x01000000 /* Fast FP/MMX Save/Restore */ 308 #define CPUID_SSE 0x02000000 /* Streaming SIMD Extensions */ 309 #define CPUID_SSE2 0x04000000 /* Streaming SIMD Extensions #2 */ 310 #define CPUID_SS 0x08000000 /* Self-Snoop */ 311 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 312 #define CPUID_TM 0x20000000 /* Thermal Monitor (TCC) */ 313 #define CPUID_PBE 0x80000000 /* Pending Break Enable */ 314 315 #define CPUID_FLAGS1 "\20" \ 316 "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ 317 "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ 318 "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ 319 "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ 320 "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFSH" \ 321 "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ 322 "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ 323 "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "PBE" 324 325 /* Blacklists of CPUID flags - used to mask certain features */ 326 #ifdef XENPV 327 #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) 328 #else 329 #define CPUID_FEAT_BLACKLIST 0 330 #endif 331 332 /* %ecx */ 333 #define CPUID2_SSE3 __BIT(0) /* Streaming SIMD Extensions 3 */ 334 #define CPUID2_PCLMULQDQ __BIT(1) /* PCLMULQDQ instructions */ 335 #define CPUID2_DTES64 __BIT(2) /* 64-bit Debug Trace */ 336 #define CPUID2_MONITOR __BIT(3) /* MONITOR/MWAIT instructions */ 337 #define CPUID2_DS_CPL __BIT(4) /* CPL Qualified Debug Store */ 338 #define CPUID2_VMX __BIT(5) /* Virtual Machine eXtensions */ 339 #define CPUID2_SMX __BIT(6) /* Safer Mode eXtensions */ 340 #define CPUID2_EST __BIT(7) /* Enhanced SpeedStep Technology */ 341 #define CPUID2_TM2 __BIT(8) /* Thermal Monitor 2 */ 342 #define CPUID2_SSSE3 __BIT(9) /* Supplemental SSE3 */ 343 #define CPUID2_CNXTID __BIT(10) /* Context ID */ 344 #define CPUID2_SDBG __BIT(11) /* Silicon Debug */ 345 #define CPUID2_FMA __BIT(12) /* Fused Multiply Add */ 346 #define CPUID2_CX16 __BIT(13) /* CMPXCHG16B instruction */ 347 #define CPUID2_XTPR __BIT(14) /* Task Priority Messages disabled? */ 348 #define CPUID2_PDCM __BIT(15) /* Perf/Debug Capability MSR */ 349 /* bit 16 unused __BIT(16) */ 350 #define CPUID2_PCID __BIT(17) /* Process Context ID */ 351 #define CPUID2_DCA __BIT(18) /* Direct Cache Access */ 352 #define CPUID2_SSE41 __BIT(19) /* Streaming SIMD Extensions 4.1 */ 353 #define CPUID2_SSE42 __BIT(20) /* Streaming SIMD Extensions 4.2 */ 354 #define CPUID2_X2APIC __BIT(21) /* xAPIC Extensions */ 355 #define CPUID2_MOVBE __BIT(22) /* MOVBE (move after byteswap) */ 356 #define CPUID2_POPCNT __BIT(23) /* POPCNT instruction available */ 357 #define CPUID2_DEADLINE __BIT(24) /* APIC Timer supports TSC Deadline */ 358 #define CPUID2_AESNI __BIT(25) /* AES instructions */ 359 #define CPUID2_XSAVE __BIT(26) /* XSAVE instructions */ 360 #define CPUID2_OSXSAVE __BIT(27) /* XGETBV/XSETBV instructions */ 361 #define CPUID2_AVX __BIT(28) /* AVX instructions */ 362 #define CPUID2_F16C __BIT(29) /* half precision conversion */ 363 #define CPUID2_RDRAND __BIT(30) /* RDRAND (hardware random number) */ 364 #define CPUID2_RAZ __BIT(31) /* RAZ. Indicates guest state. */ 365 366 #define CPUID2_FLAGS1 "\20" \ 367 "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ 368 "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ 369 "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \ 370 "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ 371 "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ 372 "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ 373 "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ 374 "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" 375 376 /* %eax */ 377 #define CPUID_TO_BASEFAMILY(cpuid) (((cpuid) >> 8) & 0xf) 378 #define CPUID_TO_BASEMODEL(cpuid) (((cpuid) >> 4) & 0xf) 379 #define CPUID_TO_STEPPING(cpuid) ((cpuid) & 0xf) 380 381 /* 382 * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY() 383 * returns 15. They are used to encode family value 16 to 270 (add 15). 384 * The Extended model bits are the high 4 bits of the model. 385 * They are only valid for family >= 15, family 6 (intel, but all amd 386 * family 6 are documented to return zero bits for them) or family 7 387 * (Zhaoxin CPUs). 388 */ 389 #define CPUID_TO_EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) 390 #define CPUID_TO_EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) 391 392 /* The macros for the Display Family and the Display Model */ 393 #define CPUID_TO_FAMILY(cpuid) (CPUID_TO_BASEFAMILY(cpuid) \ 394 + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 395 ? 0 : CPUID_TO_EXTFAMILY(cpuid))) 396 #define CPUID_TO_MODEL(cpuid) (CPUID_TO_BASEMODEL(cpuid) \ 397 | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ 398 && (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \ 399 && (CPUID_TO_BASEFAMILY(cpuid) != 0x07) \ 400 ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) 401 402 /* %ebx */ 403 #define CPUID_BRAND_INDEX __BITS(7,0) 404 #define CPUID_CLFLUSH_SIZE __BITS(15,8) 405 #define CPUID_HTT_CORES __BITS(23,16) 406 #define CPUID_LOCAL_APIC_ID __BITS(31,24) 407 408 /* 409 * Intel Deterministic Cache Parameter. 410 * CPUID Fn0000_0004 411 */ 412 413 /* %eax */ 414 #define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */ 415 #define CPUID_DCP_CACHETYPE_N 0 /* NULL */ 416 #define CPUID_DCP_CACHETYPE_D 1 /* Data cache */ 417 #define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */ 418 #define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */ 419 #define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */ 420 #define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/ 421 #define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */ 422 #define CPUID_DCP_SHARING __BITS(25, 14) /* sharing */ 423 #define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */ 424 425 /* %ebx */ 426 #define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */ 427 #define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */ 428 #define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */ 429 430 /* %ecx: Number of sets */ 431 432 /* %edx */ 433 #define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */ 434 #define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */ 435 #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ 436 437 /* 438 * Intel/AMD MONITOR/MWAIT. 439 * CPUID Fn0000_0005 440 */ 441 /* %eax */ 442 #define CPUID_MON_MINSIZE __BITS(15, 0) /* Smallest monitor-line size */ 443 /* %ebx */ 444 #define CPUID_MON_MAXSIZE __BITS(15, 0) /* Largest monitor-line size */ 445 /* %ecx */ 446 #define CPUID_MON_EMX __BIT(0) /* MONITOR/MWAIT Extensions */ 447 #define CPUID_MON_IBE __BIT(1) /* Interrupt as Break Event */ 448 449 #define CPUID_MON_FLAGS "\20" \ 450 "\1" "EMX" "\2" "IBE" 451 452 /* %edx: number of substates for specific C-state */ 453 #define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x0000000f) 454 455 /* 456 * Intel/AMD Digital Thermal Sensor and Power Management. 457 * CPUID Fn0000_0006 458 */ 459 /* %eax */ 460 #define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ 461 #define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ 462 #define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ 463 #define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ 464 #define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ 465 #define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ 466 #define CPUID_DSPM_HWP __BIT(7) /* HWP */ 467 #define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */ 468 #define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ 469 #define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ 470 #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ 471 #define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ 472 #define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */ 473 #define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */ 474 #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ 475 #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ 476 #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ 477 #define CPUID_DSPM_HFI __BIT(19) /* Hardware Feedback Interface */ 478 #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ 479 #define CPUID_DSPM_TD __BIT(23) /* Thread Director */ 480 #define CPUID_DSPM_THERMI_HFN __BIT(24) /* THERM_INTERRUPT MSR HFN bit */ 481 482 #define CPUID_DSPM_FLAGS "\20" \ 483 "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ 484 "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ 485 "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ 486 "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ 487 "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HFI" \ 488 "\25" "HWP_IGNIDL" "\30" "TD" \ 489 "\31" "THERMI_HFN" 490 491 /* %ecx */ 492 #define CPUID_DSPM_HWF __BIT(0) /* MSR_APERF/MSR_MPERF available */ 493 #define CPUID_DSPM_EPB __BIT(3) /* Energy Performance Bias */ 494 #define CPUID_DSPM_NTDC __BITS(15, 8) /* Number of Thread Director Classes */ 495 496 #define CPUID_DSPM_FLAGS1 "\177\20" \ 497 "b\0HWF\0" "b\3EPB\0" \ 498 "f\10\10NTDC\0" 499 500 /* 501 * Intel/AMD Structured Extended Feature. 502 * CPUID Fn0000_0007 503 * %ecx == 0: Subleaf 0 504 * %eax: The Maximum input value for supported subleaf. 505 * %ebx: Feature bits. 506 * %ecx: Feature bits. 507 * %edx: Feature bits. 508 * 509 * %ecx == 1: Structure Extended Feature Enumeration Sub-leaf 510 * %eax: See below. 511 */ 512 513 /* %ecx = 0, %ebx */ 514 #define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */ 515 #define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */ 516 #define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */ 517 #define CPUID_SEF_BMI1 __BIT(3) /* Advanced bit manipulation ext. 1st grp */ 518 #define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */ 519 #define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */ 520 #define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */ 521 #define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Execution Prevention */ 522 #define CPUID_SEF_BMI2 __BIT(8) /* Advanced bit manipulation ext. 2nd grp */ 523 #define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */ 524 #define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */ 525 #define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */ 526 #define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */ 527 #define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */ 528 #define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */ 529 #define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */ 530 #define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */ 531 #define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */ 532 #define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */ 533 #define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */ 534 #define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */ 535 #define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */ 536 /* Bit 22 was PCOMMIT */ 537 #define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */ 538 #define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */ 539 #define CPUID_SEF_PT __BIT(25) /* Processor Trace */ 540 #define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */ 541 #define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */ 542 #define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */ 543 #define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */ 544 #define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */ 545 #define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */ 546 547 #define CPUID_SEF_FLAGS "\20" \ 548 "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \ 549 "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \ 550 "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ 551 "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ 552 "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ 553 "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \ 554 "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ 555 "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" 556 557 /* %ecx = 0, %ecx */ 558 #define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */ 559 #define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */ 560 #define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */ 561 #define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */ 562 #define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */ 563 #define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */ 564 #define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ 565 #define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */ 566 #define CPUID_SEF_GFNI __BIT(8) /* Galois Field instructions */ 567 #define CPUID_SEF_VAES __BIT(9) /* Vector AES instruction set */ 568 #define CPUID_SEF_VPCLMULQDQ __BIT(10) /* CLMUL instruction set */ 569 #define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector Neural Network Instruction */ 570 #define CPUID_SEF_AVX512_BITALG __BIT(12) /* BITALG instructions */ 571 #define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */ 572 #define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) /* Vector Population Count D/Q */ 573 #define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */ 574 #define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */ 575 #define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ 576 #define CPUID_SEF_KL __BIT(23) /* Key Locker */ 577 #define CPUID_SEF_BUS_LOCK_DETECT __BIT(24) /* OS bus-lock detection */ 578 #define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */ 579 #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ 580 #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ 581 #define CPUID_SEF_ENQCMD __BIT(29) /* Enqueue Stores */ 582 #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ 583 #define CPUID_SEF_PKS __BIT(31) /* Protection Keys for kern-mode pages */ 584 585 #define CPUID_SEF_FLAGS1 "\177\20" \ 586 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ 587 "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ 588 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ 589 "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \ 590 "b\20LA57\0" \ 591 "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \ 592 "b\30BUS_LOCK_DETECT\0" "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ 593 "b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0" 594 595 /* %ecx = 0, %edx */ 596 #define CPUID_SEF_SGX_KEYS __BIT(1) /* Attestation support for SGX */ 597 #define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */ 598 #define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */ 599 #define CPUID_SEF_FSRM __BIT(4) /* Fast Short Rep Move */ 600 #define CPUID_SEF_UINTR __BIT(5) /* User Interrupts */ 601 #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */ 602 #define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ 603 #define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */ 604 #define CPUID_SEF_RTM_ALWAYS_ABORT __BIT(11) /* XBEGIN immediately abort */ 605 #define CPUID_SEF_RTM_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ 606 #define CPUID_SEF_SERIALIZE __BIT(14) /* SERIALIZE instruction */ 607 #define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ 608 #define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */ 609 #define CPUID_SEF_PCONFIG __BIT(18) /* Platform CONFIGuration */ 610 #define CPUID_SEF_ARCH_LBR __BIT(19) /* Architectural LBR */ 611 #define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */ 612 #define CPUID_SEF_AMX_BF16 __BIT(22) /* AMX bfloat16 */ 613 #define CPUID_SEF_AVX512_FP16 __BIT(23) /* AVX512 FP16 */ 614 #define CPUID_SEF_AMX_TILE __BIT(24) /* Tile architecture */ 615 #define CPUID_SEF_AMX_INT8 __BIT(25) /* AMX 8bit interger */ 616 #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ 617 #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ 618 #define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ 619 #define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ 620 #define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */ 621 #define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ 622 623 #define CPUID_SEF_FLAGS2 "\20" \ 624 "\2SGX_KEYS" "\3AVX512_4VNNIW" "\4AVX512_4FMAPS" \ 625 "\5FSRM" "\6UINTR" \ 626 "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" "\14RTM_ALWAYS_ABORT" \ 627 "\16RTM_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \ 628 "\21" "TSXLDTRK" "\23" "PCONFIG" "\24" "ARCH_LBR" \ 629 "\25CET_IBT" "\27AMX_BF16" "\30AVX512_FP16" \ 630 "\31AMX_TILE" "\32AMX_INT8" "\33IBRS" "\34STIBP" \ 631 "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD" 632 633 /* %ecx = 1, %eax */ 634 #define CPUID_SEF_AVXVNNI __BIT(4) /* AVX version of VNNI */ 635 #define CPUID_SEF_AVX512_BF16 __BIT(5) 636 #define CPUID_SEF_FZLRMS __BIT(10) /* fast zero-length REP MOVSB */ 637 #define CPUID_SEF_FSRSB __BIT(11) /* fast short REP STOSB */ 638 #define CPUID_SEF_FSRCS __BIT(12) /* fast short REP CMPSB, REP SCASB */ 639 #define CPUID_SEF_HRESET __BIT(22) /* HREST & IA32_HRESET_ENABLE MSR */ 640 #define CPUID_SEF_LAM __BIT(26) /* Linear Address Masking */ 641 642 #define CPUID_SEF1_FLAGS_A "\20" \ 643 "\5" "AVXVNNI" "\6" "AVX512_BF16" \ 644 "\13" "FZLRMS" "\14" "FSRSB" \ 645 "\15" "FSRCS" "\27" "HRESET" \ 646 "\31" "LAM" 647 648 /* %ecx = 1, %ebx */ 649 #define CPUID_SEF_INTEL_PPIN __BIT(0) /* IA32_PPIN & IA32_PPIN_CTL MSRs */ 650 651 #define CPUID_SEF1_FLAGS_B "\20" \ 652 "\1" "PPIN" 653 654 /* %ecx = 1, %edx */ 655 #define CPUID_SEF_CET_SSS __BIT(18) /* CET Supervisor Shadow Stack */ 656 657 #define CPUID_SEF1_FLAGS_D "\20" \ 658 "\23CET_SSS" 659 660 /* %ecx = 2, %edx */ 661 #define CPUID_SEF_PSFD __BIT(0) /* Fast Forwarding Predictor Dis. */ 662 #define CPUID_SEF_IPRED_CTRL __BIT(1) /* IPRED_DIS */ 663 #define CPUID_SEF_RRSBA_CTRL __BIT(2) /* RRSBA for CPL3 */ 664 #define CPUID_SEF_DDPD_U __BIT(3) /* Data Dependent Prefetcher */ 665 #define CPUID_SEF_BHI_CTRL __BIT(4) /* BHI_DIS_S */ 666 #define CPUID_SEF_MCDT_NO __BIT(5) /* !MXCSR Config Dependent Timing */ 667 668 #define CPUID_SEF2_FLAGS_D "\20" \ 669 "\1PSFD" "\2IPRED_CTRL" "\3RRSBA_CTRL" "\4DDPD_U" \ 670 "\5BHI_CTRL" "\6MCDT_NO" 671 672 /* 673 * Intel CPUID Architectural Performance Monitoring. 674 * CPUID Fn0000000a 675 * 676 * See also src/usr.sbin/tprof/arch/tprof_x86.c 677 */ 678 679 /* %eax */ 680 #define CPUID_PERF_VERSION __BITS(7, 0) /* Version ID */ 681 #define CPUID_PERF_NGPPC __BITS(15, 8) /* Num of G.P. perf counter */ 682 #define CPUID_PERF_NBWGPPC __BITS(23, 16) /* Bit width of G.P. perfcnt */ 683 #define CPUID_PERF_BVECLEN __BITS(31, 24) /* Length of EBX bit vector */ 684 685 #define CPUID_PERF_FLAGS0 "\177\20" \ 686 "f\0\10VERSION\0" "f\10\10GPCounter\0" \ 687 "f\20\10GPBitwidth\0" "f\30\10Vectorlen\0" 688 689 /* %ebx */ 690 #define CPUID_PERF_CORECYCL __BIT(0) /* No core cycle */ 691 #define CPUID_PERF_INSTRETRY __BIT(1) /* No instruction retried */ 692 #define CPUID_PERF_REFCYCL __BIT(2) /* No reference cycles */ 693 #define CPUID_PERF_LLCREF __BIT(3) /* No LLCache reference */ 694 #define CPUID_PERF_LLCMISS __BIT(4) /* No LLCache miss */ 695 #define CPUID_PERF_BRINSRETR __BIT(5) /* No branch inst. retried */ 696 #define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */ 697 #define CPUID_PERF_TOPDOWNSLOT __BIT(7) /* No top-down slots */ 698 699 #define CPUID_PERF_FLAGS1 "\177\20" \ 700 "b\0CORECYCL\0" "b\1INST\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ 701 "b\4LLCMISS\0" "b\5BRINST\0" "b\6BRMISPR\0" "b\7TOPDOWNSLOT\0" 702 703 /* %ecx */ 704 705 #define CPUID_PERF_FLAGS2 "\177\20" \ 706 "b\0INST\0" "b\1CLK_CORETHREAD\0" "b\2CLK_REF_TSC\0" "b\3TOPDOWNSLOT\0" 707 708 /* %edx */ 709 #define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */ 710 #define CPUID_PERF_NBWFFPC __BITS(12, 5) /* Bit width of fixed-func pc */ 711 #define CPUID_PERF_ANYTHREADDEPR __BIT(15) /* Any Thread deprecation */ 712 713 #define CPUID_PERF_FLAGS3 "\177\20" \ 714 "f\0\5FixedFunc\0" "f\5\10FFBitwidth\0" "b\17ANYTHREADDEPR\0" 715 716 /* 717 * Intel/AMD CPUID Extended Topology Enumeration. 718 * CPUID Fn0000000b 719 * %ecx == level number 720 * %eax: See below. 721 * %ebx: Number of logical processors at this level. 722 * %ecx: See below. 723 * %edx: x2APIC ID of the current logical processor. 724 */ 725 /* %eax */ 726 #define CPUID_TOP_SHIFTNUM __BITS(4, 0) /* Topology ID shift value */ 727 /* %ecx */ 728 #define CPUID_TOP_LVLNUM __BITS(7, 0) /* Level number */ 729 #define CPUID_TOP_LVLTYPE __BITS(15, 8) /* Level type */ 730 #define CPUID_TOP_LVLTYPE_INVAL 0 /* Invalid */ 731 #define CPUID_TOP_LVLTYPE_SMT 1 /* SMT */ 732 #define CPUID_TOP_LVLTYPE_CORE 2 /* Core */ 733 734 /* 735 * Intel/AMD CPUID Processor extended state Enumeration. 736 * CPUID Fn0000000d 737 * 738 * %ecx == 0: supported features info: 739 * %eax: Valid bits of lower 32bits of XCR0 740 * %ebx: Maximum save area size for features enabled in XCR0 741 * %ecx: Maximum save area size for all cpu features 742 * %edx: Valid bits of upper 32bits of XCR0 743 * 744 * %ecx == 1: 745 * %eax: See below 746 * %ebx: Save area size for features enabled by XCR0 | IA32_XSS 747 * %ecx: Valid bits of lower 32bits of IA32_XSS 748 * %edx: Valid bits of upper 32bits of IA32_XSS 749 * 750 * %ecx >= 2: Save area details for XCR0 bit n 751 * %eax: size of save area for this feature 752 * %ebx: offset of save area for this feature 753 * %ecx, %edx: reserved 754 * All of %eax, %ebx, %ecx and %edx are zero for unsupported features. 755 */ 756 757 /* %ecx = 1, %eax */ 758 #define CPUID_PES1_XSAVEOPT __BIT(0) /* xsaveopt instruction */ 759 #define CPUID_PES1_XSAVEC __BIT(1) /* xsavec & compacted XRSTOR */ 760 #define CPUID_PES1_XGETBV __BIT(2) /* xgetbv with ECX = 1 */ 761 #define CPUID_PES1_XSAVES __BIT(3) /* xsaves/xrstors, IA32_XSS */ 762 #define CPUID_PES1_XFD __BIT(4) /* eXtened Feature Disable */ 763 764 #define CPUID_PES1_FLAGS "\20" \ 765 "\1XSAVEOPT" "\2XSAVEC" "\3XGETBV" "\4XSAVES" \ 766 "\5XFD" 767 768 /* 769 * Intel Deterministic Address Translation Parameter. 770 * CPUID Fn0000_0018 771 */ 772 773 /* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */ 774 775 /* %ebx */ 776 #define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */ 777 #define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */ 778 #define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */ 779 #define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */ 780 #define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */ 781 #define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */ 782 #define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */ 783 784 /* Number of sets: %ecx */ 785 786 /* %edx */ 787 #define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */ 788 #define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */ 789 #define CPUID_DATP_TCTYPE_D 1 /* Data TLB */ 790 #define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */ 791 #define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */ 792 #define CPUID_DATP_TCTYPE_L 4 /* Load only TLB */ 793 #define CPUID_DATP_TCTYPE_S 5 /* Store only TLB */ 794 #define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ 795 #define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ 796 #define CPUID_DATP_SHARING __BITS(25, 14) /* sharing */ 797 798 /* 799 * Intel Native Model ID Information Enumeration. 800 * CPUID Fn0000_001a 801 */ 802 /* %eax */ 803 #define CPUID_HYBRID_NATIVEID __BITS(23, 0) /* Native model ID */ 804 #define CPUID_HYBRID_CORETYPE __BITS(31, 24) /* Core type */ 805 #define CPUID_HYBRID_CORETYPE_ATOM 0x20 /* Atom */ 806 #define CPUID_HYBRID_CORETYPE_CORE 0x40 /* Core */ 807 808 /* 809 * Intel Tile Information 810 * CPUID Fn0000_001d 811 * %ecx == 0: Main leaf 812 * %eax: max_palette 813 * %ecx == 1: Tile Palette1 Sub-leaf 814 * Tile palette 1 815 */ 816 817 /* %ecx */ 818 #define CPUID_TILE_P1_TOTAL_B __BITS(15, 0) 819 #define CPUID_TILE_P1_B_PERTILE __BITS(31, 16) 820 #define CPUID_TILE_P1_B_PERLOW __BITS(15, 0) 821 #define CPUID_TILE_P1_MAXNAMES __BITS(31, 16) 822 #define CPUID_TILE_P1_MAXROWS __BITS(15, 0) 823 824 /* 825 * Intel TMUL Information 826 * CPUID Fn0000_001e 827 */ 828 829 /* %ebx */ 830 #define CPUID_TMUL_MAXK __BITS(7, 0) /* Rows or columns */ 831 #define CPUID_TMUL_MAXN __BITS(23, 8) /* Column bytes */ 832 833 /* 834 * Intel extended features. 835 * CPUID Fn80000001 836 */ 837 /* %edx */ 838 #define CPUID_SYSCALL __BIT(11) /* SYSCALL/SYSRET */ 839 #define CPUID_XD __BIT(20) /* Execute Disable (like CPUID_NOX) */ 840 #define CPUID_PAGE1GB __BIT(26) /* 1GB Large Page Support */ 841 #define CPUID_RDTSCP __BIT(27) /* Read TSC Pair Instruction */ 842 #define CPUID_EM64T __BIT(29) /* Intel EM64T */ 843 844 #define CPUID_INTEL_EXT_FLAGS "\20" \ 845 "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ 846 "\34" "RDTSCP" "\36" "EM64T" 847 848 /* %ecx */ 849 #define CPUID_LAHF __BIT(0) /* LAHF/SAHF in IA-32e mode, 64bit sub*/ 850 /* __BIT(5) */ /* LZCNT. Same as AMD's CPUID_ABM */ 851 #define CPUID_PREFETCHW __BIT(8) /* PREFETCHW */ 852 853 #define CPUID_INTEL_FLAGS4 "\20" \ 854 "\1" "LAHF" "\02" "B01" "\03" "B02" \ 855 "\06" "LZCNT" \ 856 "\11" "PREFETCHW" 857 858 859 /* 860 * AMD/VIA extended features. 861 * CPUID Fn80000001 862 */ 863 /* %edx */ 864 /* CPUID_SYSCALL SYSCALL/SYSRET */ 865 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 866 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ 867 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 868 /* CPUID_MMX MMX supported */ 869 /* CPUID_FXSR fast FP/MMX save/restore */ 870 #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ 871 /* CPUID_PAGE1GB 1GB Large Page Support */ 872 /* CPUID_RDTSCP Read TSC Pair Instruction */ 873 /* CPUID_EM64T Long mode */ 874 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 875 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 876 877 #define CPUID_EXT_FLAGS "\20" \ 878 "\14" "SYSCALL/SYSRET" \ 879 "\24" "MPC" \ 880 "\25" "NOX" "\27" "MMXX" "\30" "MMX" \ 881 "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ 882 "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" 883 884 /* %ecx (AMD) */ 885 /* CPUID_LAHF LAHF/SAHF instruction */ 886 #define CPUID_CMPLEGACY __BIT(1) /* Compare Legacy */ 887 #define CPUID_SVM __BIT(2) /* Secure Virtual Machine */ 888 #define CPUID_EAPIC __BIT(3) /* Extended APIC space */ 889 #define CPUID_ALTMOVCR0 __BIT(4) /* Lock Mov Cr0 */ 890 #define CPUID_ABM __BIT(5) /* LZCNT instruction */ 891 #define CPUID_SSE4A __BIT(6) /* SSE4A instruction set */ 892 #define CPUID_MISALIGNSSE __BIT(7) /* Misaligned SSE */ 893 #define CPUID_3DNOWPF __BIT(8) /* 3DNow Prefetch */ 894 #define CPUID_OSVW __BIT(9) /* OS visible workarounds */ 895 #define CPUID_IBS __BIT(10) /* Instruction Based Sampling */ 896 #define CPUID_XOP __BIT(11) /* XOP instruction set */ 897 #define CPUID_SKINIT __BIT(12) /* SKINIT */ 898 #define CPUID_WDT __BIT(13) /* watchdog timer support */ 899 #define CPUID_LWP __BIT(15) /* Light Weight Profiling */ 900 #define CPUID_FMA4 __BIT(16) /* FMA4 instructions */ 901 #define CPUID_TCE __BIT(17) /* Translation cache Extension */ 902 #define CPUID_NODEID __BIT(19) /* NodeID MSR available */ 903 #define CPUID_TBM __BIT(21) /* TBM instructions */ 904 #define CPUID_TOPOEXT __BIT(22) /* cpuid Topology Extension */ 905 #define CPUID_PCEC __BIT(23) /* Perf Ctr Ext Core */ 906 #define CPUID_PCENB __BIT(24) /* Perf Ctr Ext NB */ 907 #define CPUID_SPM __BIT(25) /* Stream Perf Mon */ 908 #define CPUID_DBE __BIT(26) /* Data Breakpoint Extension */ 909 #define CPUID_PTSC __BIT(27) /* PerfTsc */ 910 #define CPUID_L2IPERFC __BIT(28) /* L2I performance counter Extension */ 911 #define CPUID_MWAITX __BIT(29) /* MWAITX/MONITORX support */ 912 #define CPUID_ADDRMASKEXT __BIT(30) /* Breakpoint Addressing Mask ext. */ 913 914 #define CPUID_AMD_FLAGS4 "\20" \ 915 "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ 916 "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ 917 "\11" "3DNOWPREFETCH" \ 918 "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ 919 "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ 920 "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ 921 "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ 922 "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ 923 "\35" "L2IPERFC" "\36" "MWAITX" "\37" "AddrMaskExt" "\40" "B31" 924 925 /* 926 * Advanced Power Management and RAS. 927 * CPUID Fn8000_0007 928 * 929 * Only ITSC is for both Intel and AMD. Others are only for AMD. 930 * 931 * %ebx: RAS capabilities. See below. 932 * %ecx: Processor Power Monitoring Interface. 933 * %edx: See below. 934 * 935 */ 936 /* %ebx */ 937 #define CPUID_RAS_OVFL_RECOV __BIT(0) /* MCA Overflow Recovery */ 938 #define CPUID_RAS_SUCCOR __BIT(1) /* Sw UnCorr. err. COntainment & Recovery */ 939 #define CPUID_RAS_MCAX __BIT(3) /* MCA Extension */ 940 941 #define CPUID_RAS_FLAGS "\20" \ 942 "\1OVFL_RECOV" "\2SUCCOR" "\4" "MCAX" 943 944 /* %edx */ 945 #define CPUID_APM_TS __BIT(0) /* Temperature Sensor */ 946 #define CPUID_APM_FID __BIT(1) /* Frequency ID control */ 947 #define CPUID_APM_VID __BIT(2) /* Voltage ID control */ 948 #define CPUID_APM_TTP __BIT(3) /* THERMTRIP (PCI F3xE4 register) */ 949 #define CPUID_APM_HTC __BIT(4) /* Hardware thermal control (HTC) */ 950 #define CPUID_APM_STC __BIT(5) /* Software thermal control (STC) */ 951 #define CPUID_APM_100 __BIT(6) /* 100MHz multiplier control */ 952 #define CPUID_APM_HWP __BIT(7) /* HW P-State control */ 953 #define CPUID_APM_ITSC __BIT(8) /* Invariant TSC */ 954 #define CPUID_APM_CPB __BIT(9) /* Core Performance Boost */ 955 #define CPUID_APM_EFF __BIT(10) /* Effective Frequency (read-only) */ 956 #define CPUID_APM_PROCFI __BIT(11) /* Processor Feedback Interface */ 957 #define CPUID_APM_PROCPR __BIT(12) /* Processor Power Reporting */ 958 #define CPUID_APM_CONNSTBY __BIT(13) /* Connected Standby */ 959 #define CPUID_APM_RAPL __BIT(14) /* Running Average Power Limit */ 960 961 #define CPUID_APM_FLAGS "\20" \ 962 "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ 963 "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ 964 "\11" "ITSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ 965 "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" 966 967 /* 968 * AMD Processor Capacity Parameters and Extended Features. 969 * CPUID Fn8000_0008 970 * %eax: Long Mode Size Identifiers 971 * %ebx: Extended Feature Identifiers 972 * %ecx: Size Identifiers 973 * %edx: RDPRU Register Identifier Range 974 */ 975 976 /* %ebx */ 977 #define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ 978 #define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ 979 #define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */ 980 #define CPUID_CAPEX_INVLPGB __BIT(3) /* INVLPGB instruction */ 981 #define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */ 982 #define CPUID_CAPEX_MBE __BIT(6) /* Memory Bandwidth Enforcement */ 983 #define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */ 984 #define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */ 985 #define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */ 986 #define CPUID_CAPEX_INT_WBINVD __BIT(13) /* Interruptable WB[NO]INVD */ 987 #define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */ 988 #define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */ 989 #define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */ 990 #define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */ 991 #define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */ 992 #define CPUID_CAPEX_IBRS_SAMEMODE __BIT(19) /* IBRS same speculation limits */ 993 #define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */ 994 #define CPUID_CAPEX_INVLPGB_NEST __BIT(21) /* INVLPGB nested translation */ 995 #define CPUID_CAPEX_AMD_PPIN __BIT(23) /* Protected Processor Inventory Number */ 996 #define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */ 997 #define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ 998 #define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ 999 #define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */ 1000 #define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */ 1001 #define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */ 1002 #define CPUID_CAPEX_IBPB_RET __BIT(30) /* Clear RET address predictor */ 1003 1004 #define CPUID_CAPEX_FLAGS "\20" \ 1005 "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" "\4INVLPGB" \ 1006 "\5RDPRU" "\7MBE" \ 1007 "\11MCOMMIT" "\12WBNOINVD" "\13B10" \ 1008 "\15IBPB" "\16INT_WBINVD" "\17IBRS" "\20STIBP" \ 1009 "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" \ 1010 "\24IBRS_SAMEMODE" \ 1011 "\25EFER_LSMSLE_UN" "\26INVLPGB_NEST" "\30PPIN" \ 1012 "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" "\34CPPC" \ 1013 "\35PSFD" "\36BTC_NO" "\37IBPB_RET" 1014 1015 /* %ecx */ 1016 #define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */ 1017 #define CPUID_CAPEX_ApicIdSize __BITS(15,12) /* APIC ID Size */ 1018 #define CPUID_CAPEX_NC __BITS(7,0) /* Number of threads - 1 */ 1019 1020 /* 1021 * AMD SVM Revision and Feature. 1022 * CPUID Fn8000_000a 1023 */ 1024 1025 /* %eax: SVM revision */ 1026 #define CPUID_AMD_SVM_REV __BITS(7,0) 1027 1028 /* %edx: SVM features */ 1029 #define CPUID_AMD_SVM_NP __BIT(0) /* Nested Paging */ 1030 #define CPUID_AMD_SVM_LbrVirt __BIT(1) /* LBR virtualization */ 1031 #define CPUID_AMD_SVM_SVML __BIT(2) /* SVM Lock */ 1032 #define CPUID_AMD_SVM_NRIPS __BIT(3) /* NRIP Save on #VMEXIT */ 1033 #define CPUID_AMD_SVM_TSCRateCtrl __BIT(4) /* MSR-based TSC rate ctrl */ 1034 #define CPUID_AMD_SVM_VMCBCleanBits __BIT(5) /* VMCB Clean Bits support */ 1035 #define CPUID_AMD_SVM_FlushByASID __BIT(6) /* Flush by ASID */ 1036 #define CPUID_AMD_SVM_DecodeAssist __BIT(7) /* Decode Assists support */ 1037 #define CPUID_AMD_SVM_PmcVirt __BIT(8) /* PMC Virtualization */ 1038 #define CPUID_AMD_SVM_PauseFilter __BIT(10) /* PAUSE intercept filter */ 1039 #define CPUID_AMD_SVM_PFThreshold __BIT(12) /* PAUSE filter threshold */ 1040 #define CPUID_AMD_SVM_AVIC __BIT(13) /* Advanced Virt. Intr. Ctrl */ 1041 #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD __BIT(15) /* Virtual VM{SAVE/LOAD} */ 1042 #define CPUID_AMD_SVM_vGIF __BIT(16) /* Virtualized GIF */ 1043 #define CPUID_AMD_SVM_GMET __BIT(17) /* Guest Mode Execution Trap */ 1044 #define CPUID_AMD_SVM_X2AVIC __BIT(18) /* Virt. Intr. Ctrl 4 x2APIC */ 1045 #define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */ 1046 #define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */ 1047 #define CPUID_AMD_SVM_ROGPT __BIT(21) /* Read-Only Guest PTable */ 1048 #define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */ 1049 #define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */ 1050 #define CPUID_AMD_SVM_VNMI __BIT(25) /* NMI Virtualization */ 1051 #define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */ 1052 #define CPUID_AMD_SVM_XLVTOFFFLTCHG __BIT(27) /* Ext LVToffset FLT changed */ 1053 #define CPUID_AMD_SVM_VMCBADRCHKCHG __BIT(28) /* VMCB addr check changed */ 1054 #define CPUID_AMD_SVM_BUSLOCKTHRESH __BIT(29) /* Bus Lock Threshold */ 1055 #define CPUID_AMD_SVM_IDLEHLTINTERCEPT __BIT(30) /* Idle HLT Intercept */ 1056 #define CPUID_AMD_SVM_ESHUTDOWN __BIT(31) /* Enhanced Shutdown Intr. */ 1057 1058 #define CPUID_AMD_SVM_FLAGS "\20" \ 1059 "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ 1060 "\5" "TSCRate" "\6" "VMCBCleanBits" \ 1061 "\7" "FlushByASID" "\10" "DecodeAssist" \ 1062 "\11PmcVirt" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ 1063 "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \ 1064 "\20" "V_VMSAVE_VMLOAD" \ 1065 "\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \ 1066 "\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \ 1067 "\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \ 1068 "\35VmcbAddrChkChg" "\36BusLockThreshold" "\37IdleHltIntercept" \ 1069 "\40EnhancedShutdownInterrupt" 1070 1071 /* 1072 * AMD Instruction-Based Sampling Capabilities. 1073 * CPUID Fn8000_001b 1074 */ 1075 /* %eax */ 1076 #define CPUID_IBS_FFV __BIT(0) /* Feature Flags Valid */ 1077 #define CPUID_IBS_FETCHSUM __BIT(1) /* Fetch Sampling */ 1078 #define CPUID_IBS_OPSAM __BIT(2) /* execution SAMpling */ 1079 #define CPUID_IBS_RDWROPCNT __BIT(3) /* Read Write of Op Counter */ 1080 #define CPUID_IBS_OPCNT __BIT(4) /* OP CouNTing mode */ 1081 #define CPUID_IBS_BRNTRGT __BIT(5) /* Branch Target */ 1082 #define CPUID_IBS_OPCNTEXT __BIT(6) /* OpCurCnt and OpMaxCnt extended */ 1083 #define CPUID_IBS_RIPINVALIDCHK __BIT(7) /* Invalid RIP indication */ 1084 #define CPUID_IBS_OPBRNFUSE __BIT(8) /* Fused branch micro-op indicate */ 1085 #define CPUID_IBS_FETCHCTLEXTD __BIT(9) /* IC_IBS_EXTD_CTL MSR */ 1086 #define CPUID_IBS_OPDATA4 __BIT(10) /* IBS op data 4 MSR */ 1087 #define CPUID_IBS_ZEN4E __BIT(11) /* Zen4 IBS Extensions */ 1088 #define CPUID_IBS_LOADLATFILT __BIT(12) /* Load Latency Filtering */ 1089 #define CPUID_IBS_UPDDTLBSTAT __BIT(19) /* Updated DTLB stats */ 1090 1091 #define CPUID_IBS_FLAGS "\20" \ 1092 "\1IBSFFV" "\2FetchSam" "\3OpSam" "\4RdWrOpCnt" \ 1093 "\5OpCnt" "\6BrnTrgt" "\7OpCntExt" "\10RipInvalidChk" \ 1094 "\11OpBrnFuse" "\12IbsFetchCtlExtd" "\13IbsOpData4" \ 1095 "\14Zen4IbsExtensions" \ 1096 "\15IbsLoadLatencyFiltering" \ 1097 "\24IbsUpdtdDtlbStats" 1098 1099 /* 1100 * AMD Cache Topology Information. 1101 * CPUID Fn8000_001d 1102 * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04) 1103 * except the following: 1104 * No Cores/package (%eax bit 31..26) 1105 * No Complex cache indexing (%edx bit 2) 1106 */ 1107 1108 /* 1109 * AMD Processor Topology Information. 1110 * CPUID Fn8000_001e 1111 * %eax: Extended APIC ID. 1112 * %ebx: Core Identifiers. 1113 * %ecx: Node Identifiers. 1114 */ 1115 1116 /* %ebx */ 1117 #define CPUID_AMD_PROCT_COREID __BITS(7,0) /* Core ID */ 1118 #define CPUID_AMD_PROCT_THREADS_PER_CORE __BITS(15,8) /* Threads/Core - 1 */ 1119 1120 /* %ecx */ 1121 #define CPUID_AMD_PROCT_NODEID __BITS(7,0) /* Node ID */ 1122 #define CPUID_AMD_PROCT_NODE_PER_PROCESSOR __BITS(10,8) /* Node/Processor -1 */ 1123 1124 /* 1125 * AMD Encrypted Memory Capabilities. 1126 * CPUID Fn8000_001f 1127 * %eax: flags 1128 * %ebx: 5-0: Cbit Position 1129 * 11-6: PhysAddrReduction 1130 * 15-12: NumVMPL 1131 * %ecx: 31-0: NumEncryptedGuests 1132 * %edx: 31-0: MinSevNoEsAsid 1133 */ 1134 #define CPUID_AMD_ENCMEM_SME __BIT(0) /* Secure Memory Encryption */ 1135 #define CPUID_AMD_ENCMEM_SEV __BIT(1) /* Secure Encrypted Virtualiz. */ 1136 #define CPUID_AMD_ENCMEM_PGFLMSR __BIT(2) /* Page Flush MSR */ 1137 #define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */ 1138 #define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */ 1139 #define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */ 1140 #define CPUID_AMD_ENCMEM_RMPQUERY __BIT(6) /* RMPQUERY instruction */ 1141 #define CPUID_AMD_ENCMEM_VMPLSSS __BIT(7) /* VMPL Secure Shadow Stack */ 1142 #define CPUID_AMD_ENCMEM_SECTSC __BIT(8) /* Secure TSC */ 1143 #define CPUID_AMD_ENCMEM_TSCAUX_V __BIT(9) /* TSC AUX Virtualization */ 1144 #define CPUID_AMD_ENCMEM_HECC __BIT(10) /* HW Enf Cache Coh across enc dom */ 1145 #define CPUID_AMD_ENCMEM_64BH __BIT(11) /* 64Bit Host */ 1146 #define CPUID_AMD_ENCMEM_RSTRINJ __BIT(12) /* Restricted Injection */ 1147 #define CPUID_AMD_ENCMEM_ALTINJ __BIT(13) /* Alternate Injection */ 1148 #define CPUID_AMD_ENCMEM_DBGSWAP __BIT(14) /* Debug Swap */ 1149 #define CPUID_AMD_ENCMEM_PREVHOSTIBS __BIT(15) /* Prevent Host IBS */ 1150 #define CPUID_AMD_ENCMEM_VTE __BIT(16) /* Virtual Transparent Encryption */ 1151 #define CPUID_AMD_ENCMEM_VMGEXITP __BIT(17) /* VMGEXIT Parameter */ 1152 #define CPUID_AMD_ENCMEM_VIRTTOM __BIT(18) /* Virtual TOM MSR */ 1153 #define CPUID_AMD_ENCMEM_IBSVGUEST __BIT(19) /* IBS Virt. for SEV-ES guest */ 1154 #define CPUID_AMD_ENCMEM_PMCVGUEST __BIT(20) /* PMC Virt. for SEV-ES guest */ 1155 #define CPUID_AMD_ENCMEM_RMPREAD __BIT(21) /* RMPREAD instruction */ 1156 #define CPUID_AMD_ENCMEM_GUESTINTERCEPT __BIT(22) /* Guest Intercept 4SEV-ES */ 1157 #define CPUID_AMD_ENCMEM_SEGRMP __BIT(23) /* Segmented RMP */ 1158 #define CPUID_AMD_ENCMEM_VMSA_REGPROT __BIT(24) /* VmsaRegProt */ 1159 #define CPUID_AMD_ENCMEM_SMTPROTECT __BIT(25) /* SMT Protection */ 1160 #define CPUID_AMD_ENCMEM_SECAVIC __BIT(26) /* Secure AVIC */ 1161 #define CPUID_AMD_ENCMEM_ALLOWSEV __BIT(27) /* Allowed SEV */ 1162 #define CPUID_AMD_ENCMEM_SVSM_COMMPAGE __BIT(28) /* SVSM Communication Page */ 1163 #define CPUID_AMD_ENCMEM_NESTED_VSMP __BIT(29) /* VIRT_{RMPUPDATE,PSMASH} */ 1164 #define CPUID_AMD_ENCMEM_HVINUSEWR __BIT(30) /* HV In Use Write Allow */ 1165 #define CPUID_AMD_ENCMEM_IBPBONENTRY __BIT(31) /* IBPB on Entry */ 1166 1167 #define CPUID_AMD_ENCMEM_FLAGS "\20" \ 1168 "\1" "SME" "\2" "SEV" "\3" "PageFlushMsr" "\4" "SEV-ES" \ 1169 "\5" "SEV-SNP" "\6" "VMPL" "\7RMPQUERY" "\10VmplSSS" \ 1170 "\11SecureTSC" "\12TscAuxVirt" "\13HwEnfCacheCoh" "\14" "64BitHost" \ 1171 "\15" "RSTRINJ" "\16" "ALTINJ" "\17" "DebugSwap" "\20PreventHostIbs" \ 1172 "\21VTE" "\22VmgexitParam" "\23VirtualTomMsr" "\24IbsVirtGuest" \ 1173 "\25PmcVirtGuest" "\26RMPREAD" \ 1174 "\27GuestInterceptControl" "\30SegmentedRmp" \ 1175 "\31VmsaRegProt" "\32SmtProtection" "\33SecureAvic" "\34AllowedSev" \ 1176 "\35SvsmCommPageMSR" "\36NestedVirtSnpMsr" "\37HvInuseWrAllowed" \ 1177 "\40IbpbOnEntry" 1178 1179 /* 1180 * AMD Extended Features 2. 1181 * CPUID Fn8000_0021 1182 */ 1183 1184 /* %eax */ 1185 #define CPUID_AMDEXT2_NONESTEDDBP __BIT(0) /* No nested data breakpoints */ 1186 #define CPUID_AMDEXT2_FGKBNOSERIAL __BIT(1) /* {FS,GS,K}BASE WRMSR !serializ */ 1187 #define CPUID_AMDEXT2_LFENCESERIAL __BIT(2) /* LFENCE always serializing */ 1188 #define CPUID_AMDEXT2_SMMPGCFGLCK __BIT(3) /* SMM Paging configuration lock */ 1189 #define CPUID_AMDEXT2_NULLSELCLRB __BIT(6) /* Null segment selector clr base */ 1190 #define CPUID_AMDEXT2_UPADDRIGN __BIT(7) /* Upper Address Ignore */ 1191 #define CPUID_AMDEXT2_AUTOIBRS __BIT(8) /* Automatic IBRS */ 1192 #define CPUID_AMDEXT2_NOSMMCTL __BIT(9) /* SMM_CTL MSR is not supported */ 1193 #define CPUID_AMDEXT2_FSRS __BIT(10) /* Fast Short Rep Stosb */ 1194 #define CPUID_AMDEXT2_FSRC __BIT(11) /* Fast Short Rep Cmpsb */ 1195 #define CPUID_AMDEXT2_PMCPRECISERETIRE __BIT(12) /* PMC Presize Retire */ 1196 #define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */ 1197 #define CPUID_AMDEXT2_L2TLBSIZEX32 __BIT(14) /* L2TLB size encoded as x32 */ 1198 #define CPUID_AMDEXT2_ERMSB __BIT(15) /* AMD implementation of ERMSB */ 1199 #define CPUID_AMDEXT2_OPF17RECLAIM __BIT(16) /* Reserve opcode 0f 01/7 */ 1200 #define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */ 1201 #define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predictive Store Fwd */ 1202 #define CPUID_AMDEXT2_0F017_RECLAIM __BIT(19) /* Opecode 0f 01/7 reserved */ 1203 #define CPUID_AMDEXT2_PREFETCHI __BIT(20) /* IC prefetch support */ 1204 #define CPUID_AMDEXT2_FP512_DOWNGRADE __BIT(21) /* FP512 dpath down to 256 */ 1205 #define CPUID_AMDEXT2_WL_CLASS __BIT(22) /* wkld based heuristic feedback */ 1206 #define CPUID_AMDEXT2_ERAPS __BIT(24) /* Enhn. Retn. Addr. Pred. Sec. */ 1207 #define CPUID_AMDEXT2_SBPB __BIT(27) /* Selective Brnc. Pred. Barrier */ 1208 #define CPUID_AMDEXT2_IBPB_BRTYPE __BIT(28) /* BRanch TYPE prediction flush */ 1209 #define CPUID_AMDEXT2_SRSO_NO __BIT(29) /* Not vulnerable to SRSO */ 1210 #define CPUID_AMDEXT2_SRSO_UK_NO __BIT(30) /* SRSO_NO at user-kern boundary */ 1211 #define CPUID_AMDEXT2_SRSO_MSR_FIX __BIT(31) /* SRSO mitig. bit in BP_CFG[4] */ 1212 1213 #define CPUID_AMDEXT2_FLAGS "\20" \ 1214 "\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing" \ 1215 "\3LfenceAlwaysSerialize" "\4SmmPgCfgLock" \ 1216 "\7NullSelectClearsBase" "\10UpperAddressIgnore" \ 1217 "\11AutomaticIBRS" "\12NoSmmCtlMSR" "\13FSRS" "\14FSRC" \ 1218 "\15PMC2PreciseRetire" "\16PrefetchCtlMSR" "\17L2TlbsizeX32" \ 1219 "\20AMD_ERMSB" \ 1220 "\21OPCODE_0F017_RECLAIM" "\22CpuidUserDis" "\23EPSF" \ 1221 "\24FAST_REP_SCASB" \ 1222 "\25PREFETCHI" "\26FP512_DOWNGRADE" "\27WL_CLASS_SUPPORT" \ 1223 "\31ERAPS" "\34SBPB" \ 1224 "\35IBPB_BRTYPE" "\36SRSO_NO" "\37SRSO_USER_KERNEL_NO" \ 1225 "\40SRSO_MSR_FIX" 1226 1227 /* 1228 * AMD Extended Performance Monitoring and Debug 1229 * CPUID Fn8000_0022 1230 */ 1231 1232 /* %eax */ 1233 #define CPUID_AXPERF_PERFMONV2 __BIT(0) /* Version 2 */ 1234 #define CPUID_AXPERF_LBRSTACK __BIT(1) /* Last Branch Record Stack */ 1235 #define CPUID_AXPERF_LBRPMCFREEZE __BIT(2) /* Freezing LBR and PMC */ 1236 1237 #define CPUID_AXPERF_FLAGS "\20" \ 1238 "\1PerfMonV2" "\2LbrStack" "\3LbrAndPmcFreeze" 1239 1240 /* %ebx */ 1241 #define CPUID_AXPERF_NCPC __BITS(3, 0) /* Num of Core PMC counters */ 1242 #define CPUID_AXPERF_NLBRSTACK __BITS(9, 4) /* Num of LBR Stack entries */ 1243 #define CPUID_AXPERF_NNBPC __BITS(15, 10) /* Num of NorthBridge PMCs */ 1244 #define CPUID_AXPERF_NUMCPC __BITS(23, 16) /* Num of UMC PMCs */ 1245 1246 /* 1247 * AMD Hetero Workload Classification 1248 * CPUID Fn8000_0027 1249 */ 1250 1251 /* %eax */ 1252 1253 #define CPUID_HWC_NWC __BITS(3, 0) /* Number of Workload Class IDs */ 1254 1255 /* 1256 * Centaur Extended Feature flags. 1257 * CPUID FnC000_0001 (VIA "Nehemiah" or later) 1258 */ 1259 #define CPUID_VIA_HAS_AIS __BIT(0) /* Alternate Instruction Set supported */ 1260 /* (VIA "Nehemiah" only) */ 1261 #define CPUID_VIA_DO_AIS __BIT(1) /* Alternate Instruction Set enabled */ 1262 /* (VIA "Nehemiah" only) */ 1263 #define CPUID_VIA_HAS_RNG __BIT(2) /* Random number generator */ 1264 #define CPUID_VIA_DO_RNG __BIT(3) 1265 #define CPUID_VIA_HAS_ACE __BIT(6) /* AES Encryption */ 1266 #define CPUID_VIA_DO_ACE __BIT(7) 1267 #define CPUID_VIA_HAS_ACE2 __BIT(8) /* AES+CTR instructions */ 1268 #define CPUID_VIA_DO_ACE2 __BIT(9) 1269 #define CPUID_VIA_HAS_PHE __BIT(10) /* SHA1+SHA256 HMAC */ 1270 #define CPUID_VIA_DO_PHE __BIT(11) 1271 #define CPUID_VIA_HAS_PMM __BIT(12) /* RSA Instructions */ 1272 #define CPUID_VIA_DO_PMM __BIT(13) 1273 1274 #define CPUID_FLAGS_PADLOCK "\20" \ 1275 "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \ 1276 "\15" "RSA" 1277 1278 /* 1279 * Model-Specific Registers 1280 */ 1281 #define MSR_TSC 0x010 1282 #define MSR_IA32_PLATFORM_ID 0x017 1283 #define MSR_APICBASE 0x01b 1284 #define APICBASE_BSP 0x00000100 /* boot processor */ 1285 #define APICBASE_EXTD 0x00000400 /* x2APIC mode */ 1286 #define APICBASE_EN 0x00000800 /* software enable */ 1287 /* 1288 * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're 1289 * only interested in the initial value, which is guaranteed to fit the 1290 * first 32 bits. So this macro is fine. 1291 */ 1292 #define APICBASE_PHYSADDR 0xfffff000 /* physical address */ 1293 #define MSR_EBL_CR_POWERON 0x02a 1294 #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ 1295 #define MSR_IA32_SPEC_CTRL 0x048 1296 #define IA32_SPEC_CTRL_IBRS 0x01 1297 #define IA32_SPEC_CTRL_STIBP 0x02 1298 #define IA32_SPEC_CTRL_SSBD 0x04 1299 #define MSR_IA32_PRED_CMD 0x049 1300 #define IA32_PRED_CMD_IBPB 0x01 1301 #define MSR_BIOS_UPDT_TRIG 0x079 1302 #define MSR_BIOS_SIGN 0x08b 1303 #define MSR_PERFCTR0 0x0c1 1304 #define MSR_PERFCTR1 0x0c2 1305 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 1306 #define MSR_MPERF 0x0e7 1307 #define MSR_APERF 0x0e8 1308 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 1309 #define MSR_MTRRcap 0x0fe 1310 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 1311 #define IA32_ARCH_RDCL_NO 0x01 1312 #define IA32_ARCH_IBRS_ALL 0x02 1313 #define IA32_ARCH_RSBA 0x04 1314 #define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08 1315 #define IA32_ARCH_SSB_NO 0x10 1316 #define IA32_ARCH_MDS_NO 0x20 1317 #define IA32_ARCH_IF_PSCHANGE_MC_NO 0x40 1318 #define IA32_ARCH_TSX_CTRL 0x80 1319 #define IA32_ARCH_TAA_NO 0x100 1320 #define MSR_IA32_FLUSH_CMD 0x10b 1321 #define IA32_FLUSH_CMD_L1D_FLUSH 0x01 1322 #define MSR_TSX_FORCE_ABORT 0x10f 1323 #define MSR_IA32_TSX_CTRL 0x122 1324 #define IA32_TSX_CTRL_RTM_DISABLE __BIT(0) 1325 #define IA32_TSX_CTRL_TSX_CPUID_CLEAR __BIT(1) 1326 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 1327 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 1328 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 1329 #define MSR_MCG_CAP 0x179 1330 #define MSR_MCG_STATUS 0x17a 1331 #define MSR_MCG_CTL 0x17b 1332 #define MSR_EVNTSEL0 0x186 1333 #define MSR_EVNTSEL1 0x187 1334 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 1335 #define MSR_PERF_CTL 0x199 /* Pentium M */ 1336 #define MSR_THERM_CONTROL 0x19a 1337 #define MSR_THERM_INTERRUPT 0x19b 1338 #define MSR_THERM_STATUS 0x19c 1339 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 1340 #define MSR_MISC_ENABLE 0x1a0 1341 #define IA32_MISC_FAST_STR_EN __BIT(0) 1342 #define IA32_MISC_ATCC_EN __BIT(3) 1343 #define IA32_MISC_PERFMON_EN __BIT(7) 1344 #define IA32_MISC_BTS_UNAVAIL __BIT(11) 1345 #define IA32_MISC_PEBS_UNAVAIL __BIT(12) 1346 #define IA32_MISC_EISST_EN __BIT(16) 1347 #define IA32_MISC_MWAIT_EN __BIT(18) 1348 #define IA32_MISC_LIMIT_CPUID __BIT(22) 1349 #define IA32_MISC_XTPR_DIS __BIT(23) 1350 #define IA32_MISC_XD_DIS __BIT(34) 1351 #define MSR_TEMPERATURE_TARGET 0x1a2 1352 #define MSR_DEBUGCTLMSR 0x1d9 1353 #define MSR_LASTBRANCHFROMIP 0x1db 1354 #define MSR_LASTBRANCHTOIP 0x1dc 1355 #define MSR_LASTINTFROMIP 0x1dd 1356 #define MSR_LASTINTTOIP 0x1de 1357 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 1358 #define MSR_MTRRphysBase0 0x200 1359 #define MSR_MTRRphysMask0 0x201 1360 #define MSR_MTRRphysBase1 0x202 1361 #define MSR_MTRRphysMask1 0x203 1362 #define MSR_MTRRphysBase2 0x204 1363 #define MSR_MTRRphysMask2 0x205 1364 #define MSR_MTRRphysBase3 0x206 1365 #define MSR_MTRRphysMask3 0x207 1366 #define MSR_MTRRphysBase4 0x208 1367 #define MSR_MTRRphysMask4 0x209 1368 #define MSR_MTRRphysBase5 0x20a 1369 #define MSR_MTRRphysMask5 0x20b 1370 #define MSR_MTRRphysBase6 0x20c 1371 #define MSR_MTRRphysMask6 0x20d 1372 #define MSR_MTRRphysBase7 0x20e 1373 #define MSR_MTRRphysMask7 0x20f 1374 #define MSR_MTRRphysBase8 0x210 1375 #define MSR_MTRRphysMask8 0x211 1376 #define MSR_MTRRphysBase9 0x212 1377 #define MSR_MTRRphysMask9 0x213 1378 #define MSR_MTRRphysBase10 0x214 1379 #define MSR_MTRRphysMask10 0x215 1380 #define MSR_MTRRphysBase11 0x216 1381 #define MSR_MTRRphysMask11 0x217 1382 #define MSR_MTRRphysBase12 0x218 1383 #define MSR_MTRRphysMask12 0x219 1384 #define MSR_MTRRphysBase13 0x21a 1385 #define MSR_MTRRphysMask13 0x21b 1386 #define MSR_MTRRphysBase14 0x21c 1387 #define MSR_MTRRphysMask14 0x21d 1388 #define MSR_MTRRphysBase15 0x21e 1389 #define MSR_MTRRphysMask15 0x21f 1390 #define MSR_MTRRfix64K_00000 0x250 1391 #define MSR_MTRRfix16K_80000 0x258 1392 #define MSR_MTRRfix16K_A0000 0x259 1393 #define MSR_MTRRfix4K_C0000 0x268 1394 #define MSR_MTRRfix4K_C8000 0x269 1395 #define MSR_MTRRfix4K_D0000 0x26a 1396 #define MSR_MTRRfix4K_D8000 0x26b 1397 #define MSR_MTRRfix4K_E0000 0x26c 1398 #define MSR_MTRRfix4K_E8000 0x26d 1399 #define MSR_MTRRfix4K_F0000 0x26e 1400 #define MSR_MTRRfix4K_F8000 0x26f 1401 #define MSR_CR_PAT 0x277 1402 #define MSR_MTRRdefType 0x2ff 1403 #define MSR_MC0_CTL 0x400 1404 #define MSR_MC0_STATUS 0x401 1405 #define MSR_MC0_ADDR 0x402 1406 #define MSR_MC0_MISC 0x403 1407 #define MSR_MC1_CTL 0x404 1408 #define MSR_MC1_STATUS 0x405 1409 #define MSR_MC1_ADDR 0x406 1410 #define MSR_MC1_MISC 0x407 1411 #define MSR_MC2_CTL 0x408 1412 #define MSR_MC2_STATUS 0x409 1413 #define MSR_MC2_ADDR 0x40a 1414 #define MSR_MC2_MISC 0x40b 1415 #define MSR_MC3_CTL 0x40c 1416 #define MSR_MC3_STATUS 0x40d 1417 #define MSR_MC3_ADDR 0x40e 1418 #define MSR_MC3_MISC 0x40f 1419 #define MSR_MC4_CTL 0x410 1420 #define MSR_MC4_STATUS 0x411 1421 #define MSR_MC4_ADDR 0x412 1422 #define MSR_MC4_MISC 0x413 1423 /* 0x480 - 0x490 VMX */ 1424 #define MSR_X2APIC_BASE 0x800 /* 0x800 - 0xBFF */ 1425 #define MSR_X2APIC_ID 0x002 /* x2APIC ID. (RO) */ 1426 #define MSR_X2APIC_VERS 0x003 /* Version. (RO) */ 1427 #define MSR_X2APIC_TPRI 0x008 /* Task Prio. (RW) */ 1428 #define MSR_X2APIC_PPRI 0x00a /* Processor prio. (RO) */ 1429 #define MSR_X2APIC_EOI 0x00b /* End Int. (W) */ 1430 #define MSR_X2APIC_LDR 0x00d /* Logical dest. (RO) */ 1431 #define MSR_X2APIC_SVR 0x00f /* Spurious intvec (RW) */ 1432 #define MSR_X2APIC_ISR 0x010 /* In-Service Status (RO) */ 1433 #define MSR_X2APIC_TMR 0x018 /* Trigger Mode (RO) */ 1434 #define MSR_X2APIC_IRR 0x020 /* Interrupt Req (RO) */ 1435 #define MSR_X2APIC_ESR 0x028 /* Err status. (RW) */ 1436 #define MSR_X2APIC_LVT_CMCI 0x02f /* LVT CMCI (RW) */ 1437 #define MSR_X2APIC_ICRLO 0x030 /* Int. cmd. (RW64) */ 1438 #define MSR_X2APIC_LVTT 0x032 /* Loc.vec.(timer) (RW) */ 1439 #define MSR_X2APIC_TMINT 0x033 /* Loc.vec (Thermal) (RW) */ 1440 #define MSR_X2APIC_PCINT 0x034 /* Loc.vec (Perf Mon) (RW) */ 1441 #define MSR_X2APIC_LVINT0 0x035 /* Loc.vec (LINT0) (RW) */ 1442 #define MSR_X2APIC_LVINT1 0x036 /* Loc.vec (LINT1) (RW) */ 1443 #define MSR_X2APIC_LVERR 0x037 /* Loc.vec (ERROR) (RW) */ 1444 #define MSR_X2APIC_ICR_TIMER 0x038 /* Initial count (RW) */ 1445 #define MSR_X2APIC_CCR_TIMER 0x039 /* Current count (RO) */ 1446 #define MSR_X2APIC_DCR_TIMER 0x03e /* Divisor config (RW) */ 1447 #define MSR_X2APIC_SELF_IPI 0x03f /* SELF IPI (W) */ 1448 1449 /* 1450 * VIA "Nehemiah" or later MSRs 1451 */ 1452 #define MSR_VIA_RNG 0x0000110b 1453 #define MSR_VIA_RNG_ENABLE 0x00000040 1454 #define MSR_VIA_RNG_NOISE_MASK 0x00000300 1455 #define MSR_VIA_RNG_NOISE_A 0x00000000 1456 #define MSR_VIA_RNG_NOISE_B 0x00000100 1457 #define MSR_VIA_RNG_2NOISE 0x00000300 1458 #define MSR_VIA_FCR 0x00001107 /* Feature Control Register */ 1459 #define VIA_FCR_ACE_ENABLE 0x10000000 /* Enable PadLock (ex. RNG) */ 1460 #define VIA_FCR_CX8_REPORT 0x00000002 /* Enable CX8 CPUID reporting */ 1461 #define VIA_FCR_ALTINST_ENABLE 0x00000001 /* Enable ALTINST (C3 only) */ 1462 1463 /* 1464 * AMD K6/K7 MSRs. 1465 */ 1466 #define MSR_K6_UWCCR 0xc0000085 1467 #define MSR_K7_EVNTSEL0 0xc0010000 1468 #define MSR_K7_EVNTSEL1 0xc0010001 1469 #define MSR_K7_EVNTSEL2 0xc0010002 1470 #define MSR_K7_EVNTSEL3 0xc0010003 1471 #define MSR_K7_PERFCTR0 0xc0010004 1472 #define MSR_K7_PERFCTR1 0xc0010005 1473 #define MSR_K7_PERFCTR2 0xc0010006 1474 #define MSR_K7_PERFCTR3 0xc0010007 1475 1476 /* 1477 * AMD K8 (Opteron) MSRs. 1478 */ 1479 #define MSR_SYSCFG 0xc0010010 1480 1481 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 1482 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 1483 #define EFER_LME 0x00000100 /* Long Mode Enable */ 1484 #define EFER_LMA 0x00000400 /* Long Mode Active */ 1485 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 1486 #define EFER_SVME 0x00001000 /* Secure Virtual Machine En. */ 1487 #define EFER_LMSLE 0x00002000 /* Long Mode Segment Limit E. */ 1488 #define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR En. */ 1489 #define EFER_TCE 0x00008000 /* Translation Cache Ext. */ 1490 1491 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 1492 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 1493 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 1494 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 1495 1496 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 1497 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 1498 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 1499 1500 #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ 1501 #define VMCR_DPD 0x00000001 /* Debug port disable */ 1502 #define VMCR_RINIT 0x00000002 /* intercept init */ 1503 #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ 1504 #define VMCR_LOCK 0x00000008 /* SVM Lock */ 1505 #define VMCR_SVMED 0x00000010 /* SVME Disable */ 1506 #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ 1507 1508 /* 1509 * These require a 'passcode' for access. See cpufunc.h. 1510 */ 1511 #define MSR_HWCR 0xc0010015 1512 #define HWCR_TLBCACHEDIS 0x00000008 1513 #define HWCR_FFDIS 0x00000040 1514 1515 #define MSR_NB_CFG 0xc001001f 1516 #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL 1517 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 1518 #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) 1519 1520 /* AMD Errata 1474. */ 1521 #define MSR_CC6_CFG 0xc0010296 1522 #define CC6_CFG_DISABLE_BITS (__BIT(22) | __BIT(14) | __BIT(6)) 1523 1524 #define MSR_LS_CFG 0xc0011020 1525 #define LS_CFG_ERRATA_1033 __BIT(4) 1526 #define LS_CFG_ERRATA_793 __BIT(15) 1527 #define LS_CFG_ERRATA_1095 __BIT(57) 1528 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 1529 #define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL 1530 #define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL 1531 #define LS_CFG_DIS_SSB_F17H 0x0000000000000400ULL 1532 1533 #define MSR_IC_CFG 0xc0011021 1534 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 1535 #define IC_CFG_DIS_IND 0x00004000 1536 #define IC_CFG_ERRATA_776 __BIT(26) 1537 1538 #define MSR_DC_CFG 0xc0011022 1539 #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 1540 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 1541 #define DC_CFG_ERRATA_261 0x01000000 1542 1543 #define MSR_BU_CFG 0xc0011023 1544 #define BU_CFG_ERRATA_298 0x0000000000000002ULL 1545 #define BU_CFG_ERRATA_254 0x0000000000200000ULL 1546 #define BU_CFG_ERRATA_309 0x0000000000800000ULL 1547 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 1548 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 1549 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 1550 1551 #define MSR_FP_CFG 0xc0011028 1552 #define FP_CFG_ERRATA_1049 __BIT(4) 1553 1554 #define MSR_DE_CFG 0xc0011029 1555 #define DE_CFG_ERRATA_721 0x00000001 1556 #define DE_CFG_LFENCE_SERIALIZE __BIT(1) 1557 #define DE_CFG_ERRATA_ZENBLEED __BIT(9) 1558 #define DE_CFG_ERRATA_1021 __BIT(13) 1559 1560 #define MSR_BU_CFG2 0xc001102a 1561 #define BU_CFG2_CWPLUS_DIS __BIT(24) 1562 1563 #define MSR_LS_CFG2 0xc001102d 1564 #define LS_CFG2_ERRATA_1091 __BIT(34) 1565 1566 /* AMD Family10h MSRs */ 1567 #define MSR_OSVW_ID_LENGTH 0xc0010140 1568 #define MSR_OSVW_STATUS 0xc0010141 1569 #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b 1570 #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020 1571 1572 /* X86 MSRs */ 1573 #define MSR_RDTSCP_AUX 0xc0000103 1574 1575 /* 1576 * Constants related to MTRRs 1577 */ 1578 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 1579 #define MTRR_N16K 16 1580 #define MTRR_N4K 64 1581 1582 /* 1583 * the following four 3-byte registers control the non-cacheable regions. 1584 * These registers must be written as three separate bytes. 1585 * 1586 * NCRx+0: A31-A24 of starting address 1587 * NCRx+1: A23-A16 of starting address 1588 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 1589 * 1590 * The non-cacheable region's starting address must be aligned to the 1591 * size indicated by the NCR_SIZE_xx field. 1592 */ 1593 #define NCR1 0xc4 1594 #define NCR2 0xc7 1595 #define NCR3 0xca 1596 #define NCR4 0xcd 1597 1598 #define NCR_SIZE_0K 0 1599 #define NCR_SIZE_4K 1 1600 #define NCR_SIZE_8K 2 1601 #define NCR_SIZE_16K 3 1602 #define NCR_SIZE_32K 4 1603 #define NCR_SIZE_64K 5 1604 #define NCR_SIZE_128K 6 1605 #define NCR_SIZE_256K 7 1606 #define NCR_SIZE_512K 8 1607 #define NCR_SIZE_1M 9 1608 #define NCR_SIZE_2M 10 1609 #define NCR_SIZE_4M 11 1610 #define NCR_SIZE_8M 12 1611 #define NCR_SIZE_16M 13 1612 #define NCR_SIZE_32M 14 1613 #define NCR_SIZE_4G 15 1614
Indexes created Sat Oct 03 00:25:10 UTC 2026