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History log of /src/sys/arch/x86/include/specialreg.h
RevisionDateAuthorComments
 1.220  24-Aug-2025  rillig x86/specialreg.h: remove redundant '\0' from snprintb format
 1.219  28-Apr-2025  riastradh xen: Stop-gap FPU PCB fix; disable Intel AMX for now.

Since the custom cpu_uarea_alloc/free are disabled under XENPV,
nothing would initialize struct pcb::pcb_savefpu to point either to
struct pcb::pcb_savefpusmall, or to a separately allocated large area
on machines with Intel AMX TILECFG/TILEDATA requiring it. So the
memset in fpu_lwp_fork would crash on null pointer dereference:

[ 1.0000030] uvm_fault(0xffffffff8094a300, 0x0, 2) -> e
[ 1.0000030] fatal page fault in supervisor mode
[ 1.0000030] trap type 6 code 0x2 rip 0xffffffff8062795c cs 0xe030 rflags 0x10202 cr2 0 ilevel 0 rsp 0xffffffff80adad38
[ 1.0000030] curlwp 0xffffffff8078f880 pid 0.0 lowest kstack 0xffffffff80ad62c0
kernel: page fault trap, code=0
Stopped in pid 0.0 (system) at netbsd:memset+0x2c: repe stosq %es:(%rdi)
memset() at netbsd:memset+0x2c
lwp_create() at netbsd:lwp_create+0x2f1
fork1() at netbsd:fork1+0x42c
main() at netbsd:main+0x44f

In order to support Intel AMX TILECFG/TILEDATA, or any other CPU
extensions that increase the XSAVE area beyond what fits in a single
page after struct pcb, we would need to enable the the custom
cpu_uarea_alloc/free. Currently that would imply allocating stack
guard pages (`redzone') under XENPV; if there's some reason the stack
guard pages don't work, we could also push #ifdef XENPV conditionals
into cpu_uarea_alloc/free to cover the guard pages -- to be
considered.

PR kern/59371: Xen domU uvm_fault since FPU state allocation patch

PR port-amd64/57661: Crash when booting on Xeon Silver 4416+ in
KVM/Qemu
 1.218  24-Apr-2025  riastradh amd64: Enable TILECFG and TILEDATA registers.

This allows processes to use the registers, and NetBSD will save and
restore them in context switches. But it does not expose them to
ptrace(2) or debuggers like all the other extended CPU state
(xmm/ymm/zmm) -- that will require more work.

PR kern/57661: Crash when booting on Xeon Silver 4416+ in KVM/Qemu
PR port-amd64/59299: Support Intel AMX CPU state (TILECFG/TILEDATA)
 1.217  24-Apr-2025  riastradh x86: Add some more XCR0 bits and references.

PR port-amd64/57661: Crash when booting on Xeon Silver 4416+ in
KVM/Qemu
 1.216  19-Oct-2024  msaitoh x86/specialreg.h: Update AMD CPUID definitions.

- Add AMD Hetero Workload Classification.
- Extend the number of UMC PMCs field from 6bit to 8bit.
- Add Guest Intercept Control for SEV-ES.
- Add Segmented RMP
 1.215  17-Oct-2024  msaitoh x86/specialreg.h: Update AMD CPUID definitions.

Update definitions from the following PPR:
- PPR for AMD Family 19h Model 11h, Revision B2 Processors
(Doc ID 55901 rev. 0.47)
- PPR for AMD Family 1Ah Model 02h, Revision C1 Processors
(Doc ID 57238 rev.0.24)
- PPR for AMD Family 1Ah Model 24h, Revision B0 Processors
(Doc ID 57274 rev. 3.00)

- Rename CPUID Fn8000001b EDX bit 11 from IbsL3MissFiltering to
Zen4IbsExtension.
- Add some CPUID bits.
 1.214  06-Oct-2024  msaitoh Add some unknown CPUID bits for AMD.
 1.213  06-Oct-2024  msaitoh Add some CPUID bits for AMD.
 1.212  01-Jul-2024  andvar Disable the VIA Alternate Instructions according the VIA documentation:
* C7 and above do not support ALTINST, do not check or attempt to disable them.
* For VIA C3 Nehemiah check extended feature flags for support and status,
do no attempt to disable when AIS is not supported or enabled.
* For pre-Nehemiah models explicitly disable, if they are in the range
of documented models, flags aren't present to check the status on these models.
Note: for pre-Nehemiah may be other functional side effects depdending
on the version and stepping.

Explicit disabling of ALTINST was introduced with rev. 1.84 following
the discovery of some VIA CPUs having these instructions enabled by default
leading to the potential backdoor (aka rosenbrindge).

Unfortunately, implementation used a wrong check (ACE supported flag),
which can be true for the later models, still supporting padlock features.
Setting ALTINST bit on those may have unexpected side effects like VIA C7 CPUID
instruction for temperature sensor not reporting correct value or
`cpuctl identify' not reporting certain CPU features. Similar side effects
can be observed even for Nehemiah models not supporting AIS instructions. This
change should limit possibility of such issues to only the pre-Nehemiah models,
not covered at all in the previous implementation.

Feature Control Register (FCR) macros were unified under one group and
consistent naming while implementing the change. Few comments updated as well.

patch reviewed by Riastradh@ (thank you)

need pullups to netbsd-9, 10.

PR kern/58370
 1.211  12-May-2024  msaitoh branches: 1.211.2;
s/RPMQUERY/RMPQUERY/
 1.210  08-Mar-2024  rillig cpuctl: fix i386 bit descriptions for CPUID_SEF_FLAGS1

warning: non-printing character '\31' in description
'BUS_LOCK_DETECT""b\31' [363]
 1.209  27-Oct-2023  mrg add MSR stuff for AMD errata 1474.
 1.208  27-Jul-2023  msaitoh Add AMD IBPB_RET and BusLockThreshold.
 1.207  25-Jul-2023  mrg x86: turn off zenbleed chicken bit on Zen2 cpus.

this is based upon Taylor's original work. i just made the list
of CPUs to run on correct as i could determine. (also, add some
Zen3 and Zen4 cpuids not yet used by any errata.)

(might be nice to have a better way to expression revision ranges
rather than specific cpuid matches, eg, 0x30-0x4f models in a cpu
family, etc.)

tested on ryzen 3600, and a ported zenbleed PoC that no longer
shows any obtained text. (a similar module-version of it stopped
the PoC on a ryzen 3950x without having to reboot.)

https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7008.html
https://lock.cmpxchg8b.com/zenbleed.html
 1.206  11-Apr-2023  msaitoh Fix compile error.
 1.205  11-Apr-2023  msaitoh Add CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT.
 1.204  25-Mar-2023  andvar s/Predective/Predictive/ and s/dedected/detected/ in comments.
 1.203  17-Feb-2023  msaitoh Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.
 1.202  14-Feb-2023  msaitoh Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.
 1.201  30-Dec-2022  msaitoh Fix comment.
 1.200  30-Dec-2022  msaitoh Update definitions from the latest Intel SDM.

- Rename HW_FEEDBACK to HWI (Hardware Feedback Interface).
- Add CPUID Fn0000_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25 Hardware
Feedback Notification support.
- Add CPUID Fn0000_0007 %ecx bit 29 ENQCMD.
- Add CPUID Fn0000_0007 %edx bit 1 SGX-KEYS.
- Add CPUID Fn0000_0007 %edx bit 5 UINTR(User INTeRrupts).
- Add CPUID Fn0000_0007 %edx bit 1 RTM_ALWAYS_ABORT.
- Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT.
- Add CPUID Fn0000_0007 %edx bit 22 AMX_BF16.
- Add CPUID Fn0000_0007 %edx bit 23 AVX512_FP16.
- Add CPUID Fn0000_0007 %edx bit 24 AMX_TILE.
- Add CPUID Fn0000_0007 %edx bit 25 AMX_INT8.
- Add CPUID Fn0000_0007 sub-leaf 1 %edx bit 18 CET_SSS.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 0 PSFD.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 1 IPRED_CTRL.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 2 RRSBA_CTRL.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 3 DDPD_U.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 4 BHI_CTRL.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 5 MCDT_NO.
- Modify comment. Both Intel and AMD support CPUID Fn0000000b.
- Add CPUID Fn0000_000d sub-leaf 1 %eax bit 4 XFD.
- Modify comment. Hybrid Information -> Native Model ID Information.
- Add CPUID Fn0000_001d Tile Information.
- Add CPUID Fn0000_001e TMUL Information.
 1.199  27-Dec-2022  msaitoh Use __BIT(). Add comment. Whitespace. No functional change.
 1.198  21-Nov-2022  msaitoh branches: 1.198.2;
Update AMD CPUID Fn8000_001b

- Add IbsFetchCtlExtd and IbsOpData4.
- Fix typo (lbs -> Ibs).
 1.197  16-Nov-2022  msaitoh Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.
 1.196  16-Nov-2022  msaitoh Add CPUID Fn8000_0021 AMD Extended Features Identification 2.
 1.195  16-Nov-2022  msaitoh Add Some definitions from AMD APM:

- Add CPUID Fn8000_0007 %eax RAS capabilities.
- Add CPUID Fn8000_001b Instruction-Based Sampling capabilities.
- Add BTC_NO, ROGPT, RPMQUERY, VmplSSS, TscAuxVirt, VmgexitParam,
VirtualTomMsr, bsVirtGuest, SmtProtection, vsmCommPageMSR and
NestedVirtSnpMsr.
 1.194  19-Oct-2022  msaitoh Add AMD cpuid Fn8000_000a x2AVIC, VNMI and IBSVIRT from APM Vol. 3 Rev. 3.34.
 1.193  12-Oct-2022  msaitoh Add CPUID Fn8000_001e Processor Topology Information.
 1.192  06-Oct-2022  msaitoh Update some AMD CPUID bits:

- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().
 1.191  15-Jun-2022  msaitoh Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.
 1.190  13-Jun-2022  msaitoh Add top-down slots event bit of architectural performance monitoring leaf.
 1.189  01-Feb-2022  msaitoh s/shareing/sharing/. No functional change.
 1.188  29-Jan-2022  msaitoh Add Intel Hybrid Information Enumeration (CPUID Fn0000_001a).
 1.187  17-Jan-2022  andvar fix typos in comments, mainly s/foward/forward/.
 1.186  15-Jan-2022  msaitoh Add Some definitions from AMD APM:

- CPUID Fn80000001 %ecx bit 30 AddrMaskExt.
- CPUID Fn80000008 %ebx bit 13 INT_WBINVD.
- CPUID Fn80000008 %ebx bit 19 IbrsSameMode.
- CPUID Fn80000008 %ebx bit 20 EferLmsleUnsupported.
- CPUID Fn80000008 %ebx bit 28 PSFD.
- CPUID Fn80000008 %edx bit 30 as "B30". Not documented.
- CPUID Fn8000001f %eax bit 8 SecureTSC.
- CPUID Fn8000001f %eax bit 24 VmsaRegProt.
- Tested by nonaka@.
 1.185  15-Jan-2022  msaitoh Whitespace. No functional change.
 1.184  15-Jan-2022  msaitoh Move CPUID_CAPEX_FLAGS next to %eax because it's for %eax.
 1.183  15-Jan-2022  msaitoh No functional change.

- Modify comment. Add comment. Fix typo. Mainly taken from dragonfly.
- Use __BIT().
 1.182  14-Jan-2022  msaitoh Add Architectural LBR and Linear Address Masking.
 1.181  14-Jan-2022  msaitoh Both Intel and AMD says the name of CPUID 0x01 %edx bit 19 is "CLFSH".
 1.180  13-Jan-2022  msaitoh Add some CPUID bits from the latest Intel SDM.

- Last Branch Record.
- Thread Director.
- AVX version of VNNI.
- Fast short REP MOV.
- HRESET.
- PPIN.
 1.179  13-Jan-2022  msaitoh Use __BIT(). KNF. No functional change.
 1.178  30-Sep-2021  msaitoh Print CPUID_PBE (Pending Break Enable) with "PBE".
 1.177  10-Jul-2021  msaitoh Add some definitions from Intel SDM:

- CPUID leaf 7:0 %ecx bit 13 TME_EN (Total Memory Encryption)
- CPUID leaf 7:0 %edx bit 18 PCONFIG (Platform CONFIGuration)
 1.176  24-Nov-2020  msaitoh branches: 1.176.4;
Add some definitions from the latest Intel SDM:

- Add CPUID leaf 7 %edx bit 23 "KL" (Key Locker).
- Add CPUID leaf 7 subleaf 1 %eax bit 5 "AVX512_BF16".
 1.175  07-Sep-2020  jakllsch branches: 1.175.2;
Fix printb string for LA57
 1.174  07-Sep-2020  msaitoh Add CPUID(EAX=07H, ECX=0) ECX bit 16 LA57 from maxv.
 1.173  05-Sep-2020  maxv x86: fix several CPUID flags

- Rename: CPUID_PN -> CPUID_PSN
CPUID_CFLUSH -> CPUID_CLFSH
CPUID_SBF -> CPUID_PBE
CPUID_LZCNT -> CPUID_ABM
CPUID_P1GB -> CPUID_PAGE1GB
CPUID2_PCLMUL -> CPUID2_PCLMULQDQ
CPUID2_CID -> CPUID2_CNXTID
CPUID2_xTPR -> CPUID2_XTPR
CPUID2_AES -> CPUID2_AESNI
To match the x86 specification and the other OSes.

- Remove: CPUID_B10, CPUID_B20, CPUID_IA64. They do not exist.
 1.172  04-Sep-2020  maxv Add a few more CPUID flags.
 1.171  05-Aug-2020  maxv Add new fields here and there.
 1.170  20-Jul-2020  maxv Revert previous, to unbreak the build (NVMM declares the macro too).

There are hundreds of MSRs, we're not going to list them all, especially
when the majority are unused.
 1.169  19-Jul-2020  jdolecek add definition for MSR_IA32_FEATURE_CONTROL, just for information
 1.168  18-Jun-2020  maxv style and fix typo
 1.167  10-Jun-2020  msaitoh Add SRBDS_CTRL bit.
 1.166  01-Jun-2020  msaitoh Add some definitions from the latest Intel SDM plus small fix:

- Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and IA32_PACKAGE_TERM* MSRs.
- Add CPUID leaf 7 %ecx bit 31 for Protection Keys.
- Add definition of Load only TLB and Store only TLB.
- Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES
- Fix HWP_IGNIDL.
 1.165  28-May-2020  msaitoh Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE.
This bit makes lfence instruction serializing.
 1.164  01-May-2020  msaitoh - Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit.
- Modify comment.
 1.163  25-Apr-2020  bouyer Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVM
guests in GENERIC.
Xen support can be disabled at runtime with
boot -c
disable hypervisor
 1.162  24-Apr-2020  msaitoh - AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL".
- Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory
features.
 1.161  06-Apr-2020  msaitoh branches: 1.161.2;
Rename CPUID_APM_TSC to CPUID_APM_ITSC. No functional change.
 1.160  06-Apr-2020  msaitoh CPUID Fn00000001 %edx bit 8 is printed as "TSC", so rename CPUID Fn8000_0007
%edx bit 8 from "TSC" to "ITSC" (Invariant TSC) to avoid confusion.
 1.159  01-Apr-2020  msaitoh Add AVX512_VP2INTERSECT, SERIALIZE and TSXLDTRK(TSX suspend load addr tracking)
 1.158  17-Nov-2019  msaitoh Add the following bit definitions from the latest Intel SDM:
- CET shadow stack
- Fast Short REP MOV
- Hybrid part
- CET Indirect Branch Tracking
 1.157  12-Nov-2019  maxv Mitigation for CVE-2019-11135: TSX Asynchronous Abort (TAA).

Two sysctls are added:

machdep.taa.mitigated = {0/1} user-settable
machdep.taa.method = {string} constructed by the kernel

There are two cases:

(1) If the CPU is affected by MDS, then the MDS mitigation will also
mitigate TAA, and we have nothing else to do. We make the 'mitigated' leaf
read-only, and force:
machdep.taa.mitigated = machdep.mds.mitigated
machdep.taa.method = [MDS]
The kernel already enables the MDS mitigation by default.

(2) If the CPU is not affected by MDS but is affected by TAA, then we use
the new TSX_CTRL MSR to disable RTM. This MSR is provided via a microcode
update, now available on the Intel website. The kernel will automatically
enable the TAA mitigation if the updated microcode is present. If the new
microcode is not present, the user can load it via cpuctl, and set
machdep.taa.mitigated=1.
 1.156  30-Oct-2019  msaitoh - GMET is not bit 11 but 17.
- Add unknown CPUID Fn8000_000a %edx bit 20.
 1.155  08-Oct-2019  msaitoh Fix AMD Fn8000_0001f %eax bit 0's name.
 1.154  03-Oct-2019  msaitoh - Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.
 1.153  26-Sep-2019  msaitoh Define CPUID_CAPEX_FLAGS's bit 10 correctly.
 1.152  09-Sep-2019  msaitoh Add MCOMMIT instruction.
 1.151  30-Aug-2019  msaitoh Add definitions of AMD's CPUID Fn8000_0008 %ebx.
 1.150  26-Jul-2019  msaitoh branches: 1.150.2;
- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?
 1.149  13-Jul-2019  msaitoh Define some new bits of CPUID Fn8000_0007 %edx AMD Advanced Power Management
leaf.
 1.148  26-Jun-2019  mgorny Fetch XSAVE area component offsets and sizes when initializing x86 CPU

Introduce two new arrays, x86_xsave_offsets and x86_xsave_sizes,
and initialize them with XSAVE area component offsets and sizes queried
via CPUID. This will be needed to implement getters and setters for
additional register types.

While at it, add XSAVE_* constants corresponding to specific XSAVE
components.
 1.147  29-May-2019  maxv Add PCID support in SVS. This avoids TLB flushes during kernel<->user
transitions, which greatly reduces the performance penalty introduced by
SVS.

We use two ASIDs, 0 (kern) and 1 (user), and use invpcid to flush pages
in both ASIDs.

The read-only machdep.svs.pcid={0,1} sysctl is added, and indicates whether
SVS+PCID is in use.
 1.146  18-May-2019  maxv Clean up a little, add new XCR0 bits, remove a few unused MSRs, and fix
typos.
 1.145  14-May-2019  msaitoh Add snprintb's string for cpuid7 edx bit 10 "MD_CLEAR".
 1.144  14-May-2019  maxv Mitigation for INTEL-SA-00233: Microarchitectural Data Sampling (MDS).

It requires a microcode update, now available on the Intel website. The
microcode modifies the behavior of the VERW instruction, and makes it flush
internal CPU buffers. We hotpatch the return-to-userland path to add VERW.

Two sysctls are added:

machdep.mds.mitigated = {0/1} user-settable
machdep.mds.method = {string} constructed by the kernel

The kernel will automatically enable the mitigation if the updated
microcode is present. If the new microcode is not present, the user can
load it via cpuctl, and set machdep.mds.mitigated=1.
 1.143  13-Mar-2019  msaitoh Add TSX_FORCE_ABORT related definitions.
 1.142  09-Mar-2019  maxv Start replacing the x86 PTE bits.
 1.141  16-Feb-2019  maxv Handle MSR_MISC_ENABLE on NVMM-Intel (Intel-specific).
 1.140  11-Feb-2019  cherry We reorganise definitions for XEN source support as follows:

XEN - common sources required for baseline XEN support.
XENPV - sources required for support of XEN in PV mode.
XENPVHVM - sources required for support for XEN in HVM mode.
XENPVH - sources required for support for XEN in PVH mode.
 1.139  08-Feb-2019  msaitoh Fix bitstring format of Intel CPUID Architectural Performance Monitoring
Fn0000000a %ebx.
 1.138  05-Feb-2019  msaitoh Add new CPUID flags WAITPKG, CLDEMOTE, MOVDIRI, MOVDIR64B and
IA32_CORE_CAPABILITIES from the latest Intel SDM.
 1.137  13-Jan-2019  maxv Forgot to commit file along with identcpu.c::rev1.86.
 1.136  26-Nov-2018  msaitoh Add Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.
 1.135  22-Nov-2018  msaitoh Add Intel/AMD MONITOR/MWAIT leaf.
 1.134  21-Nov-2018  msaitoh Add Intel CPUID Extended Topology Enumeration Fn0000000b definitions.
 1.133  21-Nov-2018  msaitoh Modify comment. No functional change:
- AMD also has CPUID 0x06 and 0x0d.
- PCOMMIT was obsoleted.
 1.132  15-Nov-2018  msaitoh Add MAWAU (for BND{LD,ST}X instruction) from the latest Intel SDM.
 1.131  10-Nov-2018  maxv Declare the MSR_VIA_ACE values as macros, and use a consistent naming,
similar to the rest of the file.

I'm wondering if I'm not fixing a huge bug here. The ECX8 value we were
using was wrong: ECX8 is bit 1, not bit 0. Bit 0 is ALTINST, an alternate
ISA, which is now known to be backdoored.

So it looks like we were explicitly enabling the backdoor.

Not tested, because I don't have a VIA cpu.
 1.130  20-Aug-2018  msaitoh OK'd by maxv:
- Add cpuid 7 edx L1D_FLUSH bit.
- Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
- Add IA32_FLUSH_CMD MSR.
 1.129  07-Aug-2018  maxv Add five errata for AMD Family 17h (Ryzen etc), tested by Patrick Welche,
thanks. Also add two errata for Family 16h, not yet tested, so not yet
enabled.
 1.128  13-Jul-2018  maxv Remove the X86PMC code I had written, replaced by tprof. Many defines
become unused in specialreg.h, so remove them. We don't want to add
defines all the time, there are countless PMCs on many generations, and
it's better to just inline the event/unit values.
 1.127  04-Jul-2018  maya Disable MWAIT/MONITOR on Apollo Lake CPUs to workaround APL30 errata.

We use MWAIT/MONITOR to hatch secondary CPUs. The errata means that
the wakeup may not happen, so SMP boot fails.
Use wrmsr to disable it in hardware too, for extra paranoia.

PR port-amd64/53420,
also reported on netbsd-users by joern clausen and ssartor.
 1.126  31-May-2018  msaitoh branches: 1.126.2;
Fix the bit location of SSBD in the macro for snprintb.
 1.125  23-May-2018  maxv Clean up the FPU headers.
 1.124  22-May-2018  maxv Extend the AMD NONARCH method to family 17h. The AMD spec states that for
17h care must be taken when handling sibling threads.

The concern is that if we have a protected two-thread process running on
two siblings, and context switch one thread to another unprotected thread,
disabling the SSB protection on one logical core will disable SSB on its
sibling too (which is still running the protected thread).

All of that doesn't matter to us, because the SSB value we set is
system-wide, not per-process.
 1.123  22-May-2018  maxv Implement a mitigation for SpectreV4 on AMD families 15h and 16h. We use
a non-architectural MSR. This MSR is also available on 17h, but there SMT
is involved, and it needs more investigation.

Not tested (I have only 10h).
 1.122  22-May-2018  maxv Add RSBA. When set, it indicates that the CPU is vulnerable to SpectreV2
via the RSB.
 1.121  22-May-2018  maxv Mitigation for SpectreV4, based on SSBD. The following sysctl branches
are added:

machdep.spectre_v4.mitigated = {0/1} user-settable
machdep.spectre_v4.affected = {0/1} set by the kernel

The mitigation is not enabled by default yet. It is not tested either,
because no microcode update has been published yet.

On current CPUs a microcode/bios update must be applied for SSBD to be
available. The user can then set mitigated=1. Even with an update applied
the kernel will set affected=1.

On future CPUs, where the problem will presumably be fixed by default,
the CPU will report SSB_NO, and the kernel will set affected=0. In this
case we also have mitigated=0, but the mitigation is not needed.

For now the feature is system-wide. Perhaps we will want a more
fine-grained, per-process approach in the future.
 1.120  30-Mar-2018  maxv Add RDCL_NO and IBRS_ALL.
 1.119  30-Mar-2018  msaitoh Add Some bit definitions of AMD Fn80000001 %edx:
- MMX
- FXSR
 1.118  30-Mar-2018  msaitoh From the latest Intel SDM:
- Add Intel Fn0000_0006 %eax new bit 14-20 (HWP stuff).
- Intel Fn0000_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.
 1.117  14-Mar-2018  maxv ... and also add IBPB ...
 1.116  14-Mar-2018  maxv Add the IBRS and STIBP MSRs.
 1.115  14-Mar-2018  maxv Add IC_CFG.DIS_IND: "Disable Indirect Branch Predictor". Available (at
least) on AMD Families 10h, 12h and 16h.
 1.114  12-Mar-2018  msaitoh s/CLFUSH/CLFLUSH/
No functional change.
 1.113  08-Mar-2018  msaitoh Sort entries. No functional change.
 1.112  05-Mar-2018  msaitoh branches: 1.112.2;
Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.
 1.111  15-Jan-2018  msaitoh Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.
 1.110  15-Jan-2018  msaitoh Add MSR_IA32_ARCH_CAPABILITIES definition.
 1.109  15-Jan-2018  msaitoh - Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add comment.
 1.108  13-Jan-2018  jdolecek fix swapped comments for EFER LME and LMA
 1.107  10-Jan-2018  msaitoh Add Intel cpuid 7 %edx IBRS(IBPB Speculation Control) and
STIBP(STIBP Speculation Control) from OpenBSD.
 1.106  10-Jan-2018  msaitoh Add comment.
 1.105  19-Oct-2017  msaitoh Add the following bits in AMD Fn8000000a %edx features (SVM features):
PFThreshold (PAUSE filter threshold)
AVIC (AMD virtual interrupt controller)
V_VMSAVE_VMLOAD (virtualized VMSAVE and VMLOAD)
vGIF (virtualized GIF)
 1.104  18-Oct-2017  msaitoh Add Turbo Boost Max Technology 3.0 bit.
 1.103  13-Oct-2017  msaitoh Add the following instruction bits in Structured Extended Flags Enumeration
Leaf from "Intel Architecture Instruction Set Extensions and Future Features
Programming Reference" (319433-030):
AVX512_IFMA
AVX512_VBMI
AVX512_VBMI2
GFNI
VAES
VPCLMULQDQ
AVX512_VNNI
AVX512_BITALG
AVX512_VPOPCNTDQ
AVX512_4VNNIW
AVX512_4FMAPS
 1.102  07-Sep-2017  msaitoh Define CPUID Fn00000001 %ebx bits and use them. No functional change.
 1.101  11-Aug-2017  maxv Add a comment about APICBASE_PHYSADDR. Has to do with PR/42597.
 1.100  11-Jul-2017  gson Fix typo in comment
 1.99  14-Jun-2017  maxv Add EFER_TCE. This would be an interesting feature to have, since it
reduces the indirect cost of invlpg; but I'm not convinced the way we
flush upper-levels is correct for this yet.
 1.98  15-May-2017  msaitoh branches: 1.98.2;
CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify comments
and snprintb() sring.
 1.97  22-Apr-2017  nonaka branches: 1.97.2;
move LAPIC_MSR* to specialreg.h.
 1.96  22-Apr-2017  nonaka Add x2APIC register definitions.
 1.95  11-Mar-2017  maxv Add the AMD 10h family, with additional events that I believe are useful,
the DTLB misses on large pages for example.

While here, remove a few K7 flags that do not actually exist on K7 (there
must have been a confusion between K7 and K8); and make the 'pmc list'
command a little more user-friendly.
 1.94  18-Feb-2017  maxv Add the AMD 10h family PMC values. Some values depend on the CPU revision,
they are commented out. Several other values are common with K7, we could
merge them later.

This family of CPUs has a 12bit event selector, contrary to K7 (8bit). The
thing is, i386's PMC interface takes as argument a uint8_t from userland,
so these counters are not accessible (yet).
 1.93  11-Feb-2017  maxv Fix a few (unused) MSR values, and add some others that I believe are
relevant.

From Murray Armfield (PR/42861).
 1.92  02-Feb-2017  msaitoh Modify comment. Use long form.
 1.91  08-Dec-2016  msaitoh branches: 1.91.2;
Add CLWB bit.
 1.90  05-Dec-2016  msaitoh Fix CPUID_SEF_FLAGS. Octal value has no 8.
 1.89  19-Aug-2016  maxv KNF so NXR likes it, and some typos
 1.88  16-Jul-2016  maxv Add the cr4 flags for PKE and UMIP.
 1.87  27-Apr-2016  msaitoh branches: 1.87.2;
Add some bit definitions mainly taken from the latest Intel SDM:
- Add SGX, UMIP, RDPID and SGXLC.
- Add avx512dq, avx512bw and avx512vl.
Fix the bit location of CLFLUSHOPT.
 1.86  13-Jan-2016  msaitoh Add some AMD's bit definitions from "BIOS and Kernel Developer(BKDG) for AMD
Family 15h Models 60h-6Fh Processors".
 1.85  08-Jan-2016  msaitoh Add CLFLUSHOPT bit.
 1.84  08-Jan-2016  msaitoh Add x86 FPU Data Pointer Updated Only bit from Intel SDM.
 1.83  14-Aug-2015  msaitoh - Add Hardware-Controlled Performance States (HWP) bits.
- Use __BIT()
 1.82  08-May-2015  msaitoh From Intel SDM:
- Add the Silicon Debug bit in CPUID Fn00000001 %ecx
- Add CPUID Fn0000_0007 %ecx bits
- Add comments.
 1.81  12-Dec-2014  msaitoh Use specialreg.h's definitions.
 1.80  11-Sep-2014  msaitoh branches: 1.80.2;
- Add two more bit definitions
- XINUSE -> XGETBV
 1.79  09-Sep-2014  msaitoh Update CPUID(EAX=0x0d, ECX=1) from Intel SDM:
- XSAVEC(bit1)
- XGETBV(bit2)
- XSAVES(bit3)
 1.78  25-Feb-2014  dsl branches: 1.78.4;
Add the XCR bits for snazzy upcoming features.
Define a mask for the fpu releated ones - only these wll be enabled.
The memory bound ones will need saving on every context switch.
 1.77  04-Jan-2014  msaitoh Add Energy Performance Bias bit.
 1.76  04-Jan-2014  msaitoh Remove duplicated entry. Modify comments a bit.
 1.75  25-Dec-2013  msaitoh move XCR0 definitions to next to CR0's.
 1.74  08-Dec-2013  dsl Add some definitions for cpu 'extended state'.
These are needed for support of the AVX SIMD instructions.
Nothing yet uses them.
 1.73  20-Nov-2013  msaitoh - Add some AMD Fn80000001 extended features %ecx bits definitions from
the document (AMD64 Architecture ProgrammerVolume 3: General-Purpose and
System Instructions. Document revision 3.20)

- "s/MXX/MMXX/" because this bit is "MMX eXtention".
 1.72  15-Nov-2013  msaitoh Modify some macros and add some new macros for CPU family and model
to reduce code duplication and to avoid bug.

CPUID_TO_STEPPING(cpuid) (not changed)

CPUID_TO_FAMILY(cpuid) (new)
CPUID_TO_MODEL(cpuid) (new)

Return the display family and the display model.
The macro names are the same as FreeBSD.

CPUID_TO_BASEFAMILY(cpuid) (The old name was CPUID2FAMILY)
CPUID_TO_BASEMODEL(cpuid) (The old name was CPUID2MODEL)

Only for the base field.

CPUID_TO_EXTFAMILY(cpuid) (The old name was CPUID2EXTFAMILY)
CPUID_TO_EXTMODEL(cpuid) (The old name was CPUID2EXTMODEL)

Only for the extended field.

See http://mail-index.netbsd.org/port-amd64/2013/11/12/msg001978.html
 1.71  21-Oct-2013  msaitoh - Add Intel Deterministic Cache Parameter Leaf (CPUID leaf 4).
This definitions are required to know cache information of
newer Intel CPU.
- Fix comment.
 1.70  04-Oct-2013  msaitoh Sort definitions. No functional change.
- CPUID_FEAT_BLACKLIST is for Fn00000001 %edx, so move it.
- Sort CPUID definitions with initial EAX value.
 1.69  04-Oct-2013  msaitoh Add comment about CPUID Processor extended state Enumeration Fn0000000d %eax.
 1.68  14-Sep-2013  msaitoh Add some definitions of Intel's cpuid feature from the latest document.
 1.67  12-Aug-2013  drochner add feature flag definitions for the last round of Intel instruction
set extensions (AVX512 et al.)
 1.66  26-Jul-2013  msaitoh Style change.
 1.65  25-Jul-2013  msaitoh Add some new bit definitions of Structured Extended Feature Flags Enumeration
Leaf from the document (Intel 64 and IA-32 Architectures Software Developer's
Manual).
 1.64  25-Jul-2013  msaitoh Fix the bit positions in CPUID_SEF_FLAGS macro. On snprintb(), position 1
means LSB(bit0). The bit position from HLE to SMAP was 1 bit right shifted.
The bit position of BMI1 was completely wrong.
 1.63  06-Mar-2013  yamt branches: 1.63.6;
some more definitions
 1.62  06-Jan-2013  dsl Correct the comment about the extended family and model bits.
Add some definitions related to the process extended state enumeration.
 1.61  03-Jan-2013  dsl Add some missing bit definitions to CPUID2 and those for XCR0.
Taken from the August 2012 Intel SDM (intel_x86_325462.pdf).
Split all the snprintb() format strings to make them (almost) readable.
Fix CPUID_AMD_FLAGS4 to not try to print bits \41 and \42.
 1.60  17-Oct-2012  drochner recognize the P1GB and RDTSCP which were AMD-only on Intel HW too
 1.59  05-May-2012  jym branches: 1.59.2;
Add latest CR4 bits:
- CR4_VMXE: VMX operations, used for hardware virtualization.
- CR4_SMXE: SMX operations, used for safer Mode Extensions (ground for
Intel's TXT - Trusted Execution Technology - platform).
- CR4_FSGSBASE: enable *FSBASE and *GSBASE instructions, for R/W access
to FS/GS segment base addresses.
- CR4_PCIDE: enable Process Context IDentifiers (other architectures may call
these "address space identifiers").
- CR4_OSXSAVE: enable xsave and xrestore instructions
- CR4_SMEP: Supervisor Mode Execution Prevention. Allows enforcing --x rights
from cpl 0.

From Intel® 64 and IA-32 Architectures Software Developer’s Manual,
March 2012.

Align declarations.

CPUID_* bits for these features follow.
 1.58  30-Apr-2012  christos Add VIA Eden FCR MSR.
 1.57  06-Apr-2012  chs bring in this change from openbsd:
Implement the AMD suggested workaround for family 10h & 12h errata 721
"Processor May Incorrectly Update Stack Pointer" by setting a bit
marked 'reserved' in an MSR that is only "documented" to exist on 12h.
 1.56  02-Mar-2012  bouyer Don't mask out CPUID_FXSR. If not set, the kernel won't handle SSE and SSE2
registers on context switches; leading to data corruption when running
binaries using these instructions (like e.g. binaries built with a
-mcpu newer than pentium 4, which enables theses instruction in gcc).
 1.55  15-Dec-2011  abs branches: 1.55.2;
Increase MTRR_I686_NVAR_MAX from 8 to 16. Avoids
"FIXME: more than 8 MTRRs (10)" message on booting Thinkpad W520 and
similar. While here replace a magic number with MTRR_I686_NVAR_MAX * 2
 1.54  09-Dec-2011  cegger add AMD ucode MSRs
 1.53  03-Oct-2011  njoly branches: 1.53.2; 1.53.6;
Do not redefine CPUID_LAHF.
 1.52  26-Jul-2011  yamt - add PCID
- comment
 1.51  20-Feb-2011  jruoho Add MSR_TEMPERATURE_TARGET.
 1.50  15-Feb-2011  cegger update cpuid bits
 1.49  12-Oct-2010  jakllsch branches: 1.49.2; 1.49.4;
Correct another off-by-one-bit error. This time for Erratum 97.
 1.48  18-Sep-2010  jakllsch AMD publication 25759 rev 3.69 says that DisIOReqLock in NB_CFG is "bit 3".
They probably mean "bit 3" and not "the third bit" (or bit 2).
This change should prevent superfluous warnings of errata 89.
 1.47  25-Aug-2010  jruoho Add definitions for Intel Digital Thermal Sensor and Power Management, at
CPUID Fn0000_0006, %eax, %ecx. Use these instead of magic numbers.
 1.46  21-Aug-2010  jruoho Add IA32_MPERF (E7h) and IA32_APERF (E8h) as MSR_MPERF and MSR_APERF.
 1.45  21-Aug-2010  jruoho Add CPUID_APM_CPB at Fn8000_0007 %edx, for core performance boost.
 1.44  29-Jul-2010  cegger add RDTSCP_AUX MSR
 1.43  24-Jul-2010  cegger add AMD OSVW MSRs
 1.42  06-Jul-2010  cegger Turn PMAP_NOCACHE into MI flag.
Add MI flags PMAP_WRITE_COMBINE, PMAP_WRITE_BACK, PMAP_NOCACHE_OVR.
Update pmap(9) manpage.

hppa: Remove MD PMAP_NOCACHE flag as it exists as MI flag
mips: Rename MD PMAP_NOCACHE to PGC_NOCACHE.

x86: Implement new MI flags using Page-Attribute Tables.
x86: Implement BUS_SPACE_MAP_PREFETCHABLE.

Patch presented on tech-kern@:
http://mail-index.netbsd.org/tech-kern/2010/06/30/msg008458.html

No comments on this last version.
 1.41  04-May-2010  jym Enable the NX bit feature for Xen i386pae and amd64 kernels.

Tested with Xen 3.1 and Xen 3.3, dom0 and domU, by bouyer@ and jym@.

Ok bouyer@.
 1.40  18-Apr-2010  jym This patch fixes the NX regression issue observed on amd64 kernels, where
per-page execution right was disabled (therefore leading to the inability
of the kernel to detect fraudulent use of memory mappings marked as not
being executable).

- replace cpu_feature and ci_feature_flags variables by cpu_feature and
ci_feat_val arrays. This makes it cleaner and brings kernel code closer
to the design of cpuctl(8). A warning will be raised for each CPU that
does not expose the same features as the Boot Processor (BP).

- the blacklist of CPU features is now a macro defined in the
specialreg.h header, instead of hardcoding it inside MD initialization
code; fix comments.

- replace checks against CPUID_TSC with the cpu_hascounter() function.

- clean up the code in init_x86_64(), as cpu_feature variables are set
inside cpu_probe().

- use cpu_init_msrs() for i386. It will be eventually used later for NX
feature under i386 PAE kernels.

- remove code that checks for CPUID_NOX in amd64 mptramp.S, this is already
performed by cpu_hatch() through cpu_init_msrs().

- remove cpu_signature and feature_flags members from struct mpbios_proc
(they were never used).

This patch was tested with i386 MONOLITHIC, XEN3PAE_DOM0 and XEN3_DOM0 under
a native i386 host, and amd64 GENERIC, XEN3_DOM0 via QEMU virtual machines.

XXX Should kernel rev be bumped?

XXX A similar patch should be pulled-up for NetBSD-5, hopefully tomorrow.
 1.39  03-Apr-2010  jym Fix the comments about cpuid flags, according cpuid documentation by
Intel and AMD.
 1.38  13-Jan-2010  cegger branches: 1.38.2; 1.38.4;
recognize SVM PauseFilter
 1.37  13-Aug-2009  cegger recognize virtual cpu feature indicating guest state.
 1.36  26-May-2009  rmind Add CPU topology detection support for AMD processors.
Tested on the following AMD CPUs:
- Family 15, model 65
- Family 15, model 67
- Family 15, model 75
- Family 16, model 2
- Family 17, model 3

Reviewed (slightly older version of patch) by <yamt>.
 1.35  16-May-2009  pgoyette Correctly identify flag bit for SSSE3 (one of the 'S' was missing). Also
rename AMD bit from SCALL/RET to SYSCALL/SYSRET to match Intel bit name.
 1.34  13-May-2009  pgoyette 1. Extend CPU probe of Intel processors to handle extended-models. This
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290
 1.33  12-Mar-2009  yamt add definitions for SVM features.
 1.32  12-Mar-2009  yamt comments
 1.31  14-Oct-2008  cegger branches: 1.31.2; 1.31.4; 1.31.8; 1.31.12;
do correct octal counting and use CPUID_APM_FLAGS in cpuctl
 1.30  14-Oct-2008  cegger add cpuid fn 80000007 %edx: AMD Power Management feature flags
 1.29  14-Oct-2008  cegger fix output of 3DNOWPREFETCH feature flag
 1.28  13-Oct-2008  cegger Add cpuid 0x80000001 %ecx features flags. Rename CPUID_MASK4 to CPUID_INTEL_MASK4 for consistency with new CPUID_AMD_MASK4
 1.27  26-Aug-2008  pgoyette Clean up previous: add bit definitions for some new fields, and use "old"
style bitmask_printf(9) format string for consistency with the rest of the
file. No functional change.

OK cegger@
 1.26  24-Aug-2008  pgoyette Shorten SYSCALL/SYSRET to SCALL/RET bit definition so it fits on one line.
 1.25  24-Aug-2008  pgoyette 1. For non-Intel vendors, don't overload cpuflags with the extended
flags from CPUID 80000001_EDX. Instead, keep the extended flags
separate, in ci_feature3_flags (Intel processors already kept a
separate ci_feature3_flag value).

2. Decode/display ci_feature3_flag in a vendor-specific manner, since
the definitions are vendor-specific.

OK cegger@
 1.24  25-May-2008  chris branches: 1.24.4;
Add detection of errata for AMD Family 10h steppings A and 2. Covering
errata:
254: Internal Resource Livelock Involving Cached TLB Reload
261: Processor May Stall Entering Stop-Grant Due to Pending Data
Cache Scrub
298: L2 Eviction May Occur During Processor Operation To Set
Accessed or Dirty Bit
309: Processor Core May Execute Incorrect Instructions on
Concurrent L2 and Northbridge Response
 1.23  03-Feb-2008  xtraeme branches: 1.23.6; 1.23.8; 1.23.10; 1.23.12;
Add DTES64 and SSE4 related bits to CPUID2_FLAGS, from FreeBSD.
 1.22  21-Dec-2007  drochner define the SSSE3 feature flag bit and print out all known bits
 1.21  29-Oct-2007  xtraeme branches: 1.21.2; 1.21.4; 1.21.8;
Add coretemp(4). A new driver for Intel Core's on-die thermal sensor,
available on Intel Core or newer CPUs.

Ported from FreeBSD. Tested by rmind on i386 and joerg on amd64.

Enabled with "options INTEL_CORETEMP".
 1.20  17-Oct-2007  garbled Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.19  26-Sep-2007  ad branches: 1.19.2;
x86 changes for pcc and LKMs.

- Replace most inline assembly with proper functions. As a side effect
this reduces the size of amd64 GENERIC by about 120kB, and i386 by a
smaller amount. Nearly all of the inlines did something slow, or something
that does not need to be fast.
- Make curcpu() and curlwp functions proper, unless __GNUC__ && _KERNEL.
In that case make them inlines. Makes curlwp LKM and preemption safe.
- Make bus_space and bus_dma more LKM friendly.
- Share a few more files between the ports.
- Other minor changes.
 1.18  11-Jul-2007  njoly branches: 1.18.8; 1.18.10; 1.18.12;
Display RDTSCP bit on AMD processors (Read Serialized TSC Pair).

ok by xtraeme
 1.17  03-Jul-2007  christos Support for VIA Esther (From FreeBSD)
 1.16  04-Jun-2007  xtraeme Add four missing bits for CPUID2_FLAGS, from FreeBSD.
 1.15  17-Feb-2007  daniel branches: 1.15.2; 1.15.6; 1.15.8; 1.15.14;
Add an opencrypto provider for the AES xcrypt instructions found on VIA
C5P and later cores (also known as 'ACE', which is part of the VIA PadLock
security engine). Ported from OpenBSD.

Reviewed on tech-crypto and port-i386, no objections to commiting this.
 1.14  16-Jan-2007  christos PR/35430: Izumi Tsutsui: Identify amd64 CPU on NetBSD/i386
 1.13  11-Jan-2007  ad x86_errata: correct the definition of MSR_HWCR and re-enable. Problem
noted and debugged by Murray Armfield (murray at river-styx.org).
 1.12  01-Jan-2007  ad Report on and where possible, try to work around some of the known errata
for Athlon 64 and Opteron processors. Tested briefly by cube@ and elad@.
 1.11  03-Sep-2006  xtraeme branches: 1.11.2; 1.11.6;
Update the enhanced speedstep driver and sync the code with OpenBSD:

est.c:

* Use a quintuplet (vendor, MHz_hi, mV_hi, MHz_lo, mV_lo } to match
CPUs more correctly than parsing the brand string.
* Add support for a bunch of models.
* Create a fake table on the fly if the CPU is unknown (there's no
table for it) with the current/highest/lowest frequency.

specialreg.h:

* Add some MSRs needed to get the bus clock value.

identcpu.c:

* Add functions specific to Pentium III, Pentium M and Pentium 4 to
get the bus clock value.

Note that the new fake table code from Simon Burge is not included on
this commit.

Ok'ed by simonb and dogcow.
 1.10  24-Aug-2006  cube Display XD for Intel processors (Execution Disable bit support).
 1.9  02-Dec-2005  christos branches: 1.9.4; 1.9.8; 1.9.18;
PR/32216: Nicolas Joly: Missing HTT feature display for Opterons dual-core CPUs
 1.8  21-Feb-2005  he branches: 1.8.4;
Probe and print the Intel Extended Feature Bits, as documented
in the CPUID instruction description in the "Intel Extended Memory 64
Technology Software Developer's Guide, Volume 1 of 2" available at
ftp://download.intel.com/technology/64bitextensions/30083402.pdf

This presently consists of the SYSCALL/SYSRET and the EM64T features.
CPUs with the EM64T feature available should be able to run amd64 code.

Reviewed by fvdl
 1.7  10-Feb-2005  drochner Recognize an obscure cpu feature flag bit "xTPR"
which indicates that Task Priority Messages might
be disabled. Not relevant for the kernel for now
(related to interrupt distribution on the APIC bus
afaict), but present on one of my boxes.
Being here, also recognise the future "Vanderpool"
extension.
 1.6  17-May-2004  joda branches: 1.6.4; 1.6.6;
the EST and TM2 flags in the second cpuid register were swapped
(according AP-485); while here add a few more flags
 1.5  19-Feb-2004  drochner define AMD64's CPUID_NOX bit (I'm curious where Intel puts this bit in the
ia32 extension just announced)
XXX there should be a better separation between generic and vendor
specific feature flags
 1.4  02-Feb-2004  soren Add Pentium M MSR definitions from Michael Eriksson.
 1.3  07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.2  25-Apr-2003  fvdl branches: 1.2.2;
Share some common cache info cpuid code between i386 and x86_64.
 1.1  26-Feb-2003  fvdl Move some files out of i386 into x86, so that they can be shared with
other ports.
 1.2.2.6  11-Dec-2005  christos Sync with head.
 1.2.2.5  04-Mar-2005  skrll Sync with HEAD.

Hi Perry!
 1.2.2.4  15-Feb-2005  skrll Sync with HEAD.
 1.2.2.3  21-Sep-2004  skrll Fix the sync with head I botched.
 1.2.2.2  18-Sep-2004  skrll Sync with HEAD.
 1.2.2.1  03-Aug-2004  skrll Sync with HEAD
 1.6.6.2  19-Mar-2005  yamt sync with head. xen and whitespace. xen part is not finished.
 1.6.6.1  12-Feb-2005  yamt sync with head.
 1.6.4.1  29-Apr-2005  kent sync with -current
 1.8.4.8  04-Feb-2008  yamt sync with head.
 1.8.4.7  21-Jan-2008  yamt sync with head
 1.8.4.6  15-Nov-2007  yamt sync with head.
 1.8.4.5  27-Oct-2007  yamt sync with head.
 1.8.4.4  03-Sep-2007  yamt sync with head.
 1.8.4.3  26-Feb-2007  yamt sync with head.
 1.8.4.2  30-Dec-2006  yamt sync with head.
 1.8.4.1  21-Jun-2006  yamt sync with head.
 1.9.18.1  06-Sep-2006  riz Pull up following revision(s) (requested by xtraeme in ticket #111):
sys/arch/x86/include/specialreg.h: revision 1.11
sys/arch/i386/i386/identcpu.c: revision 1.39
sys/arch/i386/include/cpu.h: revision 1.128
sys/arch/i386/i386/est.c: revision 1.26
Update the enhanced speedstep driver and sync the code with OpenBSD:
est.c:
* Use a quintuplet (vendor, MHz_hi, mV_hi, MHz_lo, mV_lo } to match
CPUs more correctly than parsing the brand string.
* Add support for a bunch of models.
* Create a fake table on the fly if the CPU is unknown (there's no
table for it) with the current/highest/lowest frequency.
specialreg.h:
* Add some MSRs needed to get the bus clock value.
identcpu.c:
* Add functions specific to Pentium III, Pentium M and Pentium 4 to
get the bus clock value.
Note that the new fake table code from Simon Burge is not included on
this commit.
Ok'ed by simonb and dogcow.
 1.9.8.1  03-Sep-2006  yamt sync with head.
 1.9.4.1  09-Sep-2006  rpaulo sync with head
 1.11.6.1  10-Feb-2007  tron Pull up following revision(s) (requested by chs in ticket #411):
sys/arch/x86/include/specialreg.h: revision 1.14
sys/arch/i386/i386/identcpu.c: revision 1.53
PR/35430: Izumi Tsutsui: Identify amd64 CPU on NetBSD/i386
 1.11.2.2  01-Feb-2007  ad Sync with head.
 1.11.2.1  12-Jan-2007  ad Sync with head.
 1.15.14.2  03-Oct-2007  garbled Sync with HEAD
 1.15.14.1  26-Jun-2007  garbled Sync with HEAD.
 1.15.8.1  11-Jul-2007  mjf Sync with head.
 1.15.6.4  03-Dec-2007  ad Sync with HEAD.
 1.15.6.3  09-Oct-2007  ad Sync with head.
 1.15.6.2  15-Jul-2007  ad Sync with head.
 1.15.6.1  09-Jun-2007  ad Sync with head.
 1.15.2.2  17-Feb-2007  daniel Add an opencrypto provider for the AES xcrypt instructions found on VIA
C5P and later cores (also known as 'ACE', which is part of the VIA PadLock
security engine). Ported from OpenBSD.

Reviewed on tech-crypto and port-i386, no objections to commiting this.
 1.15.2.1  17-Feb-2007  daniel file specialreg.h was added on branch yamt-idlelwp on 2007-02-17 00:28:26 +0000
 1.18.12.1  06-Oct-2007  yamt sync with head.
 1.18.10.3  23-Mar-2008  matt sync with HEAD
 1.18.10.2  09-Jan-2008  matt sync with HEAD
 1.18.10.1  06-Nov-2007  matt sync with HEAD
 1.18.8.2  29-Oct-2007  joerg Sync with HEAD.
 1.18.8.1  02-Oct-2007  joerg Sync with HEAD.
 1.19.2.1  13-Nov-2007  bouyer Sync with HEAD
 1.21.8.1  02-Jan-2008  bouyer Sync with HEAD
 1.21.4.1  26-Dec-2007  ad Sync with head.
 1.21.2.1  18-Feb-2008  mjf Sync with HEAD.
 1.23.12.2  18-Sep-2008  wrstuden Sync with wrstuden-revivesa-base-2.
 1.23.12.1  23-Jun-2008  wrstuden Sync w/ -current. 34 merge conflicts to follow.
 1.23.10.7  09-Oct-2010  yamt sync with head
 1.23.10.6  11-Aug-2010  yamt sync with head.
 1.23.10.5  11-Mar-2010  yamt sync with head
 1.23.10.4  19-Aug-2009  yamt sync with head.
 1.23.10.3  20-Jun-2009  yamt sync with head
 1.23.10.2  16-May-2009  yamt sync with head
 1.23.10.1  04-May-2009  yamt sync with head.
 1.23.8.1  04-Jun-2008  yamt sync with head
 1.23.6.3  17-Jan-2009  mjf Sync with HEAD.
 1.23.6.2  28-Sep-2008  mjf Sync with HEAD.
 1.23.6.1  02-Jun-2008  mjf Sync with HEAD.
 1.24.4.1  19-Oct-2008  haad Sync with HEAD.
 1.31.12.1  21-Apr-2010  matt sync to netbsd-5
 1.31.8.6  27-Aug-2011  jym Sync with HEAD. Most notably: uvm/pmap work done by rmind@, and MP Xen
work of cherry@.

No regression observed on suspend/restore.
 1.31.8.5  28-Mar-2011  jym Sync with HEAD. TODO before merge:
- shortcut for suspend code in sysmon, when powerd(8) is not running.
Borrow ``xs_watch'' thread context?
- bug hunting in xbd + xennet resume. Rings are currently thrashed upon
resume, so current implementation force flush them on suspend. It's not
really needed.
 1.31.8.4  24-Oct-2010  jym Sync with HEAD
 1.31.8.3  01-Nov-2009  jym Sync with HEAD.
 1.31.8.2  31-May-2009  jym Sync with HEAD.
 1.31.8.1  13-May-2009  jym Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.
 1.31.4.4  01-Jun-2015  sborrill Pull up the following revisions(s) (requested by msaitoh in ticket #1968):
sys/arch/x86/include/specialreg.h: revision 1.72 via patch

Backport CPUID_TO_*() macros. Old macros are kept for compatibility.
 1.31.4.3  19-Jun-2013  bouyer Pull up following revision(s) (requested by msaitoh in ticket #1847):
sys/arch/x86/include/mtrr.h: revision 1.5
sys/arch/x86/x86/mtrr_i686.c: revision 1.25
sys/arch/x86/include/specialreg.h: revision 1.55
Increase MTRR_I686_NVAR_MAX from 8 to 16. Avoids
"FIXME: more than 8 MTRRs (10)" message on booting Thinkpad W520 and
similar. While here replace a magic number with MTRR_I686_NVAR_MAX * 2
 1.31.4.2  28-Nov-2012  riz branches: 1.31.4.2.2;
Pull up following revision(s) (requested by christos in ticket #1819):
sys/arch/x86/include/specialreg.h: revision 1.58
Add VIA Eden FCR MSR.
 1.31.4.1  16-Jun-2009  snj branches: 1.31.4.1.2;
Pull up following revision(s) (requested by rmind in ticket #789):
sys/arch/x86/include/specialreg.h: revision 1.36
sys/arch/x86/x86/cpu_topology.c: revision 1.2
Add CPU topology detection support for AMD processors.
Tested on the following AMD CPUs:
- Family 15, model 65
- Family 15, model 67
- Family 15, model 75
- Family 16, model 2
- Family 17, model 3
Reviewed (slightly older version of patch) by <yamt>.
 1.31.4.2.2.1  01-Jun-2015  sborrill Pull up the following revisions(s) (requested by msaitoh in ticket #1968):
sys/arch/x86/include/specialreg.h: revision 1.72 via patch

Backup CPUID_TO_*() macros. Old macros are kept for compatibility.
 1.31.4.1.2.1  01-Jun-2015  sborrill Pull up the following revisions(s) (requested by msaitoh in ticket #1968):
sys/arch/x86/include/specialreg.h: revision 1.72 via patch

Backup CPUID_TO_*() macros. Old macros are kept for compatibility.
 1.31.2.1  28-Apr-2009  skrll Sync with HEAD.
 1.38.4.2  05-Mar-2011  rmind sync with head
 1.38.4.1  30-May-2010  rmind sync with head
 1.38.2.3  22-Oct-2010  uebayasi Sync with HEAD (-D20101022).
 1.38.2.2  17-Aug-2010  uebayasi Sync with HEAD.
 1.38.2.1  30-Apr-2010  uebayasi Sync with HEAD.
 1.49.4.2  05-Mar-2011  bouyer Sync with HEAD
 1.49.4.1  17-Feb-2011  bouyer Sync with HEAD
 1.49.2.1  06-Jun-2011  jruoho Sync with HEAD.
 1.53.6.6  02-Jun-2012  mrg sync to latest -current.
 1.53.6.5  29-Apr-2012  mrg sync to latest -current.
 1.53.6.4  06-Mar-2012  mrg sync to -current
 1.53.6.3  06-Mar-2012  mrg sync to -current
 1.53.6.2  04-Mar-2012  mrg sync to latest -current.
 1.53.6.1  18-Feb-2012  mrg merge to -current.
 1.53.2.5  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.53.2.4  23-Jan-2013  yamt sync with head
 1.53.2.3  30-Oct-2012  yamt sync with head
 1.53.2.2  23-May-2012  yamt sync with head.
 1.53.2.1  17-Apr-2012  yamt sync with head
 1.55.2.5  26-Jan-2015  martin Pull up the following, requested by msaitoh in ticket #1240:

sys/arch/x86/include/specialreg.h 1.72 via patch

Add CPUID_TO_*() macros to avoid bug. Old macros are kept for compatibility.
See http://mail-index.netbsd.org/port-amd64/2013/11/12/msg001978.html
 1.55.2.4  29-Dec-2014  martin Pull up the following revisisions, requested by msaitoh in #1220:

sys/arch/x86/include/specialreg.h 1.59-1.71, 1.73-1.81 (patch)

Update x86 special register definitions:
- Add latest CR4 bits.
- Recognize the P1GB and RDTSCP which were AMD-only on Intel HW too.
- Add some missing bit definitions for CPUID2 and those for XCR0.
- Fix CPUID_AMD_FLAGS4 to not try to print bits \41 and \42.
- Correct the comment about the extended family and model bits.
- Add some definitions related to the process extended state
enumeration.
- Add Intel Structured Extended Feature leaf (Fn0000_0007).
- Sort CPUID definitions in initial EAX value.
- Add Intel Deterministic Cache Parameter Leaf (CPUID leaf 4).
- Add some AMD Fn80000001 extended features %ecx bits definitions.
- "s/MXX/MMXX/" because this bit is "MMX eXtention".
- Add some definitions for cpu 'extended state' enumeration
(Fn0000000d).
- Add Energy Performance Bias bit of Fn0000_0006 %ecx.
- Add MSR_IA32_PLATFORM_ID (0x017)
- Modify comment.
- Style fix.
 1.55.2.3  07-May-2012  riz Pull up following revision(s) (requested by christos in ticket #220):
sys/arch/x86/x86/identcpu.c: revision 1.31
sys/arch/x86/include/specialreg.h: revision 1.58
PR/41267: Andrius V: 5.0 RC4 does not detect second CPU in VIA. VIA Eden cpuid
lies about it's ability to do cmpxchg8b. Turn the feature on using the FCR MSR.
Needs pullup to both 5 and 6.
Add VIA Eden FCR MSR.
 1.55.2.2  09-Apr-2012  riz Pull up following revision(s) (requested by chs in ticket #168):
sys/arch/x86/include/specialreg.h: revision 1.57
sys/arch/x86/x86/errata.c: revision 1.20
bring in this change from openbsd:
Implement the AMD suggested workaround for family 10h & 12h errata 721
"Processor May Incorrectly Update Stack Pointer" by setting a bit
marked 'reserved' in an MSR that is only "documented" to exist on 12h.
 1.55.2.1  05-Mar-2012  sborrill Pull up the following revisions(s) (requested by bouyer in ticket #80):
sys/arch/xen/x86/x86_xpmap.c: revision 1.42
sys/arch/x86/include/specialreg.h: revision 1.56
sys/arch/amd64/amd64/machdep.c: revision 1.179
sys/arch/i386/i386/locore.S: revision 1.97
sys/arch/i386/i386/machdep.c: revision 1.723 via patch
sys/arch/x86/include/cpu.h: revision 1.49

Fix possible FPU registers corruption on context switches.
Fix type of pointers passed to some hypercalls.
 1.59.2.5  03-Dec-2017  jdolecek update from HEAD
 1.59.2.4  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.59.2.3  23-Jun-2013  tls resync from head
 1.59.2.2  25-Feb-2013  tls resync with head
 1.59.2.1  20-Nov-2012  tls Resync to 2012-11-19 00:00:00 UTC
 1.63.6.2  18-May-2014  rmind sync with head
 1.63.6.1  28-Aug-2013  rmind sync with head
 1.78.4.6  09-Oct-2018  snj Pull up following revision(s) (requested by msaitoh in ticket #1636):
sys/arch/x86/include/cacheinfo.h: 1.23-1.26
sys/arch/x86/include/cpu.h: 1.70
sys/arch/x86/include/specialreg.h: 1.91-1.93,1.98,1.100,1.102-1.124,1.126,1.130 via patch
sys/arch/x86/x86/cpu_topology.c: 1.10
sys/arch/x86/x86/identcpu.c: 1.56-1.57,1.70 via patch
usr.sbin/cpuctl/arch/i386.c: 1.71,1.75-1.79,1.81-1.85 via patch
Add some register definitions for x86:
- Add CLWB bit.
- Fix a few (unused) MSR values, and add some bit definitions of
MSR_EFER from Murray Armfield in PR#42861.
- CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify
comments and snprintb() string.
- Define CPUID Fn00000001 %ebx bits and use them.
No functional change.
- Add Structured Extended Flags Enumeration Leaf's bit definitions:
AVX512_{IFMA,VBMI2,VNNI,BITALG,VPOPCNTDQ,4VNNIW,4FMAPS},GFNI&VAES.
- Add Turbo Boost Max Technology 3.0 bit.
- Add AMD SVM features definitions.
- Add Intel cpuid 7 %edx IBRS and STIBP bit definitions.
- Fix swapped comments for EFER LME and LMA
- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add MSR_IA32_ARCH_CAPABILITIES definition.
- Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.
- Add Intel Deterministic Address Translation Parameter Leaf(0x18)
definitions.
- s/CLFUSH/CLFLUSH/
- Add AMD's Disable Indirect Branch Predictor bit definition.
- Add the MSR bits definitions for IBRS, STIBP and IBPB.
- Add Intel Fn0000_0006 %eax new bit 14-20 (HWP stuff).
- Intel Fn0000_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.
- Add AMD's CPUID Fn80000001 %edx MMX and FXSR bit definitions.
- Add RDCL_NO and IBRS_ALL.
- Add SSBD and RSBA bit definitions.
- Add AMD's SSB bit definitions for F15H, F16H and F17H.
- Add cpuid 7 edx L1D_FLUSH bit.
- Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
- Add IA32_FLUSH_CMD MSR.
- Add yet another Shared L2 TLB (2M/4M pages).
- Add 3way and 6way of L2 cache or TLB on AMD CPU.
- AMD L3 cache association bitfield is not 8bit but 4bit like others
association bitfields.
- Sort entries. No functional change.
- Modify comment, fix typo in comment and add comment.
cpuctl(8):
- Add detection for Quark X1000, Xeon E5 v4, E7 v4,
Core i7-69xx Extreme Edition, Xeon Scalable (Skylake),
Xeon Phi [357]200 (Knights Landing), Atom (Goldmont),
Atom (Denverton), Future Core (Cannon Lake), Atom (Goldmont Plus),
Xeon Phi 7215, 7285 and 7295 (Knights Mill) and
7th or 8th gen Core (Kaby Lake, Coffee Lake).
- Print Structured Extended Feature leaf Fn0000_0007 %ebx on AMD,too.
- Print Fn0000_0007 %ecx on Intel.
- Print Intel cpuid 7 %edx.
- Parse the TLB info from `cpuid leaf 18H' on Intel processor.
- Use aprint_error_dev() for error output.
 1.78.4.5  08-Dec-2016  snj Pull up following revision(s) (requested by msaitoh in ticket #1285):
sys/arch/x86/include/cacheinfo.h: revision 1.22
sys/arch/x86/include/specialreg.h: revisions 1.87 and 1.90
usr.sbin/cpuctl/arch/i386.c: revisions 1.72-1.74
Changes for x86's cpuctl(8):
- Add Quark X1000, Xeon E[57] v4, Core i7-69xx Extreme, 7th gen Core,
Denverton, Xeon Phi [357]200, Future Xeon and Future Xeon Phi.
- Add SGX, UMIP, RDPID, SGXLC, AVX512DQ, AVX512BW and AVX512VL bit.
- Fix the bit location of CLFLUSHOPT.
- Add new TLB descriptor 0x64 and 0xc4.
 1.78.4.4  06-Mar-2016  martin branches: 1.78.4.4.2;
Pull up the following changes, requested by msaitoh in #1117:

sys/arch/x86/include/cacheinfo.h 1.20-1.21
sys/arch/x86/include/specialreg.h 1.83-1.86
usr.sbin/cpuctl/arch/i386.c 1.67-1.70

Changes for x86's cpuctl(8):
- Add some TLB information (index 0x6a-0x6d).
- Add Hardware-Controlled Performance States (HWP) bits, FPU Data
Pointer Updated Only bit and CLFLUSHOPT bit.
- Add some AMD's bit definitions from "BIOS and Kernel Developer(BKDG)
for AMD Family 15h Models 60h-6Fh Processors".
- Add Xeon E5-4600 v3,
- Add Xeon E3-1200 v4 and v5.
- Add 6th gen Core, Xeon E3-1500 v5 and Xeon D-1500.
- Change CPU family 0x1c from "Atom Family" to "45nm Atom Family"
 1.78.4.3  09-May-2015  snj Pull up following revision(s) (requested by msaitoh in ticket #739):
sys/arch/x86/include/specialreg.h: revision 1.82
usr.sbin/cpuctl/arch/i386.c: revision 1.66
From Intel SDM:
- Add the Silicon Debug bit in CPUID Fn00000001 %ecx
- Add CPUID Fn0000_0007 %ecx bits
- Add comments.
--
Update some Intel CPU models (Sky Lake, Broadwell and Atom X[357]).
 1.78.4.2  09-Jan-2015  martin Pull up following revision(s) (requested by msaitoh in ticket #396):
sys/arch/x86/x86/cpu_ucode_intel.c: revision 1.6
sys/arch/x86/include/specialreg.h: revision 1.81
Use specialreg.h's definitions.
 1.78.4.1  12-Dec-2014  martin Pull up following revision(s) (requested by msaitoh in ticket #310):
sys/arch/x86/include/specialreg.h: revision 1.79-1.80
usr.sbin/cpuctl/arch/i386.c: revision 1.59
sys/arch/x86/include/cacheinfo.h: revision 1.19

Update some cpuid related values:
- Add XSAVECC, XGETBV, XSAVES, SMAP and PQE
- Change XINUSE to XGETBV
- Add new cache descripter value (0xc3)
- Update signatures for the follwing CPUs:
- Core M-5xxx
- Core i7 Extreme
- Future Core (0x4e)
- Future Xeon (0x56)
 1.78.4.4.2.1  18-Jan-2017  skrll Sync with netbsd-5
 1.80.2.8  28-Aug-2017  skrll Sync with HEAD
 1.80.2.7  05-Feb-2017  skrll Sync with HEAD
 1.80.2.6  05-Oct-2016  skrll Sync with HEAD
 1.80.2.5  29-May-2016  skrll Sync with HEAD
 1.80.2.4  19-Mar-2016  skrll Sync with HEAD
 1.80.2.3  22-Sep-2015  skrll Sync with HEAD
 1.80.2.2  06-Jun-2015  skrll Sync with HEAD
 1.80.2.1  06-Apr-2015  skrll Sync with HEAD
 1.87.2.4  26-Apr-2017  pgoyette Sync with HEAD
 1.87.2.3  20-Mar-2017  pgoyette Sync with HEAD
 1.87.2.2  07-Jan-2017  pgoyette Sync with HEAD. (Note that most of these changes are simply $NetBSD$
tag issues.)
 1.87.2.1  26-Jul-2016  pgoyette Sync with HEAD
 1.91.2.1  21-Apr-2017  bouyer Sync with HEAD
 1.97.2.1  19-May-2017  pgoyette Resolve conflicts from previous merge (all resulting from $NetBSD
keywork expansion)
 1.98.2.28  29-Jul-2023  martin Pull up the following revisions, all via patch, requested by msaitoh
in ticket #1853:

sys/arch/x86/include/specialreg.h 1.204-1.206, 1.208

- Add Intel CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT.
- Add AMD CPUID 0x80000008 %ebx bit 30 IBPB_RET and CPUID 0x8000000a
%edx bit 29 BusLockThreshold.
- Fix typo in comment.
 1.98.2.27  25-Jul-2023  martin Pull up following revision(s) (requested by mrg in ticket #1851):

sys/arch/x86/include/specialreg.h: revision 1.207
sys/arch/x86/x86/errata.c: revision 1.31

x86: turn off zenbleed chicken bit on Zen2 cpus.

this is based upon Taylor's original work. i just made the list
of CPUs to run on correct as i could determine. (also, add some
Zen3 and Zen4 cpuids not yet used by any errata.)

(might be nice to have a better way to expression revision ranges
rather than specific cpuid matches, eg, 0x30-0x4f models in a cpu
family, etc.)

tested on ryzen 3600, and a ported zenbleed PoC that no longer
shows any obtained text. (a similar module-version of it stopped
the PoC on a ryzen 3950x without having to reboot.)

https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7008.html
https://lock.cmpxchg8b.com/zenbleed.html
 1.98.2.26  21-Jun-2023  martin Pull up following revision(s) (requested by msaitoh in ticket #1827):

sys/arch/x86/include/specialreg.h: revision 1.202
sys/arch/x86/include/specialreg.h: revision 1.203
usr.sbin/cpuctl/arch/i386.c: revision 1.136

Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.

Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.
 1.98.2.25  23-Jan-2023  martin Pull up the following revisions, requested by msaitoh in ticket #1791:

sys/arch/x86/include/specialreg.h 1.193-1.198

- Add CPUID Fn0000_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25
Hardware Feedback Notification support.
- Add CPUID Fn0000_0007 %ecx bit 29 ENQCMD.
- Add CPUID Fn0000_0007 %edx bit 1 SGX-KEYS.
- Add CPUID Fn0000_0007 %edx bit 5 UINTR(User INTeRrupts).
- Add CPUID Fn0000_0007 %edx bit 11 RTM_ALWAYS_ABORT.
- Add CPUID Fn0000_0007 %edx bit 22 AMX_BF16.
- Add CPUID Fn0000_0007 %edx bit 23 AVX512_FP16.
- Add CPUID Fn0000_0007 %edx bit 24 AMX_TILE.
- Add CPUID Fn0000_0007 %edx bit 25 AMX_INT8.
- Add CPUID Fn0000_0007 sub-leaf 1 %edx bit 18 CET_SSS.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx definitions.
- Add CPUID Fn0000_000d sub-leaf 1 %eax bit 4 XFD.
- Add CPUID Fn0000_001d Tile Information.
- Add CPUID Fn0000_001e TMUL Information.
- Add CPUID Fn8000_0007 %eax RAS capabilities.
- Add CPUID Fn8000_0008 %ebx BTC_NO,
- Add cpuid Fn8000_000a x2AVIC, VNMI, IBSVIRT and ROGPT.
- Add CPUID Fn8000_001b Instruction-Based Sampling.
- Add CPUID Fn8000_001e Processor Topology Information.
- Add CPUID Fn8000_001f %eax RPMQUERY, VmplSSS, TscAuxVirt,
VmgexitParam, VirtualTomMsr, IbsVirtGuest, SmtProtection,
vsmCommPageMSR and NestedVirtSnpMsr.
- Add CPUID Fn8000_0021 AMD Extended Features Identification 2.
- Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.
- Rename HW_FEEDBACK to HWI (Hardware Feedback Interface).
- Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT.
- Modify comment. Both Intel and AMD support CPUID Fn0000000b.
- Modify comment. Hybrid Information -> Native Model ID Information.
- Use __BIT(). Add comment. Whitespace fix.
 1.98.2.24  15-Oct-2022  martin Pull up following revision(s) (requested by msaitoh in ticket #1775):

sys/arch/x86/include/specialreg.h: revision 1.189
usr.sbin/cpuctl/arch/i386.c: revision 1.128
sys/arch/x86/include/specialreg.h: revision 1.190
sys/arch/x86/include/specialreg.h: revision 1.191
sys/arch/x86/include/specialreg.h: revision 1.192

s/shareing/sharing/. No functional change.

Add top-down slots event bit of architectural performance monitoring leaf.

Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.

Modify output of CPUID Fn0000000a.
old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>
new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>

Update some AMD CPUID bits:
- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().
 1.98.2.23  31-Jan-2022  martin Pull up the following revisions (all via patch), requested by
msaitoh in ticket #1731:

sys/arch/x86/include/specialreg.h 1.179-1.188

- Add CPUID definitions of Last Branch Record, Thread Director,
AVX version of VNNI, Fast short REP MOV, HRESET, PPIN, Architectural
LBR, Linear Address Masking and Hybrid Information from the latest
Intel SDM.
- Add CPUID definitions of AddrMaskExt, INT_WBINVD, IbrsSameMode,
EferLmsleUnsupported, PSFD and SecureTSC from AMD APM.
- Print CLFSH instead of CLFLUSH because both Intel and AMD documents
say so.
- Modify comment. Add comment. Fix typo. Use __BIT(). KNF. Sort lines.
No functional change.
 1.98.2.22  08-Dec-2021  martin Pull up the following, requested by msaitoh in ticket #1720:

sys/arch/x86/include/specialreg.h 1.146, 1.171,
1.173-1.178 via patch
sys/arch/x86/x86/identcpu.c 1.106, 1.117,
1.122 via patch
sys/arch/x86/x86/pmap.c patch
sys/external/bsd/drm2/drm/drm_cache.c 1.14
usr.sbin/cpuctl/arch/i386.c 1.114-1.117


- Add PT, PKRU, HDC, LA57, PKE, PKS, CET, CET_U, CET_S, HWP, KL,
AVX512_BF16, TME_EN and PCONFIG.
- Rename some macros to match the x86 specification and the other OSes.
- Print CPUID 0x8000008 %ebx on Intel, too.
- Print CPUID leaf 7 subleaf 1.
- Identify Tiger Lake, 3rd gen Xeon Scalable (Ice Lake), Elkhart Lake
and Jasper Lake.
- Remove a few unused MSRs.
- Add comment.
- KNF. Whitespace fix.
 1.98.2.21  05-Aug-2020  martin Accidently not commited for ticket #1595:

sys/arch/x86/include/specialreg.h 1.129 via patch

Add six errata for AMD Family 17h (Ryzen etc).
 1.98.2.20  05-Aug-2020  martin Pull up the following revisions, requested by msaitoh in ticket #1588:

sys/arch/x86/include/specialreg.h 1.162-1.168 via patch

- AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL".
- Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory
features.
- Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC
intercept bit.
- Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE.
- Add some definitions for Intel:
- Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and
IA32_PACKAGE_TERM* MSRs.
- Add CPUID leaf 7 %ecx bit 31 for Protection Keys.
- Add definition of Load only TLB and Store only TLB.
- Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES
- Fix HWP_IGNIDL.
- Add CPUID 7 %edx bit 9 "SRBDS_CTRL"
- Modify comment. Style and fix typo.
 1.98.2.19  15-Apr-2020  martin Pull up the following, requested by msaitoh in ticket #1530:

sys/arch/x86/x86/procfs_machdep.c 1.33-1.36
sys/arch/x86/x86/tsc.c 1.40
sys/arch/x86/x86/specialreg.h 1.159-1.161
usr.sbin/cpuctl/arch/i386.c 1.109-1.110 via patch

- Print avx512ifma, cqm_mbm_total, cqm_mbm_local, waitpkg, rdpru,
Fast Short Rep Mov(fsrm), AVX512_VP2INTERSECT, SERIALIZE and
TSXLDTRK.
- Rename CPUID Fn8000_0007 %edx bit 8 from "TSC" to "ITSC"
(Invariant TSC) to avoid confusion.
- Print CPUID 0x80000007 %edx on both Intel and AMD.
- Remove ci_max_ext_cpuid from usr.sbin/cpuctl/arch/i386.c because it's
the same as ci_cpuid_extlevel.
- Use unsigned to avoid undefined behavior in procfs_getonefeatreg().
 1.98.2.18  31-Jan-2020  martin Pull up the following, requested by msaitoh in ticket #1494:

sys/arch/x86/include/specialreg.h 1.146, 1.151-1.154, 1.156 via patch
usr.sbin/cpuctl/arch/i386.c 1.105-1.107 via patch

- Add definitions of AMD's CPUID Fn8000_0008 %ebx.
- Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.
- Call cpu_dcp_cacheinfo() only when the cpuid Topology Extension flag
is set on AMD processor.
- Fix typos.
 1.98.2.17  19-Nov-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #1450):

usr.sbin/cpuctl/arch/i386.c: revision 1.108
sys/arch/x86/include/specialreg.h: revision 1.158

Add the following bit definitions from the latest Intel SDM:
- CET shadow stack
- Fast Short REP MOV
- Hybrid part
- CET Indirect Branch Tracking

0x7d and 0x7e are for 10th generation Core (Ice Lake).
 1.98.2.16  12-Nov-2019  martin Pull up following revision(s) (requested by maxv in ticket #1433):

sys/arch/x86/include/specialreg.h: revision 1.157
sys/arch/x86/x86/spectre.c: revision 1.31

Mitigation for CVE-2019-11135: TSX Asynchronous Abort (TAA).

Two sysctls are added:
machdep.taa.mitigated = {0/1} user-settable
machdep.taa.method = {string} constructed by the kernel

There are two cases:

(1) If the CPU is affected by MDS, then the MDS mitigation will also
mitigate TAA, and we have nothing else to do. We make the 'mitigated' leaf
read-only, and force:

machdep.taa.mitigated = machdep.mds.mitigated
machdep.taa.method = [MDS]

The kernel already enables the MDS mitigation by default.

(2) If the CPU is not affected by MDS but is affected by TAA, then we use
the new TSX_CTRL MSR to disable RTM. This MSR is provided via a microcode
update, now available on the Intel website. The kernel will automatically
enable the TAA mitigation if the updated microcode is present. If the new
microcode is not present, the user can load it via cpuctl, and set
machdep.taa.mitigated=1.
 1.98.2.15  16-Aug-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #1338):

usr.sbin/cpuctl/arch/i386.c: revision 1.104
sys/arch/x86/x86/identcpu.c: revision 1.93
sys/arch/x86/include/cacheinfo.h: revision 1.28
sys/arch/x86/include/specialreg.h: revision 1.150

- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
Intel Deterministic Cache Parameter Leaf(0x04), so make new
cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?
 1.98.2.14  17-Jul-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #1293):

sys/arch/x86/include/specialreg.h: revision 1.149

Define some new bits of CPUID Fn8000_0007 %edx AMD Advanced Power Management
leaf.
 1.98.2.13  29-May-2019  martin Pullup the following, requested by msaitoh in ticket #1270:

sys/arch/x86/include/specialreg.h 1.143, 1.145 via patch
sys/arch/x86/x86/procfs_machdep.c 1.30

Add TSX_FORCE_ABORT related definitions.
Add cpuid7 edx bit 10 "MD_CLEAR".
 1.98.2.12  14-May-2019  martin Pull up following revision(s) (requested by maxv in ticket #1269):

sys/arch/amd64/amd64/locore.S: revision 1.181 (adapted)
sys/arch/amd64/amd64/amd64_trap.S: revision 1.47 (adapted)
sys/arch/x86/include/specialreg.h: revision 1.144 (adapted)
sys/arch/amd64/include/frameasm.h: revision 1.43 (adapted)
sys/arch/x86/x86/spectre.c: revision 1.27 (adapted)

Mitigation for INTEL-SA-00233: Microarchitectural Data Sampling (MDS).
It requires a microcode update, now available on the Intel website. The
microcode modifies the behavior of the VERW instruction, and makes it flush
internal CPU buffers. We hotpatch the return-to-userland path to add VERW.

Two sysctls are added:

machdep.mds.mitigated = {0/1} user-settable
machdep.mds.method = {string} constructed by the kernel

The kernel will automatically enable the mitigation if the updated
microcode is present. If the new microcode is not present, the user can
load it via cpuctl, and set machdep.mds.mitigated=1.
 1.98.2.11  12-Feb-2019  martin Actually pull up rev 1.139 (as claimed, but not done in previous),
requested by msaitoh in ticket #1187:

Fix bitstring format of Intel CPUID Architectural Performance Monitoring
Fn0000000a %ebx.
 1.98.2.10  11-Feb-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #1187):

usr.sbin/cpuctl/arch/i386.c: revision 1.92
sys/arch/x86/include/specialreg.h: revision 1.138

Add new CPUID flags WAITPKG, CLDEMOTE, MOVDIRI, MOVDIR64B and
IA32_CORE_CAPABILITIES from the latest Intel SDM.

Add Ice Lake and Tremont from the latest Intel SDM.

Fix bitstring format of Intel CPUID Architectural Performance Monitoring
Fn0000000a %ebx.
 1.98.2.9  27-Dec-2018  martin Pull up following revision(s) (requested by maxv in ticket #1148):

sys/arch/x86/x86/identcpu.c: revision 1.81
sys/arch/x86/x86/identcpu.c: revision 1.82
sys/arch/x86/x86/identcpu.c: revision 1.84
sys/arch/x86/include/specialreg.h: revision 1.131

Declare the MSR_VIA_ACE values as macros, and use a consistent naming,
similar to the rest of the file.

I'm wondering if I'm not fixing a huge bug here. The ECX8 value we were
using was wrong: ECX8 is bit 1, not bit 0. Bit 0 is ALTINST, an alternate
ISA, which is now known to be backdoored.

So it looks like we were explicitly enabling the backdoor.

Not tested, because I don't have a VIA cpu.

-

Merge the VIA detection code into cpu_probe_c3.

-

Explicitly disable ALTINST on VIA, in case it isn't disabled by default
already (the 'VIA cpu backdoor').
 1.98.2.8  04-Dec-2018  martin Pull up following revision(s) (requested by msaitoh in ticket #1120):

usr.sbin/cpuctl/arch/i386.c: revision 1.85
usr.sbin/cpuctl/arch/i386.c: revision 1.86
usr.sbin/cpuctl/arch/i386.c: revision 1.87
usr.sbin/cpuctl/arch/i386.c: revision 1.88
usr.sbin/cpuctl/arch/i386.c: revision 1.89
usr.sbin/cpuctl/arch/i386.c: revision 1.90
sys/arch/x86/include/specialreg.h: revision 1.132
sys/arch/x86/include/specialreg.h: revision 1.133
sys/arch/x86/include/specialreg.h: revision 1.134
sys/arch/x86/include/specialreg.h: revision 1.135
sys/arch/x86/include/specialreg.h: revision 1.136
sys/arch/x86/x86/cpu_topology.c: revision 1.14

Add MAWAU (for BND{LD,ST}X instruction) from the latest Intel SDM.

Whitespace fix. No functional change.

Modify comment. No functional change:
- AMD also has CPUID 0x06 and 0x0d.
- PCOMMIT was obsoleted.
- Use ci_feat_val[7] as CPUID 7 %edx to match x86/cpu.h
- AMD also has CPUID 6.
- Remove unused code for coretemp.
- Consistently use descs[] instead of data[].
- AMD also reports CPUID 7's highest subleaf. Print it.
- Use macro.
Add Intel CPUID Extended Topology Enumeration Fn0000000b definitions.
Decode package, core and SMT id if CPUID 0x0b is available on Intel processor.

If the value is different from the kernel value, we should fix the kernel code.

TODO: Use 0x1f if it's available.

Add Intel/AMD MONITOR/MWAIT leaf.
Decode Intel/AMD MONITOR/MWAIT leaf.

Add Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.

Print Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.
 1.98.2.7  23-Sep-2018  martin Pull up following revision(s) (requested by msaitoh in ticket #1026):

sys/arch/x86/x86/procfs_machdep.c: revision 1.24
sys/arch/x86/include/specialreg.h: revision 1.130

OK'd by maxv:
- Add cpuid 7 edx L1D_FLUSH bit.
- Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
- Add IA32_FLUSH_CMD MSR.
 1.98.2.6  13-Jul-2018  martin Pull up following revision(s) (requested by maya in ticket #912):

sys/arch/x86/x86/identcpu.c: revision 1.79
sys/arch/x86/include/specialreg.h: revision 1.127

Disable MWAIT/MONITOR on Apollo Lake CPUs to workaround APL30 errata.

We use MWAIT/MONITOR to hatch secondary CPUs. The errata means that
the wakeup may not happen, so SMP boot fails.
Use wrmsr to disable it in hardware too, for extra paranoia.

PR port-amd64/53420,
also reported on netbsd-users by joern clausen and ssartor.
 1.98.2.5  09-Jun-2018  martin Pullup the following revisions, requested by maxv in ticket #865:

sys/arch/amd64/amd64/machdep.c 1.303 (patch)
sys/arch/amd64/conf/GENERIC 1.492 (patch)
sys/arch/amd64/conf/files.amd64 1.103 (patch)
sys/arch/i386/i386/machdep.c 1.806 (patch)
sys/arch/i386/conf/GENERIC 1.1179 (patch)
sys/arch/i386/conf/files.i386 1.393 (patch)
sys/arch/x86/include/cpu.h 1.91 (patch)
sys/arch/x86/include/specialreg.h upto 1.126 (patch)
sys/arch/x86/x86/x86_machdep.c upto 1.115 (patch, adapted)
sys/arch/x86/x86/spectre.c upto 1.19 (patch, adapted,
no IBRS,
SpectreV2 mitigations not
enabled by default)

Backport the hardware SpectreV2 and SpectreV4 mitigations.
 1.98.2.4  18-Apr-2018  martin Pull up following revision(s) (requested by msaitoh in ticket #778):

sys/arch/x86/include/specialreg.h: revision 1.118,1.119

From the latest Intel SDM:
- Add Intel Fn0000_0006 %eax new bit 14-20 (HWP stuff).
- Intel Fn0000_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.

Add Some bit definitions of AMD Fn80000001 %edx:
- MMX
- FXSR
 1.98.2.3  31-Mar-2018  martin Pull up following revision(s) (requested by maxv in ticket #678):

sys/arch/x86/include/specialreg.h: revision 1.115-1.117,1.120

Add IC_CFG.DIS_IND: "Disable Indirect Branch Predictor". Available (at
least) on AMD Families 10h, 12h and 16h.

Add the IBRS and STIBP MSRs.

... and also add IBPB ...

Add RDCL_NO and IBRS_ALL.
 1.98.2.2  16-Mar-2018  martin Pull up following revision(s) (requested by msaitoh in ticket #633):
sys/arch/x86/include/specialreg.h: revision 1.107
sys/arch/x86/include/specialreg.h: revision 1.108
sys/arch/x86/include/specialreg.h: revision 1.109
sys/arch/x86/include/cacheinfo.h: revision 1.23
sys/arch/x86/include/specialreg.h: revision 1.110
sys/arch/x86/include/specialreg.h: revision 1.111
sys/arch/x86/include/specialreg.h: revision 1.112
sys/arch/x86/include/specialreg.h: revision 1.113
sys/arch/x86/include/specialreg.h: revision 1.114
usr.sbin/cpuctl/arch/i386.c: revision 1.79
sys/arch/x86/x86/identcpu.c: revision 1.70
sys/arch/x86/include/specialreg.h: revision 1.106

Add comment.

Add Intel cpuid 7 %edx IBRS(IBPB Speculation Control) and
STIBP(STIBP Speculation Control) from OpenBSD.

Print Intel cpuid 7 %edx.

Example output of cpuctl -v identify 0:
+cpu0: 00000007: 00000000 000027ab 00000000 0c000000
(snip)
+cpu0: SEF edx 0xc000000<IBRS,STIBP>

fix swapped comments for EFER LME and LMA

- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add comment.
Add MSR_IA32_ARCH_CAPABILITIES definition.

Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.

Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

Sort entries. No functional change.

s/CLFUSH/CLFLUSH/
No functional change.
 1.98.2.1  21-Nov-2017  martin Pull up following revision(s) (requested by msaitoh in ticket #365):
sys/arch/x86/include/specialreg.h: revision 1.99
usr.sbin/cpuctl/arch/i386.c: revision 1.75
usr.sbin/cpuctl/arch/i386.c: revision 1.76
usr.sbin/cpuctl/arch/i386.c: revision 1.77
usr.sbin/cpuctl/arch/i386.c: revision 1.78
sys/arch/x86/x86/identcpu.c: revision 1.56
sys/arch/x86/x86/identcpu.c: revision 1.57
sys/arch/x86/x86/cpu_topology.c: revision 1.10
sys/arch/x86/include/specialreg.h: revision 1.100
sys/arch/x86/include/specialreg.h: revision 1.101
sys/arch/x86/include/specialreg.h: revision 1.102
sys/arch/x86/include/specialreg.h: revision 1.103
sys/arch/x86/include/specialreg.h: revision 1.104
sys/arch/x86/include/specialreg.h: revision 1.105
Add EFER_TCE. This would be an interesting feature to have, since it
reduces the indirect cost of invlpg; but I'm not convinced the way we
flush upper-levels is correct for this yet.
Fix typo in comment
Add a comment about APICBASE_PHYSADDR. Has to do with PR/42597.
Define CPUID Fn00000001 %ebx bits and use them. No functional change.
Set ci->ci_cflush_lsize correctly. This bug was added in the last commit(1.56).
Add the following instruction bits in Structured Extended Flags Enumeration
Leaf from "Intel Architecture Instruction Set Extensions and Future Features
Programming Reference" (319433-030):
AVX512_IFMA
AVX512_VBMI
AVX512_VBMI2
GFNI
VAES
VPCLMULQDQ
AVX512_VNNI
AVX512_BITALG
AVX512_VPOPCNTDQ
AVX512_4VNNIW
AVX512_4FMAPS
- Print ci_feat_val[5] (Structured Extended Feature leaf Fn0000_0007 %ebx) on
AMD, too.
- Print ci_feat_val[6] (Fn0000_0007 %ecx) on Intel.
Update from the latest Intel SDM:
0x5c: Atom (Goldmont)
0x5f: Atom (Goldmont, Denverton)
0x7a: Atom (Goldmont Plus)
Add Turbo Boost Max Technology 3.0 bit.
Update from Intel SDM:
0x55: Xeon Scalable (Skylake)
0x57: Xeon Phi [357]200 (Knights Landing)
0x66: Future Core (Cannon Lake)
0x85: Future Xeon Phi (Knights Mill)
Add the following bits in AMD Fn8000000a %edx features (SVM features):
PFThreshold (PAUSE filter threshold)
AVIC (AMD virtual interrupt controller)
V_VMSAVE_VMLOAD (virtualized VMSAVE and VMLOAD)
vGIF (virtualized GIF)
 1.112.2.8  18-Jan-2019  pgoyette Synch with HEAD
 1.112.2.7  26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.112.2.6  26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.112.2.5  06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.112.2.4  28-Jul-2018  pgoyette Sync with HEAD
 1.112.2.3  25-Jun-2018  pgoyette Sync with HEAD
 1.112.2.2  07-Apr-2018  pgoyette Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
 1.112.2.1  15-Mar-2018  pgoyette Synch with HEAD
 1.126.2.2  13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.126.2.1  10-Jun-2019  christos Sync with HEAD
 1.150.2.16  20-Jul-2024  martin Pull up following revision(s) (requested by andvar in ticket #1855):

sys/arch/x86/x86/identcpu.c: revision 1.129
sys/arch/x86/include/specialreg.h: revision 1.212
sys/arch/x86/x86/identcpu.c: revision 1.130

Disable the VIA Alternate Instructions according the VIA documentation:
* C7 and above do not support ALTINST, do not check or attempt to disable them.
* For VIA C3 Nehemiah check extended feature flags for support and status,
do no attempt to disable when AIS is not supported or enabled.
* For pre-Nehemiah models explicitly disable, if they are in the range
of documented models, flags aren't present to check the status on
these models.

Note: for pre-Nehemiah may be other functional side effects depdending
on the version and stepping.

Explicit disabling of ALTINST was introduced with rev. 1.84 following
the discovery of some VIA CPUs having these instructions enabled by default
leading to the potential backdoor (aka rosenbrindge).

Unfortunately, implementation used a wrong check (ACE supported flag),
which can be true for the later models, still supporting padlock features.

Setting ALTINST bit on those may have unexpected side effects like VIA C7 CPUID
instruction for temperature sensor not reporting correct value or
`cpuctl identify' not reporting certain CPU features. Similar side effects
can be observed even for Nehemiah models not supporting AIS instructions. This
change should limit possibility of such issues to only the pre-Nehemiah models,
not covered at all in the previous implementation.

Feature Control Register (FCR) macros were unified under one group and
consistent naming while implementing the change. Few comments updated as well.
patch reviewed by Riastradh@ (thank you)

PR kern/58370

Move determination of the largest VIA CPU extended function value
to the intended place where the checks are performed.
Currently the value can be overridden while checking for the padlock features,
and failing the check for max function value as a result.
 1.150.2.15  29-Jul-2023  martin Pull up the following revisions, all via patch, requested by msaitoh
in ticket #1669:

sys/arch/x86/include/specialreg.h 1.204-1.206, 1.208

- Add Intel CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT.
- Add AMD CPUID 0x80000008 %ebx bit 30 IBPB_RET and CPUID 0x8000000a
%edx bit 29 BusLockThreshold.
- Fix typo in comment.
 1.150.2.14  25-Jul-2023  martin Pull up following revision(s) (requested by mrg in ticket #1664):

sys/arch/x86/include/specialreg.h: revision 1.207
sys/arch/x86/x86/errata.c: revision 1.31

x86: turn off zenbleed chicken bit on Zen2 cpus.

this is based upon Taylor's original work. i just made the list
of CPUs to run on correct as i could determine. (also, add some
Zen3 and Zen4 cpuids not yet used by any errata.)

(might be nice to have a better way to expression revision ranges
rather than specific cpuid matches, eg, 0x30-0x4f models in a cpu
family, etc.)

tested on ryzen 3600, and a ported zenbleed PoC that no longer
shows any obtained text. (a similar module-version of it stopped
the PoC on a ryzen 3950x without having to reboot.)

https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7008.html
https://lock.cmpxchg8b.com/zenbleed.html
 1.150.2.13  21-Jun-2023  martin Pull up following revision(s) (requested by msaitoh in ticket #1646):

sys/arch/x86/include/specialreg.h: revision 1.202
sys/arch/x86/include/specialreg.h: revision 1.203
usr.sbin/cpuctl/arch/i386.c: revision 1.136

Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.

Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.
 1.150.2.12  23-Jan-2023  martin Pull up the following revisions, requested by msaitoh in ticket #1574:

sys/arch/x86/include/specialreg.h 1.193-1.198

- Add CPUID Fn0000_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25
Hardware Feedback Notification support.
- Add CPUID Fn0000_0007 %ecx bit 29 ENQCMD.
- Add CPUID Fn0000_0007 %edx bit 1 SGX-KEYS.
- Add CPUID Fn0000_0007 %edx bit 5 UINTR(User INTeRrupts).
- Add CPUID Fn0000_0007 %edx bit 11 RTM_ALWAYS_ABORT.
- Add CPUID Fn0000_0007 %edx bit 22 AMX_BF16.
- Add CPUID Fn0000_0007 %edx bit 23 AVX512_FP16.
- Add CPUID Fn0000_0007 %edx bit 24 AMX_TILE.
- Add CPUID Fn0000_0007 %edx bit 25 AMX_INT8.
- Add CPUID Fn0000_0007 sub-leaf 1 %edx bit 18 CET_SSS.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx definitions.
- Add CPUID Fn0000_000d sub-leaf 1 %eax bit 4 XFD.
- Add CPUID Fn0000_001d Tile Information.
- Add CPUID Fn0000_001e TMUL Information.
- Add CPUID Fn8000_0007 %eax RAS capabilities.
- Add CPUID Fn8000_0008 %ebx BTC_NO,
- Add cpuid Fn8000_000a x2AVIC, VNMI, IBSVIRT and ROGPT.
- Add CPUID Fn8000_001b Instruction-Based Sampling.
- Add CPUID Fn8000_001e Processor Topology Information.
- Add CPUID Fn8000_001f %eax RPMQUERY, VmplSSS, TscAuxVirt,
VmgexitParam, VirtualTomMsr, IbsVirtGuest, SmtProtection,
vsmCommPageMSR and NestedVirtSnpMsr.
- Add CPUID Fn8000_0021 AMD Extended Features Identification 2.
- Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.
- Rename HW_FEEDBACK to HWI (Hardware Feedback Interface).
- Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT.
- Modify comment. Both Intel and AMD support CPUID Fn0000000b.
- Modify comment. Hybrid Information -> Native Model ID Information.
- Use __BIT(). Add comment. Whitespace fix.
 1.150.2.11  15-Oct-2022  martin Pull up following revision(s) (requested by msaitoh in ticket #1542):

sys/arch/x86/include/specialreg.h: revision 1.189
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.23
usr.sbin/cpuctl/arch/i386.c: revision 1.128
sys/arch/x86/include/specialreg.h: revision 1.190
sys/arch/x86/include/specialreg.h: revision 1.191
sys/arch/x86/include/specialreg.h: revision 1.192

s/shareing/sharing/. No functional change.

Add top-down slots event bit of architectural performance monitoring leaf.

Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.

Modify output of CPUID Fn0000000a.
old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>
new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>

Update some AMD CPUID bits:
- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().
 1.150.2.10  31-Jan-2022  martin Pull up the following revisions (all via patch), requested by msaitoh
in ticket #1417:

sys/arch/x86/include/specialreg.h 1.179-1.188

- Add CPUID definitions of Last Branch Record, Thread Director,
AVX version of VNNI, Fast short REP MOV, HRESET, PPIN, Architectural
LBR, Linear Address Masking and Hybrid Information from the latest
Intel SDM.
- Add CPUID definitions of AddrMaskExt, INT_WBINVD, IbrsSameMode,
EferLmsleUnsupported, PSFD and SecureTSC from AMD APM.
- Print CLFSH instead of CLFLUSH because both Intel and AMD documents
say so.
- Modify comment. Add comment. Fix typo. Use __BIT(). KNF. Sort lines.
No functional change.
 1.150.2.9  08-Dec-2021  martin Pull up the following revisions, requested by msaitoh in ticket #1391:

sys/arch/x86/include/specialreg.h 1.171, 1.173-1.178
sys/arch/x86/x86/identcpu.c 1.106, 1.117,
1.122 via patch
sys/dev/nvmm/x86/nvmm_x86.c 1.18
sys/external/bsd/drm2/drm/drm_cache.c 1.14
sys/external/bsd/drm2/include/asm/cpufeature.h 1.5
usr.sbin/cpuctl/arch/i386.c 1.114-1.117


- Add LA57, PKE, PKS, CET, CET_U, CET_S, HWP, KL, AVX512_BF16, TME_EN
and PCONFIG.
- Rename some macros to match the x86 specification and the other OSes.
- Print CPUID 0x8000008 %ebx on Intel, too.
- Print CPUID leaf 7 subleaf 1.
- Identify Tiger Lake, 3rd gen Xeon Scalable (Ice Lake), Elkhart Lake
and Jasper Lake.
- Add comment.
- KNF. Whitespace fix.
 1.150.2.8  04-Sep-2020  martin Pull up following revision(s) (requested by maxv in ticket #1076):

sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.75
sys/arch/x86/include/specialreg.h: revision 1.172
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.72

nvmm-x86-vmx: fix detection of the BIOS lock

If it's locked, ensure it's locked with VMX enabled. If it's not locked,
then lock it ourselves with VMX enabled.

Should fix NetBSD PR/55596.

-

Add a few more CPUID flags.

-

nvmm-x86-svm: check the SVM revision
Only revision 1 exists, but check it, for future-proofness.
 1.150.2.7  13-Jul-2020  martin Pull up following revision(s) (requested by msaitoh in ticket #998):

sys/arch/x86/include/specialreg.h: revision 1.162
sys/arch/x86/include/specialreg.h: revision 1.164
sys/arch/x86/include/specialreg.h: revision 1.165
sys/arch/x86/include/specialreg.h: revision 1.166
sys/arch/x86/include/specialreg.h: revision 1.167
sys/arch/x86/include/specialreg.h: revision 1.168

- AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL".
- Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory
features.
- Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit.
- Modify comment.
Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE.
This bit makes lfence instruction serializing.
Add some definitions from the latest Intel SDM plus small fix:
- Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and IA32_PACKAGE_TERM* MSRs.
- Add CPUID leaf 7 %ecx bit 31 for Protection Keys.
- Add definition of Load only TLB and Store only TLB.
- Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES
- Fix HWP_IGNIDL.
Add SRBDS_CTRL bit.
style and fix typo
 1.150.2.6  14-Apr-2020  martin Pull up following revision(s) (requested by msaitoh in ticket #833):

usr.sbin/cpuctl/arch/i386.c: revision 1.109
sys/arch/x86/include/specialreg.h: revision 1.159
usr.sbin/cpuctl/arch/i386.c: revision 1.110
sys/arch/x86/include/specialreg.h: revision 1.160
sys/arch/x86/include/specialreg.h: revision 1.161
sys/arch/x86/x86/tsc.c: revision 1.40
sys/arch/x86/x86/procfs_machdep.c: revision 1.35
sys/arch/x86/x86/procfs_machdep.c: revision 1.36

Add Fast Short Rep Mov(fsrm).

Add AVX512_VP2INTERSECT, SERIALIZE and TSXLDTRK(TSX suspend load addr tracking)

CPUID Fn00000001 %edx bit 8 is printed as "TSC", so rename CPUID Fn8000_0007
%edx bit 8 from "TSC" to "ITSC" (Invariant TSC) to avoid confusion.

Rename CPUID_APM_TSC to CPUID_APM_ITSC. No functional change.

Remove ci_max_ext_cpuid because it's the same as ci_cpuid_extlevel.

Print CPUID 0x80000007 %edx on both Intel and AMD.
 1.150.2.5  19-Nov-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #452):

usr.sbin/cpuctl/arch/i386.c: revision 1.108
sys/arch/x86/include/specialreg.h: revision 1.158

Add the following bit definitions from the latest Intel SDM:
- CET shadow stack
- Fast Short REP MOV
- Hybrid part
- CET Indirect Branch Tracking
0x7d and 0x7e are for 10th generation Core (Ice Lake).
 1.150.2.4  12-Nov-2019  martin Pull up following revision(s) (requested by maxv in ticket #419):

sys/arch/x86/include/specialreg.h: revision 1.157
sys/arch/x86/x86/spectre.c: revision 1.31

Mitigation for CVE-2019-11135: TSX Asynchronous Abort (TAA).

Two sysctls are added:
machdep.taa.mitigated = {0/1} user-settable
machdep.taa.method = {string} constructed by the kernel

There are two cases:

(1) If the CPU is affected by MDS, then the MDS mitigation will also
mitigate TAA, and we have nothing else to do. We make the 'mitigated' leaf
read-only, and force:

machdep.taa.mitigated = machdep.mds.mitigated
machdep.taa.method = [MDS]

The kernel already enables the MDS mitigation by default.

(2) If the CPU is not affected by MDS but is affected by TAA, then we use
the new TSX_CTRL MSR to disable RTM. This MSR is provided via a microcode
update, now available on the Intel website. The kernel will automatically
enable the TAA mitigation if the updated microcode is present. If the new
microcode is not present, the user can load it via cpuctl, and set
machdep.taa.mitigated=1.
 1.150.2.3  10-Nov-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #407):

sys/arch/x86/include/specialreg.h: revision 1.156

- GMET is not bit 11 but 17.
- Add unknown CPUID Fn8000_000a %edx bit 20.
 1.150.2.2  17-Oct-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #344):

sys/arch/x86/include/specialreg.h: revision 1.154
sys/arch/x86/include/specialreg.h: revision 1.155
usr.sbin/cpuctl/arch/i386.c: revision 1.107
sys/arch/x86/x86/procfs_machdep.c: revision 1.34

- Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.

Fix AMD Fn8000_0001f %eax bit 0's name.

Add rdpru.
 1.150.2.1  26-Sep-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #241):

sys/arch/x86/include/specialreg.h: revision 1.152
sys/arch/x86/include/specialreg.h: revision 1.153
usr.sbin/cpuctl/arch/i386.c: revision 1.105
sys/arch/x86/x86/spectre.c: revision 1.30
sys/arch/x86/include/specialreg.h: revision 1.151

Add definitions of AMD's CPUID Fn8000_0008 %ebx.
Decode AMD's CPUID Fn8000_0008 %ebx.
Use macro.
Add MCOMMIT instruction.
Define CPUID_CAPEX_FLAGS's bit 10 correctly.
 1.161.2.1  25-Apr-2020  bouyer Sync with bouyer-xenpvh-base2 (HEAD)
 1.175.2.1  14-Dec-2020  thorpej Sync w/ HEAD.
 1.176.4.1  01-Aug-2021  thorpej Sync with HEAD.
 1.198.2.6  03-Oct-2024  martin Pull up following revision(s) (requested by rin in ticket #919):

sys/arch/x86/x86/errata.c: revision 1.28
sys/arch/x86/x86/errata.c: revision 1.29
sys/arch/x86/include/specialreg.h: revision 1.209
usr.sbin/cpuctl/arch/i386.c: revision 1.144
sys/arch/x86/x86/errata.c: revision 1.30
sys/arch/x86/x86/errata.c: revision 1.33
sys/arch/x86/x86/errata.c: revision 1.34
sys/arch/x86/x86/errata.c: revision 1.35
sys/arch/x86/include/specialreg.h: revision 1.210
sys/arch/x86/include/specialreg.h: revision 1.211

x86/errata.c: Link to original AMD errata guide.

This one is no longer updated; need to link to newer ones for
individual families too. That's where all the cryptic nomenclature
comes from here.

x86/errata.c: Say what revision we're searching for.

x86/errata.c: Only say the errata revision search for cpu0.

x86: make the CPUID list for errata be far less confusing
the 0x80000001 CPUID result needs some parsing to match against
actual family/model/stepping values. 4-bit 'family' values of
15 or 6 change how to parse the 4-bit extended model and 8-bit
extended family value - for family 6 or 15, the extended model
bits (4) are concatenated with the base 4-bits to create an
8-bit value, and for family 15, the family value is addition
of the family value and the 8-bit extended-family value, giving
a range of 0 to 15 + 0xff aka 270.

use a CPUREV(family, model, stepping) macro that builds the
relevant bit-representation of a CPUID, making it far easier
to understand what each entry means, and to add new ones too.
i have confirmed that the emitted cpurevs[] array has the same
values before/after this change, ie, NFCI or observed.

x86: add names for errata that don't have actual numbers
zenbleed is reported as "erratum 65535" currently, this adds a name
for it, and enables the name for any others as well.
pull logging into a function with a tag message.

x86: handle AMD errata 1474: A CPU core may hang after about 1044 days
from the new comment:
* This requires disabling CC6 power level, which can be a performance
* issue since it stops full turbo in some implementations (eg, half the
* cores must be in CC6 to achieve the highest boost level.) Set a timer
* to fire in 1000 days -- except NetBSD timers end up having a signed
* 32-bit hz-based value, which rolls over in under 25 days with HZ=1000,
* and doing xcall(9) or kthread(9) from a callout is not allowed anyway,
* so just have a kthread wait 1 day for 1000 times.
documented in:
https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/revision-guides/56323-PUB_1_01.pdf

add MSR stuff for AMD errata 1474.

cpuctl: fix i386 bit descriptions for CPUID_SEF_FLAGS1
warning: non-printing character '\31' in description
'BUS_LOCK_DETECT""b\31' [363]
s/RPMQUERY/RMPQUERY/
 1.198.2.5  20-Jul-2024  martin Pull up following revision(s) (requested by andvar in ticket #738):

sys/arch/x86/x86/identcpu.c: revision 1.129
sys/arch/x86/include/specialreg.h: revision 1.212
sys/arch/x86/x86/identcpu.c: revision 1.130

Disable the VIA Alternate Instructions according the VIA documentation:
* C7 and above do not support ALTINST, do not check or attempt to disable them.
* For VIA C3 Nehemiah check extended feature flags for support and status,
do no attempt to disable when AIS is not supported or enabled.
* For pre-Nehemiah models explicitly disable, if they are in the range
of documented models, flags aren't present to check the status on
these models.

Note: for pre-Nehemiah may be other functional side effects depdending
on the version and stepping.

Explicit disabling of ALTINST was introduced with rev. 1.84 following
the discovery of some VIA CPUs having these instructions enabled by default
leading to the potential backdoor (aka rosenbrindge).

Unfortunately, implementation used a wrong check (ACE supported flag),
which can be true for the later models, still supporting padlock features.

Setting ALTINST bit on those may have unexpected side effects like VIA C7 CPUID
instruction for temperature sensor not reporting correct value or
`cpuctl identify' not reporting certain CPU features. Similar side effects
can be observed even for Nehemiah models not supporting AIS instructions. This
change should limit possibility of such issues to only the pre-Nehemiah models,
not covered at all in the previous implementation.

Feature Control Register (FCR) macros were unified under one group and
consistent naming while implementing the change. Few comments updated as well.
patch reviewed by Riastradh@ (thank you)

PR kern/58370

Move determination of the largest VIA CPU extended function value
to the intended place where the checks are performed.
Currently the value can be overridden while checking for the padlock features,
and failing the check for max function value as a result.
 1.198.2.4  29-Jul-2023  martin Pull up the following revisions, all via patch, requested by msaitoh
in ticket #250:

sys/arch/x86/include/specialreg.h 1.204-1.206, 1.208

- Add Intel CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT.
- Add AMD CPUID 0x80000008 %ebx bit 30 IBPB_RET and CPUID 0x8000000a
%edx bit 29 BusLockThreshold.
- Fix typo in comment.
 1.198.2.3  25-Jul-2023  martin Pull up following revision(s) (requested by mrg in ticket #243):

sys/arch/x86/include/specialreg.h: revision 1.207
sys/arch/x86/x86/errata.c: revision 1.31

x86: turn off zenbleed chicken bit on Zen2 cpus.

this is based upon Taylor's original work. i just made the list
of CPUs to run on correct as i could determine. (also, add some
Zen3 and Zen4 cpuids not yet used by any errata.)

(might be nice to have a better way to expression revision ranges
rather than specific cpuid matches, eg, 0x30-0x4f models in a cpu
family, etc.)

tested on ryzen 3600, and a ported zenbleed PoC that no longer
shows any obtained text. (a similar module-version of it stopped
the PoC on a ryzen 3950x without having to reboot.)

https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7008.html
https://lock.cmpxchg8b.com/zenbleed.html
 1.198.2.2  21-Jun-2023  martin Pull up following revision(s) (requested by msaitoh in ticket #200):

sys/arch/x86/include/specialreg.h: revision 1.202
sys/arch/x86/include/specialreg.h: revision 1.203
usr.sbin/cpuctl/arch/i386.c: revision 1.136

Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.

Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.
 1.198.2.1  23-Jan-2023  martin Pull up following revision(s) (requested by msaitoh in ticket #56):

sys/arch/x86/include/specialreg.h: revision 1.200
sys/arch/x86/include/specialreg.h: revision 1.201
sys/arch/x86/include/specialreg.h: revision 1.199

Use __BIT(). Add comment. Whitespace. No functional change.

Update definitions from the latest Intel SDM.
- Rename HW_FEEDBACK to HWI (Hardware Feedback Interface).
- Add CPUID Fn0000_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25 Hardware
Feedback Notification support.
- Add CPUID Fn0000_0007 %ecx bit 29 ENQCMD.
- Add CPUID Fn0000_0007 %edx bit 1 SGX-KEYS.
- Add CPUID Fn0000_0007 %edx bit 5 UINTR(User INTeRrupts).
- Add CPUID Fn0000_0007 %edx bit 1 RTM_ALWAYS_ABORT.
- Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT.
- Add CPUID Fn0000_0007 %edx bit 22 AMX_BF16.
- Add CPUID Fn0000_0007 %edx bit 23 AVX512_FP16.
- Add CPUID Fn0000_0007 %edx bit 24 AMX_TILE.
- Add CPUID Fn0000_0007 %edx bit 25 AMX_INT8.
- Add CPUID Fn0000_0007 sub-leaf 1 %edx bit 18 CET_SSS.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 0 PSFD.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 1 IPRED_CTRL.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 2 RRSBA_CTRL.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 3 DDPD_U.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 4 BHI_CTRL.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 5 MCDT_NO.
- Modify comment. Both Intel and AMD support CPUID Fn0000000b.
- Add CPUID Fn0000_000d sub-leaf 1 %eax bit 4 XFD.
- Modify comment. Hybrid Information -> Native Model ID Information.
- Add CPUID Fn0000_001d Tile Information.
- Add CPUID Fn0000_001e TMUL Information.

Fix comment.
 1.211.2.1  02-Aug-2025  perseant Sync with HEAD

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