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    Searched refs:AR_CR (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/isc/atheros_hal/dist/ar5211/
ar5211_recv.c 55 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
64 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
65 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
68 "AR_CR=0x%08X\nAR_DIAG_SW=0x%08X\n"
70 , OS_REG_READ(ah, AR_CR)
ar5211reg.h 32 #define AR_CR 0x0008 /* control register */
  /src/sys/external/isc/atheros_hal/dist/ar5210/
ar5210_recv.c 54 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
65 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
67 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
73 ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR));
ar5210_xmit.c 300 if (OS_REG_READ(ah, AR_CR) & AR_CR_TXE0)
301 ath_hal_printf(ah, "%s: TXE asserted; AR_CR=0x%x\n",
302 __func__, OS_REG_READ(ah, AR_CR));
378 OS_REG_WRITE(ah, AR_CR, AR_CR_TXE0);
381 OS_REG_WRITE(ah, AR_CR, AR_CR_TXE1); /* enable altq xmit */
440 OS_REG_WRITE(ah, AR_CR, AR_CR_TXD0);
446 OS_REG_WRITE(ah, AR_CR, 0);
ar5210reg.h 36 #define AR_CR 0x0008 /* Command register */
  /src/sys/external/isc/atheros_hal/dist/ar5212/
ar5212_recv.c 53 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
62 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
63 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
66 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
68 OS_REG_READ(ah, AR_CR),
ar5212reg.h 27 #define AR_CR 0x0008 /* MAC control register */
  /src/sys/dev/ic/
athnreg.h 27 #define AR_CR 0x0008
259 /* Bits for AR_CR. */
athn.c 1780 AR_WRITE(sc, AR_CR, AR_CR_RXD);
1783 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE))
arn5008.c 719 AR_WRITE(sc, AR_CR, AR_CR_RXE);
954 AR_WRITE(sc, AR_CR, AR_CR_RXE);
arn9003.c 870 AR_WRITE(sc, AR_CR, 0);
1084 AR_WRITE(sc, AR_CR, 0);
  /src/sys/dev/usb/
if_athn_usb.c 1733 AR_WRITE(sc, AR_CR, AR_CR_RXE);

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