| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| b0.S | 8 ASTAT = R0; 13 _DBG ASTAT; 14 R0 = ASTAT; CHECKREG R0, (_AC0|_AC0_COPY|_CC|_AZ); 16 R0 = ASTAT; CHECKREG R0, (_CC); 19 R0 = ASTAT; CHECKREG R0, (_CC|_AN); 21 R0 = ASTAT; CHECKREG R0, (_CC|_AN); 24 _DBG ASTAT; 25 R0 = ASTAT; CHECKREG R0, (_AC0|_CC|_AN); 28 _DBG ASTAT; 29 R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_CC|_AN) [all...] |
| random_0004.S | 1 # Test for ASTAT bits being written when they shouldn't (only a reg mov) 9 dmm32 ASTAT, (0x1c304e90 | _VS | _V | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); 15 checkreg ASTAT, (0x1c304e90 | _VS | _V | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); 17 dmm32 ASTAT, (0x6cd08a00 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _AN | _AZ); 23 checkreg ASTAT, (0x6cd08a00 | _VS | _V | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY); 25 dmm32 ASTAT, (0x60700280 | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN); 31 checkreg ASTAT, (0x60700280 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN);
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| c_ccflag_pr_imm3.s | 21 ASTAT = R0; 24 R0 = ASTAT; 26 R1 = ASTAT; 28 R2 = ASTAT; 30 R3 = ASTAT; 32 R4 = ASTAT; 34 R5 = ASTAT; 43 R0 = ASTAT; 45 R1 = ASTAT; 47 R2 = ASTAT; [all...] |
| c_ccflag_dr_dr.s | 19 ASTAT = R7; 20 R4 = ASTAT; 24 R5 = ASTAT; 26 R6 = ASTAT; 28 R7 = ASTAT; 34 R4 = ASTAT; 36 R5 = ASTAT; 42 R5 = ASTAT; 44 R6 = ASTAT; 46 R7 = ASTAT; [all...] |
| c_ccflag_dr_imm3.s | 19 ASTAT = R7; 20 R4 = ASTAT; 24 R5 = ASTAT; 26 R6 = ASTAT; 31 R5 = ASTAT; 33 R6 = ASTAT; 35 R7 = ASTAT; 42 R5 = ASTAT; 44 R6 = ASTAT; 46 R7 = ASTAT; [all...] |
| c_ccflag_dr_imm3_uu.s | 19 ASTAT = R7; 20 R4 = ASTAT; 24 R5 = ASTAT; 26 R6 = ASTAT; 31 R5 = ASTAT; 33 R6 = ASTAT; 35 R7 = ASTAT; 42 R5 = ASTAT; 44 R6 = ASTAT; 46 R7 = ASTAT; [all...] |
| a20.S | 8 ASTAT = R1; 14 _DBG ASTAT; 15 R7 = ASTAT; 21 _DBG ASTAT; 22 R7 = ASTAT; 26 ASTAT = R0; 27 _DBG ASTAT; 28 R7 = ASTAT; 35 _DBG ASTAT; 36 R7 = ASTAT; [all...] |
| c_ccflag_pr_imm3_uu.s | 23 ASTAT = R0; 26 R0 = ASTAT; 28 R1 = ASTAT; 30 R2 = ASTAT; 32 R3 = ASTAT; 34 R4 = ASTAT; 36 R5 = ASTAT; 45 R0 = ASTAT; 47 R1 = ASTAT; 49 R2 = ASTAT; [all...] |
| c_cc2stat_cc_ac.S | 20 ASTAT = R7; // cc = 0, AC0 = 0 25 ASTAT = R7; // cc = 0, AC0 = 1 30 ASTAT = R7; // cc = 1, AC0 = 0 35 ASTAT = R7; // cc = 1, AC0 = 1 41 ASTAT = R7; // cc = 0, AC0 = 0 46 ASTAT = R7; // cc = 0, AC0 = 1 51 ASTAT = R7; // cc = 1, AC0 = 0 56 ASTAT = R7; // cc = 1, AC0 = 1 71 ASTAT = R7; // cc = 0, AC0 = 0 76 ASTAT = R7; // cc = 0, AC0 = [all...] |
| c_cc2stat_cc_an.s | 21 ASTAT = R7; // cc = 0, AN = 0 26 ASTAT = R7; // cc = 0, AN = 1 31 ASTAT = R7; // cc = 1, AN = 0 36 ASTAT = R7; // cc = 1, AN = 1 42 ASTAT = R7; // cc = 0, AN = 0 47 ASTAT = R7; // cc = 0, AN = 1 52 ASTAT = R7; // cc = 1, AN = 0 57 ASTAT = R7; // cc = 1, AN = 1 72 ASTAT = R7; // cc = 0, AN = 0 77 ASTAT = R7; // cc = 0, AN = [all...] |
| c_cc2stat_cc_aq.s | 21 ASTAT = R7; // cc = 0, AQ = 0 26 ASTAT = R7; // cc = 0, AQ = 1 31 ASTAT = R7; // cc = 1, AQ = 0 36 ASTAT = R7; // cc = 1, AQ = 1 42 ASTAT = R7; // cc = 0, AQ = 0 47 ASTAT = R7; // cc = 0, AQ = 1 52 ASTAT = R7; // cc = 1, AQ = 0 57 ASTAT = R7; // cc = 1, AQ = 1 72 ASTAT = R7; // cc = 0, AQ = 0 77 ASTAT = R7; // cc = 0, AQ = [all...] |
| c_cc2stat_cc_av0.S | 21 ASTAT = R7; // cc = 0, AV0 = 0 26 ASTAT = R7; // cc = 0, AV0 = 1 31 ASTAT = R7; // cc = 1, AV0 = 0 36 ASTAT = R7; // cc = 1, AV0 = 1 42 ASTAT = R7; // cc = 0, AV0 = 0 47 ASTAT = R7; // cc = 0, AV0 = 1 52 ASTAT = R7; // cc = 1, AV0 = 0 57 ASTAT = R7; // cc = 1, AV0 = 1 72 ASTAT = R7; // cc = 0, AV0 = 0 77 ASTAT = R7; // cc = 0, AV0 = [all...] |
| c_cc2stat_cc_av1.S | 20 ASTAT = R7; // cc = 0, AV1 = 0 25 ASTAT = R7; // cc = 0, AV1 = 1 30 ASTAT = R7; // cc = 1, AV1 = 0 35 ASTAT = R7; // cc = 1, AV1 = 1 41 ASTAT = R7; // cc = 0, AV1 = 0 46 ASTAT = R7; // cc = 0, AV1 = 1 51 ASTAT = R7; // cc = 1, AV1 = 0 56 ASTAT = R7; // cc = 1, AV1 = 1 71 ASTAT = R7; // cc = 0, AV1 = 0 76 ASTAT = R7; // cc = 0, AV1 = [all...] |
| c_cc2stat_cc_az.s | 21 ASTAT = R7; // cc = 0, AZ = 0 26 ASTAT = R7; // cc = 0, AZ = 1 31 ASTAT = R7; // cc = 1, AZ = 0 36 ASTAT = R7; // cc = 1, AZ = 1 42 ASTAT = R7; // cc = 0, AZ = 0 47 ASTAT = R7; // cc = 0, AZ = 1 52 ASTAT = R7; // cc = 1, AZ = 0 57 ASTAT = R7; // cc = 1, AZ = 1 72 ASTAT = R7; // cc = 0, AZ = 0 77 ASTAT = R7; // cc = 0, AZ = [all...] |
| issue126.s | 7 ASTAT = R0; 15 _DBG ASTAT; 16 R5 = ASTAT;
|
| issue140.S | 8 ASTAT = R0; 17 _DBG ASTAT; 19 R7 = ASTAT;
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| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| b0.S | 8 ASTAT = R0; 13 _DBG ASTAT; 14 R0 = ASTAT; CHECKREG R0, (_AC0|_AC0_COPY|_CC|_AZ); 16 R0 = ASTAT; CHECKREG R0, (_CC); 19 R0 = ASTAT; CHECKREG R0, (_CC|_AN); 21 R0 = ASTAT; CHECKREG R0, (_CC|_AN); 24 _DBG ASTAT; 25 R0 = ASTAT; CHECKREG R0, (_AC0|_CC|_AN); 28 _DBG ASTAT; 29 R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_CC|_AN) [all...] |
| random_0004.S | 1 # Test for ASTAT bits being written when they shouldn't (only a reg mov) 9 dmm32 ASTAT, (0x1c304e90 | _VS | _V | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); 15 checkreg ASTAT, (0x1c304e90 | _VS | _V | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY); 17 dmm32 ASTAT, (0x6cd08a00 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _AN | _AZ); 23 checkreg ASTAT, (0x6cd08a00 | _VS | _V | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY); 25 dmm32 ASTAT, (0x60700280 | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN); 31 checkreg ASTAT, (0x60700280 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN);
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| c_ccflag_pr_imm3.s | 21 ASTAT = R0; 24 R0 = ASTAT; 26 R1 = ASTAT; 28 R2 = ASTAT; 30 R3 = ASTAT; 32 R4 = ASTAT; 34 R5 = ASTAT; 43 R0 = ASTAT; 45 R1 = ASTAT; 47 R2 = ASTAT; [all...] |
| c_ccflag_dr_dr.s | 19 ASTAT = R7; 20 R4 = ASTAT; 24 R5 = ASTAT; 26 R6 = ASTAT; 28 R7 = ASTAT; 34 R4 = ASTAT; 36 R5 = ASTAT; 42 R5 = ASTAT; 44 R6 = ASTAT; 46 R7 = ASTAT; [all...] |
| c_ccflag_dr_imm3.s | 19 ASTAT = R7; 20 R4 = ASTAT; 24 R5 = ASTAT; 26 R6 = ASTAT; 31 R5 = ASTAT; 33 R6 = ASTAT; 35 R7 = ASTAT; 42 R5 = ASTAT; 44 R6 = ASTAT; 46 R7 = ASTAT; [all...] |
| c_ccflag_dr_imm3_uu.s | 19 ASTAT = R7; 20 R4 = ASTAT; 24 R5 = ASTAT; 26 R6 = ASTAT; 31 R5 = ASTAT; 33 R6 = ASTAT; 35 R7 = ASTAT; 42 R5 = ASTAT; 44 R6 = ASTAT; 46 R7 = ASTAT; [all...] |
| a20.S | 8 ASTAT = R1; 14 _DBG ASTAT; 15 R7 = ASTAT; 21 _DBG ASTAT; 22 R7 = ASTAT; 26 ASTAT = R0; 27 _DBG ASTAT; 28 R7 = ASTAT; 35 _DBG ASTAT; 36 R7 = ASTAT; [all...] |
| c_ccflag_pr_imm3_uu.s | 23 ASTAT = R0; 26 R0 = ASTAT; 28 R1 = ASTAT; 30 R2 = ASTAT; 32 R3 = ASTAT; 34 R4 = ASTAT; 36 R5 = ASTAT; 45 R0 = ASTAT; 47 R1 = ASTAT; 49 R2 = ASTAT; [all...] |
| c_cc2stat_cc_ac.S | 20 ASTAT = R7; // cc = 0, AC0 = 0 25 ASTAT = R7; // cc = 0, AC0 = 1 30 ASTAT = R7; // cc = 1, AC0 = 0 35 ASTAT = R7; // cc = 1, AC0 = 1 41 ASTAT = R7; // cc = 0, AC0 = 0 46 ASTAT = R7; // cc = 0, AC0 = 1 51 ASTAT = R7; // cc = 1, AC0 = 0 56 ASTAT = R7; // cc = 1, AC0 = 1 71 ASTAT = R7; // cc = 0, AC0 = 0 76 ASTAT = R7; // cc = 0, AC0 = [all...] |