1 //Original:/testcases/core/c_cc2stat_cc_ac/c_cc2stat_cc_ac.dsp 2 // Spec Reference: cc2stat cc ac 3 # mach: bfin 4 5 #include "test.h" 6 .include "testutils.inc" 7 start 8 9 imm32 r0, _UNSET; 10 imm32 r1, _UNSET; 11 imm32 r2, _UNSET; 12 imm32 r3, _UNSET; 13 imm32 r4, _UNSET; 14 imm32 r5, _UNSET; 15 imm32 r6, _UNSET; 16 imm32 r7, _UNSET; 17 18 // test CC = AC 0-0, 0-1, 1-0, 1-1 19 imm32 R7, 0x00; 20 ASTAT = R7; // cc = 0, AC0 = 0 21 CC = AC0; // 22 R0 = CC; // 23 24 imm32 R7, _AC0; 25 ASTAT = R7; // cc = 0, AC0 = 1 26 CC = AC0; // 27 R1 = CC; // 28 29 imm32 R7, _CC; 30 ASTAT = R7; // cc = 1, AC0 = 0 31 CC = AC0; // 32 R2 = CC; // 33 34 imm32 R7, (_CC|_AC0); 35 ASTAT = R7; // cc = 1, AC0 = 1 36 CC = AC0; // 37 R3 = CC; // 38 39 // test cc |= AC (0-0, 0-1, 1-0, 1-1) 40 imm32 R7, 0x00; 41 ASTAT = R7; // cc = 0, AC0 = 0 42 CC |= AC0; // 43 R4 = CC; // 44 45 imm32 R7, _AC0; 46 ASTAT = R7; // cc = 0, AC0 = 1 47 CC |= AC0; // 48 R5 = CC; // 49 50 imm32 R7, (_CC|_AC0); 51 ASTAT = R7; // cc = 1, AC0 = 0 52 CC |= AC0; // 53 R6 = CC; // 54 55 imm32 R7, (_CC|_AC0); 56 ASTAT = R7; // cc = 1, AC0 = 1 57 CC |= AC0; // 58 R7 = CC; // 59 60 CHECKREG r0, _UNSET; 61 CHECKREG r1, _SET; 62 CHECKREG r2, _UNSET; 63 CHECKREG r3, _SET; 64 CHECKREG r4, _UNSET; 65 CHECKREG r5, _SET; 66 CHECKREG r6, _SET; 67 CHECKREG r7, _SET; 68 69 // test CC &= AC (0-0, 0-1, 1-0, 1-1) 70 imm32 R7, 0x00; 71 ASTAT = R7; // cc = 0, AC0 = 0 72 CC &= AC0; // 73 R4 = CC; // 74 75 imm32 R7, _AC0; 76 ASTAT = R7; // cc = 0, AC0 = 1 77 CC &= AC0; // 78 R5 = CC; // 79 80 imm32 R7, _CC; 81 ASTAT = R7; // cc = 1, AC0 = 0 82 CC &= AC0; // 83 R6 = CC; // 84 85 imm32 R7, (_CC|_AC0); 86 ASTAT = R7; // cc = 1, AC0 = 1 87 CC &= AC0; // 88 R7 = CC; // 89 90 CHECKREG r0, _UNSET; 91 CHECKREG r1, _SET; 92 CHECKREG r2, _UNSET; 93 CHECKREG r3, _SET; 94 CHECKREG r4, _UNSET; 95 CHECKREG r5, _UNSET; 96 CHECKREG r6, _UNSET; 97 CHECKREG r7, _SET; 98 99 // test CC ^= AC (0-0, 0-1, 1-0, 1-1) 100 imm32 R7, 0x00; 101 ASTAT = R7; // cc = 0, AC0 = 0 102 CC ^= AC0; // 103 R4 = CC; // 104 105 imm32 R7, _AC0; 106 ASTAT = R7; // cc = 0, AC0 = 1 107 CC ^= AC0; // 108 R5 = CC; // 109 110 imm32 R7, _CC; 111 ASTAT = R7; // cc = 1, AC0 = 0 112 CC ^= AC0; // 113 R6 = CC; // 114 115 imm32 R7, (_CC|_AC0); 116 ASTAT = R7; // cc = 1, AC0 = 1 117 CC ^= AC0; // 118 R7 = CC; // 119 120 CHECKREG r0, _UNSET; 121 CHECKREG r1, _SET; 122 CHECKREG r2, _UNSET; 123 CHECKREG r3, _SET; 124 CHECKREG r4, _UNSET; 125 CHECKREG r5, _SET; 126 CHECKREG r6, _SET; 127 CHECKREG r7, _UNSET; 128 129 // test AC0 = CC 0-0, 0-1, 1-0, 1-1 130 imm32 R7, 0x00; 131 ASTAT = R7; // cc = 0, AC0 = 0 132 AC0 = CC; // 133 R0 = ASTAT; // 134 135 imm32 R7, _AC0; 136 ASTAT = R7; // cc = 0, AC0 = 1 137 AC0 = CC; // 138 R1 = ASTAT; // 139 140 imm32 R7, _CC; 141 ASTAT = R7; // cc = 1, AC0 = 0 142 AC0 = CC; // 143 R2 = ASTAT; // 144 145 imm32 R7, (_CC|_AC0); 146 ASTAT = R7; // cc = 1, AC0 = 1 147 AC0 = CC; // 148 R3 = ASTAT; // 149 150 // test AC0 |= CC (0-0, 0-1, 1-0, 1-1) 151 imm32 R7, 0x00; 152 ASTAT = R7; // cc = 0, AC0 = 0 153 AC0 |= CC; // 154 R4 = ASTAT; // 155 156 imm32 R7, _AC0; 157 ASTAT = R7; // cc = 0, AC0 = 1 158 AC0 |= CC; // 159 R5 = ASTAT; // 160 161 imm32 R7, _CC; 162 ASTAT = R7; // cc = 1, AC0 = 0 163 AC0 |= CC; // 164 R6 = ASTAT; // 165 166 imm32 R7, (_CC|_AC0); 167 ASTAT = R7; // cc = 1, AC0 = 1 168 AC0 |= CC; // 169 R7 = ASTAT; // 170 171 CHECKREG r0, _UNSET; 172 CHECKREG r1, _UNSET; 173 CHECKREG r2, (_AC0|_CC); 174 CHECKREG r3, (_CC|_AC0); 175 CHECKREG r4, _UNSET; 176 CHECKREG r5, (_AC0); 177 CHECKREG r6, (_AC0|_CC); 178 CHECKREG r7, (_CC|_AC0); 179 180 // test AC0 &= CC (0-0, 0-1, 1-0, 1-1) 181 imm32 R7, 0x00; 182 ASTAT = R7; // cc = 0, AC0 = 0 183 AC0 &= CC; // 184 R4 = ASTAT; // 185 186 imm32 R7, _AC0; 187 ASTAT = R7; // cc = 0, AC0 = 1 188 AC0 &= CC; // 189 R5 = ASTAT; // 190 191 imm32 R7, _CC; 192 ASTAT = R7; // cc = 1, AC0 = 0 193 AC0 &= CC; // 194 R6 = ASTAT; // 195 196 imm32 R7, (_CC|_AC0); 197 ASTAT = R7; // cc = 1, AC0 = 1 198 AC0 &= CC; // 199 R7 = ASTAT; // 200 201 CHECKREG r0, _UNSET; 202 CHECKREG r1, _UNSET; 203 CHECKREG r2, (_CC|_AC0); 204 CHECKREG r3, (_CC|_AC0); 205 CHECKREG r4, _UNSET; 206 CHECKREG r5, _UNSET; 207 CHECKREG r6, _CC; 208 CHECKREG r7, (_CC|_AC0); 209 210 // test AC0 ^= CC (0-0, 0-1, 1-0, 1-1) 211 imm32 R7, 0x00; 212 ASTAT = R7; // cc = 0, AC0 = 0 213 AC0 ^= CC; // 214 R4 = ASTAT; // 215 216 imm32 R7, _AC0; 217 ASTAT = R7; // cc = 0, AC0 = 1 218 AC0 ^= CC; // 219 R5 = ASTAT; // 220 221 imm32 R7, _CC; 222 ASTAT = R7; // cc = 1, AC0 = 0 223 AC0 ^= CC; // 224 R6 = ASTAT; // 225 226 imm32 R7, (_CC|_AC0); 227 ASTAT = R7; // cc = 1, AC0 = 1 228 AC0 ^= CC; // 229 R7 = ASTAT; // 230 231 CHECKREG r0, _UNSET; 232 CHECKREG r1, _UNSET; 233 CHECKREG r2, (_CC|_AC0); 234 CHECKREG r3, (_CC|_AC0); 235 CHECKREG r4, _UNSET; 236 CHECKREG r5, (_AC0); 237 CHECKREG r6, (_CC|_AC0); 238 CHECKREG r7, _CC; 239 240 pass 241
Indexes created Sun Apr 26 00:22:38 UTC 2026