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    Searched refs:BIT5 (Results 1 - 20 of 20) sorted by relevancy

  /src/external/gpl3/gdb/dist/sim/ppc/
idecode_fields.h 92 #define TO_0_ ((TO & BIT5(0)) != 0)
93 #define TO_1_ ((TO & BIT5(1)) != 0)
94 #define TO_2_ ((TO & BIT5(2)) != 0)
95 #define TO_3_ ((TO & BIT5(3)) != 0)
96 #define TO_4_ ((TO & BIT5(4)) != 0)
98 #define BO_0_ ((BO & BIT5(0)) != 0)
99 #define BO_1_ ((BO & BIT5(1)) != 0)
100 #define BO_2_ ((BO & BIT5(2)) != 0)
101 #define BO_3_ ((BO & BIT5(3)) != 0)
102 #define BO_4_ ((BO & BIT5(4)) != 0
    [all...]
bits.h 96 #define BIT5(POS) (1 << _MAKE_SHIFT(5, POS))
  /src/external/gpl3/gdb.old/dist/sim/ppc/
idecode_fields.h 92 #define TO_0_ ((TO & BIT5(0)) != 0)
93 #define TO_1_ ((TO & BIT5(1)) != 0)
94 #define TO_2_ ((TO & BIT5(2)) != 0)
95 #define TO_3_ ((TO & BIT5(3)) != 0)
96 #define TO_4_ ((TO & BIT5(4)) != 0)
98 #define BO_0_ ((BO & BIT5(0)) != 0)
99 #define BO_1_ ((BO & BIT5(1)) != 0)
100 #define BO_2_ ((BO & BIT5(2)) != 0)
101 #define BO_3_ ((BO & BIT5(3)) != 0)
102 #define BO_4_ ((BO & BIT5(4)) != 0
    [all...]
bits.h 96 #define BIT5(POS) (1 << _MAKE_SHIFT(5, POS))
  /src/external/bsd/zstd/dist/lib/common/
zstd_internal.h 73 #define BIT5 32
  /src/sys/dev/pci/
unichromefb.c 702 uni_wr_mask(sc, VIACR, CR36, 0, BIT5+BIT4);
708 uni_wr_mask(sc, VIACR, CR36, BIT5+BIT4, BIT5+BIT4);
714 uni_wr_mask(sc, VIASR, SR01, 0, BIT5);
720 uni_wr_mask(sc, VIASR, SR01, 0x20, BIT5);
787 uni_wr_mask(sc, VIACR, CR11, 0x00, BIT4+BIT5+BIT6);
unichromereg.h 57 #define BIT5 0x20
  /src/external/gpl3/gdb.old/dist/sim/common/
sim-bits.h 252 #define BIT5(POS) (1 << _LSB_SHIFT (5, (POS)))
  /src/external/gpl3/gdb/dist/sim/common/
sim-bits.h 252 #define BIT5(POS) (1 << _LSB_SHIFT (5, (POS)))
  /src/external/gpl3/binutils/dist/opcodes/
sparc-opc.c 1935 #define BIT5 (1<<5)
1936 { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, 0, 0, sparclet },
1937 { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, 0, 0, sparclet },
1938 { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet },
1940 { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet },
1942 { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, 0, 0, sparclet },
1943 #undef BIT5
  /src/external/gpl3/binutils.old/dist/opcodes/
sparc-opc.c 1935 #define BIT5 (1<<5)
1936 { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, 0, 0, sparclet },
1937 { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, 0, 0, sparclet },
1938 { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet },
1940 { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet },
1942 { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, 0, 0, sparclet },
1943 #undef BIT5
  /src/external/gpl3/gdb.old/dist/opcodes/
sparc-opc.c 1935 #define BIT5 (1<<5)
1936 { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, 0, 0, sparclet },
1937 { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, 0, 0, sparclet },
1938 { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet },
1940 { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet },
1942 { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, 0, 0, sparclet },
1943 #undef BIT5
  /src/external/gpl3/gdb/dist/opcodes/
sparc-opc.c 1935 #define BIT5 (1<<5)
1936 { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, 0, 0, sparclet },
1937 { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, 0, 0, sparclet },
1938 { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet },
1940 { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet },
1942 { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, 0, 0, sparclet },
1943 #undef BIT5
  /src/external/bsd/zstd/dist/lib/legacy/
zstd_v01.c 1277 #define BIT5 32
zstd_v03.c 2282 #define BIT5 32
zstd_v04.c 301 #define BIT5 32
zstd_v02.c 2642 #define BIT5 32
zstd_v06.c 411 #define BIT5 32
zstd_v07.c 2649 #define BIT5 32
  /src/sys/external/bsd/acpica/dist/tests/misc/
grammar.asl 5130 BIT5, 1, // single bit field entry
5229 Store (0, BIT5)
5231 If (LNotEqual (BIT5, 0))
6695 BIT5, 1, // single-bit field
6752 // be set. BIT4, BIT6. BIT5 and BIT7 should be clear.
6758 If (BIT5)

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