1 /* $NetBSD: unichromereg.h,v 1.1 2006/08/02 01:44:09 jmcneill Exp $ */ 2 3 /* 4 * Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved. 5 * Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sub license, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 */ 26 27 #ifndef _DEV_PCI_UNICHROMEREG_H 28 #define _DEV_PCI_UNICHROMEREG_H 29 30 /* Define Return Value */ 31 #define FAIL -1 32 #define OK 1 33 34 /* S.T.Chen[2005.12.26]: Define Boolean Value */ 35 #ifndef bool 36 typedef int bool; 37 #endif 38 39 #ifndef TRUE 40 #define TRUE 1 41 #endif 42 43 #ifndef FALSE 44 #define FALSE 0 45 #endif 46 47 #ifndef NULL 48 #define NULL 0 49 #endif 50 51 /* Define Bit Field */ 52 #define BIT0 0x01 53 #define BIT1 0x02 54 #define BIT2 0x04 55 #define BIT3 0x08 56 #define BIT4 0x10 57 #define BIT5 0x20 58 #define BIT6 0x40 59 #define BIT7 0x80 60 61 /* Video Memory Size */ 62 #define VIDEO_MEMORY_SIZE_16M 0x1000000 63 64 // Definition Mode Index 65 #define VIA_RES_640X480 0 66 #define VIA_RES_800X600 1 67 #define VIA_RES_1024X768 2 68 #define VIA_RES_1152X864 3 69 #define VIA_RES_1280X1024 4 70 #define VIA_RES_1600X1200 5 71 #define VIA_RES_1440X1050 6 72 #define VIA_RES_1280X768 7 73 #define VIA_RES_1280X960 8 74 #define VIA_RES_1920X1440 9 75 #define VIA_RES_848X480 10 76 #define VIA_RES_1400X1050 11 77 #define VIA_RES_720X480 12 78 #define VIA_RES_720X576 13 79 #define VIA_RES_1024X512 14 80 #define VIA_RES_856X480 15 81 #define VIA_RES_1024X576 16 82 #define VIA_RES_640X400 17 83 #define VIA_RES_1280X720 18 84 #define VIA_RES_1920X1080 19 85 #define VIA_RES_800X480 20 86 #define VIA_RES_1366X768 21 87 #define VIA_RES_INVALID 255 88 89 90 // standard VGA IO port 91 #define VIA_REGBASE 0x3C0 92 #define VIAAR 0x000 93 #define VIARMisc 0x00C 94 #define VIAWMisc 0x002 95 #define VIAStatus 0x01A 96 #define VIACR 0x014 97 #define VIASR 0x004 98 #define VIAGR 0x00E 99 100 #define StdCR 0x19 101 #define StdSR 0x04 102 #define StdGR 0x09 103 #define StdAR 0x14 104 105 #define PatchCR 11 106 107 /* Display path */ 108 #define IGA1 1 109 #define IGA2 2 110 #define IGA1_IGA2 3 111 112 /* Define Color Depth */ 113 #define MODE_8BPP 1 114 #define MODE_16BPP 2 115 #define MODE_32BPP 4 116 117 #define GR20 0x20 118 #define GR21 0x21 119 #define GR22 0x22 120 121 122 /* Sequencer Registers */ 123 #define SR01 0x01 124 #define SR10 0x10 125 #define SR12 0x12 126 #define SR15 0x15 127 #define SR16 0x16 128 #define SR17 0x17 129 #define SR18 0x18 130 #define SR1B 0x1B 131 #define SR1A 0x1A 132 #define SR1C 0x1C 133 #define SR1D 0x1D 134 #define SR1E 0x1E 135 #define SR1F 0x1F 136 #define SR20 0x20 137 #define SR21 0x21 138 #define SR22 0x22 139 #define SR2A 0x2A 140 #define SR2D 0x2D 141 #define SR2E 0x2E 142 143 #define SR30 0x30 144 #define SR39 0x39 145 #define SR3D 0x3D 146 #define SR3E 0x3E 147 #define SR3F 0x3F 148 #define SR40 0x40 149 #define SR44 0x44 150 #define SR45 0x45 151 #define SR46 0x46 152 #define SR47 0x47 153 #define SR48 0x48 154 #define SR49 0x49 155 #define SR4A 0x4A 156 #define SR4B 0x4B 157 #define SR4C 0x4C 158 #define SR52 0x52 159 #define SR5E 0x5E 160 161 162 /* CRT Controller Registers */ 163 #define CR00 0x00 164 #define CR01 0x01 165 #define CR02 0x02 166 #define CR03 0x03 167 #define CR04 0x04 168 #define CR05 0x05 169 #define CR06 0x06 170 #define CR07 0x07 171 #define CR08 0x08 172 #define CR09 0x09 173 #define CR0A 0x0A 174 #define CR0B 0x0B 175 #define CR0C 0x0C 176 #define CR0D 0x0D 177 #define CR0E 0x0E 178 #define CR0F 0x0F 179 #define CR10 0x10 180 #define CR11 0x11 181 #define CR12 0x12 182 #define CR13 0x13 183 #define CR14 0x14 184 #define CR15 0x15 185 #define CR16 0x16 186 #define CR17 0x17 187 #define CR18 0x18 188 189 /* Extend CRT Controller Registers */ 190 #define CR30 0x30 191 #define CR31 0x31 192 #define CR32 0x32 193 #define CR33 0x33 194 #define CR34 0x34 195 #define CR35 0x35 196 #define CR36 0x36 197 #define CR37 0x37 198 #define CR38 0x38 199 #define CR39 0x39 200 #define CR3A 0x3A 201 #define CR3B 0x3B 202 #define CR3C 0x3C 203 #define CR3D 0x3D 204 #define CR3E 0x3E 205 #define CR3F 0x3F 206 #define CR40 0x40 207 #define CR41 0x41 208 #define CR42 0x42 209 #define CR43 0x43 210 #define CR44 0x44 211 #define CR45 0x45 212 #define CR46 0x46 213 #define CR47 0x47 214 #define CR48 0x48 215 #define CR49 0x49 216 #define CR4A 0x4A 217 #define CR4B 0x4B 218 #define CR4C 0x4C 219 #define CR4D 0x4D 220 #define CR4E 0x4E 221 #define CR4F 0x4F 222 #define CR50 0x50 223 #define CR51 0x51 224 #define CR52 0x52 225 #define CR53 0x53 226 #define CR54 0x54 227 #define CR55 0x55 228 #define CR56 0x56 229 #define CR57 0x57 230 #define CR58 0x58 231 #define CR59 0x59 232 #define CR5A 0x5A 233 #define CR5B 0x5B 234 #define CR5C 0x5C 235 #define CR5D 0x5D 236 #define CR5E 0x5E 237 #define CR5F 0x5F 238 #define CR60 0x60 239 #define CR61 0x61 240 #define CR62 0x62 241 #define CR63 0x63 242 #define CR64 0x64 243 #define CR65 0x65 244 #define CR66 0x66 245 #define CR67 0x67 246 #define CR68 0x68 247 #define CR69 0x69 248 #define CR6A 0x6A 249 #define CR6B 0x6B 250 #define CR6C 0x6C 251 #define CR6D 0x6D 252 #define CR6E 0x6E 253 #define CR6F 0x6F 254 #define CR70 0x70 255 #define CR71 0x71 256 #define CR72 0x72 257 #define CR73 0x73 258 #define CR74 0x74 259 #define CR75 0x75 260 #define CR76 0x76 261 #define CR77 0x77 262 #define CR78 0x78 263 #define CR79 0x79 264 #define CR7A 0x7A 265 #define CR7B 0x7B 266 #define CR7C 0x7C 267 #define CR7D 0x7D 268 #define CR7E 0x7E 269 #define CR7F 0x7F 270 #define CR80 0x80 271 #define CR81 0x81 272 #define CR82 0x82 273 #define CR83 0x83 274 #define CR84 0x84 275 #define CR85 0x85 276 #define CR86 0x86 277 #define CR87 0x87 278 #define CR88 0x88 279 #define CR89 0x89 280 #define CR8A 0x8A 281 #define CR8B 0x8B 282 #define CR8C 0x8C 283 #define CR8D 0x8D 284 #define CR8E 0x8E 285 #define CR8F 0x8F 286 #define CR90 0x90 287 #define CR91 0x91 288 #define CR92 0x92 289 #define CR93 0x93 290 #define CR94 0x94 291 #define CR95 0x95 292 #define CR96 0x96 293 #define CR97 0x97 294 #define CR98 0x98 295 #define CR99 0x99 296 #define CR9A 0x9A 297 #define CR9B 0x9B 298 #define CR9C 0x9C 299 #define CR9D 0x9D 300 #define CR9E 0x9E 301 #define CR9F 0x9F 302 #define CRA0 0xA0 303 #define CRA1 0xA1 304 #define CRA2 0xA2 305 #define CRA3 0xA3 306 #define CRD2 0xD2 307 #define CRD3 0xD3 308 #define CRD4 0xD4 309 310 /* LUT Table*/ 311 #define LUT_DATA 0x09 /* DACDATA */ 312 #define LUT_INDEX_READ 0x07 /* DACRX */ 313 #define LUT_INDEX_WRITE 0x08 /* DACWX */ 314 #define DACMASK 0x06 315 316 /* Definition Device */ 317 #define DEVICE_CRT 0x01 318 #define DEVICE_TV 0x02 319 #define DEVICE_DVI 0x03 320 #define DEVICE_LCD 0x04 321 322 /* Device output interface */ 323 #define INTERFACE_NONE 0x00 324 #define INTERFACE_ANALOG_RGB 0x01 325 #define INTERFACE_DVP0 0x02 326 #define INTERFACE_DVP1 0x03 327 #define INTERFACE_DFP_HIGH 0x04 328 #define INTERFACE_DFP_LOW 0x05 329 #define INTERFACE_DFP 0x06 330 #define INTERFACE_LVDS0 0x07 331 #define INTERFACE_LVDS1 0x08 332 #define INTERFACE_LVDS0LVDS1 0x09 333 #define INTERFACE_TMDS 0x0A 334 335 /* Definition Refresh Rate */ 336 #define REFRESH_60 60 337 #define REFRESH_75 75 338 #define REFRESH_85 85 339 #define REFRESH_100 100 340 #define REFRESH_120 120 341 342 /* Definition Sync Polarity*/ 343 #define NEGATIVE 1 344 #define POSITIVE 0 345 346 //640x480@60 Sync Polarity (VESA Mode) 347 #define M640X480_R60_HSP NEGATIVE 348 #define M640X480_R60_VSP NEGATIVE 349 350 //640x480@75 Sync Polarity (VESA Mode) 351 #define M640X480_R75_HSP NEGATIVE 352 #define M640X480_R75_VSP NEGATIVE 353 354 //640x480@85 Sync Polarity (VESA Mode) 355 #define M640X480_R85_HSP NEGATIVE 356 #define M640X480_R85_VSP NEGATIVE 357 358 //640x480@100 Sync Polarity (GTF Mode) 359 #define M640X480_R100_HSP NEGATIVE 360 #define M640X480_R100_VSP POSITIVE 361 362 //640x480@120 Sync Polarity (GTF Mode) 363 #define M640X480_R120_HSP NEGATIVE 364 #define M640X480_R120_VSP POSITIVE 365 366 //720x480@60 Sync Polarity (GTF Mode) 367 #define M720X480_R60_HSP NEGATIVE 368 #define M720X480_R60_VSP POSITIVE 369 370 //720x576@60 Sync Polarity (GTF Mode) 371 #define M720X576_R60_HSP NEGATIVE 372 #define M720X576_R60_VSP POSITIVE 373 374 //800x600@60 Sync Polarity (VESA Mode) 375 #define M800X600_R60_HSP POSITIVE 376 #define M800X600_R60_VSP POSITIVE 377 378 //800x600@75 Sync Polarity (VESA Mode) 379 #define M800X600_R75_HSP POSITIVE 380 #define M800X600_R75_VSP POSITIVE 381 382 //800x600@85 Sync Polarity (VESA Mode) 383 #define M800X600_R85_HSP POSITIVE 384 #define M800X600_R85_VSP POSITIVE 385 386 //800x600@100 Sync Polarity (GTF Mode) 387 #define M800X600_R100_HSP NEGATIVE 388 #define M800X600_R100_VSP POSITIVE 389 390 //800x600@120 Sync Polarity (GTF Mode) 391 #define M800X600_R120_HSP NEGATIVE 392 #define M800X600_R120_VSP POSITIVE 393 394 //800x480@60 Sync Polarity (GTF Mode) 395 #define M800X480_R60_HSP NEGATIVE 396 #define M800X480_R60_VSP POSITIVE 397 398 //848x480@60 Sync Polarity (GTF Mode) 399 #define M848X480_R60_HSP NEGATIVE 400 #define M848X480_R60_VSP POSITIVE 401 402 //852x480@60 Sync Polarity (GTF Mode) 403 #define M852X480_R60_HSP NEGATIVE 404 #define M852X480_R60_VSP POSITIVE 405 406 //1024x512@60 Sync Polarity (GTF Mode) 407 #define M1024X512_R60_HSP NEGATIVE 408 #define M1024X512_R60_VSP POSITIVE 409 410 //1024x768@60 Sync Polarity (VESA Mode) 411 #define M1024X768_R60_HSP NEGATIVE 412 #define M1024X768_R60_VSP NEGATIVE 413 414 //1024x768@75 Sync Polarity (VESA Mode) 415 #define M1024X768_R75_HSP POSITIVE 416 #define M1024X768_R75_VSP POSITIVE 417 418 //1024x768@85 Sync Polarity (VESA Mode) 419 #define M1024X768_R85_HSP POSITIVE 420 #define M1024X768_R85_VSP POSITIVE 421 422 //1024x768@100 Sync Polarity (GTF Mode) 423 #define M1024X768_R100_HSP NEGATIVE 424 #define M1024X768_R100_VSP POSITIVE 425 426 //1152x864@75 Sync Polarity (VESA Mode) 427 #define M1152X864_R75_HSP POSITIVE 428 #define M1152X864_R75_VSP POSITIVE 429 430 //1280x720@60 Sync Polarity (GTF Mode) 431 #define M1280X720_R60_HSP NEGATIVE 432 #define M1280X720_R60_VSP POSITIVE 433 434 //1280x768@60 Sync Polarity (GTF Mode) 435 #define M1280X768_R60_HSP NEGATIVE 436 #define M1280X768_R60_VSP POSITIVE 437 438 //1280x960@60 Sync Polarity (VESA Mode) 439 #define M1280X960_R60_HSP POSITIVE 440 #define M1280X960_R60_VSP POSITIVE 441 442 //1280x1024@60 Sync Polarity (VESA Mode) 443 #define M1280X1024_R60_HSP POSITIVE 444 #define M1280X1024_R60_VSP POSITIVE 445 446 /* 1368x768@60 Sync Polarity (VESA Mode) */ 447 #define M1368X768_R60_HSP NEGATIVE 448 #define M1368X768_R60_VSP POSITIVE 449 450 //1280x1024@75 Sync Polarity (VESA Mode) 451 #define M1280X1024_R75_HSP POSITIVE 452 #define M1280X1024_R75_VSP POSITIVE 453 454 //1280x1024@85 Sync Polarity (VESA Mode) 455 #define M1280X1024_R85_HSP POSITIVE 456 #define M1280X1024_R85_VSP POSITIVE 457 458 //1440x1050@60 Sync Polarity (GTF Mode) 459 #define M1440X1050_R60_HSP NEGATIVE 460 #define M1440X1050_R60_VSP POSITIVE 461 462 //1600x1200@60 Sync Polarity (VESA Mode) 463 #define M1600X1200_R60_HSP POSITIVE 464 #define M1600X1200_R60_VSP POSITIVE 465 466 //1600x1200@75 Sync Polarity (VESA Mode) 467 #define M1600X1200_R75_HSP POSITIVE 468 #define M1600X1200_R75_VSP POSITIVE 469 470 //1920x1080@60 Sync Polarity (GTF Mode) 471 #define M1920X1080_R60_HSP NEGATIVE 472 #define M1920X1080_R60_VSP POSITIVE 473 474 //1920x1440@60 Sync Polarity (VESA Mode) 475 #define M1920X1440_R60_HSP NEGATIVE 476 #define M1920X1440_R60_VSP POSITIVE 477 478 //1920x1440@75 Sync Polarity (VESA Mode) 479 #define M1920X1440_R75_HSP NEGATIVE 480 #define M1920X1440_R75_VSP POSITIVE 481 482 /* 1400x1050@60 Sync Polarity (VESA Mode) */ 483 #define M1400X1050_R60_HSP NEGATIVE 484 #define M1400X1050_R60_VSP NEGATIVE 485 486 487 /* define PLL index: */ 488 #define CLK_25_175M 25175000 489 #define CLK_26_880M 26880000 490 #define CLK_29_581M 29581000 491 #define CLK_31_490M 31490000 492 #define CLK_31_500M 31500000 493 #define CLK_31_728M 31728000 494 #define CLK_32_668M 32688000 495 #define CLK_36_000M 36000000 496 #define CLK_40_000M 40000000 497 #define CLK_41_291M 41291000 498 #define CLK_43_163M 43163000 499 //#define CLK_46_996M 46996000 500 #define CLK_49_500M 49500000 501 #define CLK_52_406M 52406000 502 #define CLK_56_250M 56250000 503 #define CLK_65_000M 65000000 504 #define CLK_68_179M 68179000 505 #define CLK_78_750M 78750000 506 #define CLK_80_136M 80136000 507 #define CLK_83_950M 83950000 508 #define CLK_85_860M 85860000 509 #define CLK_94_500M 94500000 510 #define CLK_108_000M 108000000 511 #define CLK_125_104M 125104000 512 #define CLK_133_308M 133308000 513 #define CLK_135_000M 135000000 514 //#define CLK_148_500M 148500000 515 #define CLK_157_500M 157500000 516 #define CLK_162_000M 162000000 517 #define CLK_202_500M 202500000 518 #define CLK_234_000M 234000000 519 #define CLK_297_500M 297500000 520 #define CLK_74_481M 74481000 521 #define CLK_172_798M 172798000 522 523 524 // CLE266 PLL value 525 #define CLE266_PLL_25_175M 0x0000C763 526 #define CLE266_PLL_26_880M 0x0000440F 527 #define CLE266_PLL_29_581M 0x00008421 528 #define CLE266_PLL_31_490M 0x00004721 529 #define CLE266_PLL_31_500M 0x0000C3B5 530 #define CLE266_PLL_31_728M 0x0000471F 531 #define CLE266_PLL_32_668M 0x0000C449 532 #define CLE266_PLL_36_000M 0x0000C5E5 533 #define CLE266_PLL_40_000M 0x0000C459 534 #define CLE266_PLL_41_291M 0x00004417 535 #define CLE266_PLL_43_163M 0x0000C579 536 //#define CLE266_PLL_46_996M 0x0000C4E9 537 #define CLE266_PLL_49_500M 0x00008653 538 #define CLE266_PLL_52_406M 0x0000C475 539 #define CLE266_PLL_56_250M 0x000047B7 540 #define CLE266_PLL_65_000M 0x000086ED 541 #define CLE266_PLL_68_179M 0x00000413 542 #define CLE266_PLL_78_750M 0x00004321 543 #define CLE266_PLL_80_136M 0x0000051C 544 #define CLE266_PLL_83_950M 0x00000729 545 #define CLE266_PLL_85_860M 0x00004754 546 #define CLE266_PLL_94_500M 0x00000521 547 #define CLE266_PLL_108_000M 0x00008479 548 #define CLE266_PLL_125_104M 0x000006B5 549 #define CLE266_PLL_133_308M 0x0000465F 550 #define CLE266_PLL_135_000M 0x0000455E 551 //#define CLE266_PLL_148_500M 0x0000 552 #define CLE266_PLL_157_500M 0x000005B7 553 #define CLE266_PLL_162_000M 0x00004571 554 #define CLE266_PLL_202_500M 0x00000763 555 #define CLE266_PLL_234_000M 0x00000662 556 #define CLE266_PLL_297_500M 0x000005E6 557 #define CLE266_PLL_74_481M 0x0000051A 558 #define CLE266_PLL_172_798M 0x00004579 559 560 // K800 PLL value 561 #define K800_PLL_25_175M 0x00539001 562 #define K800_PLL_26_880M 0x001C8C80 563 #define K800_PLL_29_581M 0x00409080 564 #define K800_PLL_31_490M 0x006F9001 565 #define K800_PLL_31_500M 0x008B9002 566 #define K800_PLL_31_728M 0x00AF9003 567 #define K800_PLL_32_668M 0x00909002 568 #define K800_PLL_36_000M 0x009F9002 569 #define K800_PLL_40_000M 0x00578C02 570 #define K800_PLL_41_291M 0x00438C01 571 #define K800_PLL_43_163M 0x00778C03 572 //#define K800_PLL_46_996M 0x00000000 573 #define K800_PLL_49_500M 0x00518C01 574 #define K800_PLL_52_406M 0x00738C02 575 #define K800_PLL_56_250M 0x007C8C02 576 #define K800_PLL_65_000M 0x006B8C01 577 #define K800_PLL_68_179M 0x00708C01 578 #define K800_PLL_78_750M 0x00408801 579 #define K800_PLL_80_136M 0x00428801 580 #define K800_PLL_83_950M 0x00738803 581 #define K800_PLL_85_860M 0x00768883 582 #define K800_PLL_94_500M 0x00828803 583 #define K800_PLL_108_000M 0x00778882 584 #define K800_PLL_125_104M 0x00688801 585 #define K800_PLL_133_308M 0x005D8801 586 #define K800_PLL_135_000M 0x001A4081 587 //#define K800_PLL_148_500M 0x0000 588 #define K800_PLL_157_500M 0x00142080 589 #define K800_PLL_162_000M 0x006F8483 590 #define K800_PLL_202_500M 0x00538481 591 #define K800_PLL_234_000M 0x00608401 592 #define K800_PLL_297_500M 0x00A48402 593 #define K800_PLL_74_481M 0x007B8C81 594 #define K800_PLL_172_798M 0x00778483 595 596 /* PLL for VT3324 */ 597 #define CX700_25_175M 0x008B1003 598 #define CX700_26_719M 0x00931003 599 #define CX700_26_880M 0x00941003 600 #define CX700_29_581M 0x00A49003 601 #define CX700_31_490M 0x00AE1003 602 #define CX700_31_500M 0x00AE1003 603 #define CX700_31_728M 0x00AF1003 604 #define CX700_32_668M 0x00B51003 605 #define CX700_36_000M 0x00C81003 606 #define CX700_40_000M 0x006E0C03 607 #define CX700_41_291M 0x00710C03 608 #define CX700_43_163M 0x00770C03 609 #define CX700_49_500M 0x00880C03 610 #define CX700_52_406M 0x00730C02 611 #define CX700_56_250M 0x009B0C03 612 #define CX700_65_000M 0x006B0C01 613 #define CX700_68_179M 0x00BC0C03 614 #define CX700_74_481M 0x00CE0C03 615 #define CX700_78_750M 0x006C0803 616 #define CX700_80_136M 0x006E0803 617 #define CX700_83_375M 0x005B0882 618 #define CX700_83_950M 0x00730803 619 #define CX700_85_860M 0x00760803 620 #define CX700_94_500M 0x00820803 621 #define CX700_108_000M 0x00950803 622 #define CX700_125_104M 0x00AD0803 623 #define CX700_133_308M 0x00930802 624 #define CX700_135_000M 0x00950802 625 #define CX700_157_500M 0x006C0403 626 #define CX700_162_000M 0x006F0403 627 #define CX700_172_798M 0x00770403 628 #define CX700_202_500M 0x008C0403 629 #define CX700_234_000M 0x00600401 630 #define CX700_297_500M 0x00CE0403 631 632 /* Definition CRTC Timing Index */ 633 #define H_TOTAL_INDEX 0 634 #define H_ADDR_INDEX 1 635 #define H_BLANK_START_INDEX 2 636 #define H_BLANK_END_INDEX 3 637 #define H_SYNC_START_INDEX 4 638 #define H_SYNC_END_INDEX 5 639 #define V_TOTAL_INDEX 6 640 #define V_ADDR_INDEX 7 641 #define V_BLANK_START_INDEX 8 642 #define V_BLANK_END_INDEX 9 643 #define V_SYNC_START_INDEX 10 644 #define V_SYNC_END_INDEX 11 645 #define H_TOTAL_SHADOW_INDEX 12 646 #define H_BLANK_END_SHADOW_INDEX 13 647 #define V_TOTAL_SHADOW_INDEX 14 648 #define V_ADDR_SHADOW_INDEX 15 649 #define V_BLANK_SATRT_SHADOW_INDEX 16 650 #define V_BLANK_END_SHADOW_INDEX 17 651 #define V_SYNC_SATRT_SHADOW_INDEX 18 652 #define V_SYNC_END_SHADOW_INDEX 19 653 654 // Definition Video Mode Pixel Clock (picoseconds) 655 #define RES_640X480_60HZ_PIXCLOCK 39722 656 #define RES_640X480_75HZ_PIXCLOCK 31747 657 #define RES_640X480_85HZ_PIXCLOCK 27777 658 #define RES_640X480_100HZ_PIXCLOCK 23168 659 #define RES_640X480_120HZ_PIXCLOCK 19081 660 #define RES_720X480_60HZ_PIXCLOCK 37020 661 #define RES_720X576_60HZ_PIXCLOCK 30611 662 #define RES_800X600_60HZ_PIXCLOCK 25000 663 #define RES_800X600_75HZ_PIXCLOCK 20203 664 #define RES_800X600_85HZ_PIXCLOCK 17777 665 #define RES_800X600_100HZ_PIXCLOCK 14815 666 #define RES_800X600_120HZ_PIXCLOCK 11912 667 #define RES_800X480_60HZ_PIXCLOCK 33805 668 #define RES_848X480_60HZ_PIXCLOCK 31756 669 #define RES_856X480_60HZ_PIXCLOCK 31518 670 #define RES_1024X512_60HZ_PIXCLOCK 24218 671 #define RES_1024X768_60HZ_PIXCLOCK 15385 672 #define RES_1024X768_75HZ_PIXCLOCK 12699 673 #define RES_1024X768_85HZ_PIXCLOCK 10582 674 #define RES_1024X768_100HZ_PIXCLOCK 9091 675 #define RES_1152X864_70HZ_PIXCLOCK 10000 676 #define RES_1152X864_75HZ_PIXCLOCK 9091 677 #define RES_1280X768_60HZ_PIXCLOCK 12480 678 #define RES_1280X960_60HZ_PIXCLOCK 9259 679 #define RES_1280X1024_60HZ_PIXCLOCK 9260 680 #define RES_1280X1024_75HZ_PIXCLOCK 7408 681 #define RES_1280X768_85HZ_PIXCLOCK 6349 682 #define RES_1440X1050_60HZ_PIXCLOCK 7993 683 #define RES_1600X1200_60HZ_PIXCLOCK 6411 684 #define RES_1600X1200_75HZ_PIXCLOCK 4938 685 #define RES_1280X720_60HZ_PIXCLOCK 13426 686 #define RES_1920X1080_60HZ_PIXCLOCK 5787 687 #define RES_1400X1050_60HZ_PIXCLOCK 9260 688 #define RES_1366X768_60HZ_PIXCLOCK 11647 689 690 // LCD display method 691 #define LCD_EXPANDSION 0x00 692 #define LCD_CENTERING 0x01 693 694 // Define display timing 695 696 struct display_timing { 697 uint16_t hor_total; 698 uint16_t hor_addr; 699 uint16_t hor_blank_start; 700 uint16_t hor_blank_end; 701 uint16_t hor_sync_start; 702 uint16_t hor_sync_end; 703 uint16_t ver_total; 704 uint16_t ver_addr; 705 uint16_t ver_blank_start; 706 uint16_t ver_blank_end; 707 uint16_t ver_sync_start; 708 uint16_t ver_sync_end; 709 }; 710 711 struct crt_mode_table { 712 int refresh_rate; 713 unsigned long clk; 714 int h_sync_polarity; 715 int v_sync_polarity; 716 struct display_timing crtc; 717 }; 718 719 struct io_reg{ 720 int port; 721 uint8_t index; 722 uint8_t mask; 723 uint8_t value; 724 }; 725 726 #endif /* _DEV_PCI_UNICHROMEREG_H */ 727 728
Indexes created Sat Sep 20 22:09:52 GMT 2025