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    Searched refs:CG_FDO_CTRL2 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu7_thermal.c 121 CG_FDO_CTRL2, FDO_PWM_MODE);
124 CG_FDO_CTRL2, TMIN);
129 CG_FDO_CTRL2, TMIN, 0);
131 CG_FDO_CTRL2, FDO_PWM_MODE, mode);
145 CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode);
147 CG_FDO_CTRL2, TMIN, hwmgr->tmin);
359 CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28);
amdgpu_vega10_thermal.c 140 CG_FDO_CTRL2, FDO_PWM_MODE);
143 CG_FDO_CTRL2, TMIN);
149 CG_FDO_CTRL2, TMIN, 0));
152 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
169 CG_FDO_CTRL2, FDO_PWM_MODE,
173 CG_FDO_CTRL2, TMIN,
420 CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
amdgpu_vega20_thermal.c 101 CG_FDO_CTRL2, TMIN, 0));
104 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ci_dpm.c 945 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
947 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
952 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
954 WREG32_SMC(CG_FDO_CTRL2, tmp);
956 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
958 WREG32_SMC(CG_FDO_CTRL2, tmp);
1161 tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
1223 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
1225 WREG32_SMC(CG_FDO_CTRL2, tmp);
1227 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK
    [all...]
radeon_si_dpm.c 6017 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6019 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6024 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6026 WREG32(CG_FDO_CTRL2, tmp);
6028 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6030 WREG32(CG_FDO_CTRL2, tmp);
6221 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6283 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6285 WREG32(CG_FDO_CTRL2, tmp);
6287 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK
    [all...]
cikd.h 222 #define CG_FDO_CTRL2 0xC030006C
sid.h 219 #define CG_FDO_CTRL2 0x75C
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si_dpm.c 6454 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6456 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6461 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6463 WREG32(CG_FDO_CTRL2, tmp);
6465 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6467 WREG32(CG_FDO_CTRL2, tmp);
6655 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6717 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6719 WREG32(CG_FDO_CTRL2, tmp);
6721 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK
    [all...]
sid.h 221 #define CG_FDO_CTRL2 0x1d7
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_smu_v11_0.c 1424 CG_FDO_CTRL2, TMIN, 0));
1427 CG_FDO_CTRL2, FDO_PWM_MODE, mode));

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