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    Searched refs:CG_THERMAL_CTRL (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
rv6xxd.h 146 #define CG_THERMAL_CTRL 0x7f0
rv770d.h 410 #define CG_THERMAL_CTRL 0x72C
radeon_rv770_dpm.c 1846 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
1890 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
cikd.h 183 #define CG_THERMAL_CTRL 0xC0300004
radeon_r600_dpm.c 761 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
sid.h 179 #define CG_THERMAL_CTRL 0x700
radeon_ci_dpm.c 898 tmp = RREG32_SMC(CG_THERMAL_CTRL);
901 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1414 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1417 WREG32_SMC(CG_THERMAL_CTRL, tmp);
evergreend.h 879 #define CG_THERMAL_CTRL 0x72c
r600d.h 300 #define CG_THERMAL_CTRL 0x7F0
radeon_rv6xx_dpm.c 1385 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
radeon_si_dpm.c 3310 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
6003 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
radeon_evergreen.c 1463 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu7_thermal.c 339 CG_THERMAL_CTRL, DIG_THERM_DPM,
amdgpu_smu7_hwmgr.c 108 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
1282 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h 181 #define CG_THERMAL_CTRL 0x1c0
amdgpu_si_dpm.c 3770 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
6440 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);

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