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    Searched refs:CH_SR (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/arch/vax/boot/boot/
consio.c 276 #define CH_SR 1
284 while ((vxtregs[CH_SR] & SR_TX_RDY) == 0)
292 while ((vxtregs[CH_SR] & SR_RX_RDY) == 0)
300 if ((vxtregs[CH_SR] & SR_RX_RDY) == 0)
  /src/sys/arch/sgimips/dev/
scnreg.h 43 #define CH_SR SCN_REG(1) /* ro status register */
scn.c 1399 sr = (SC)->sc_chbase[CH_SR]; \
1414 sr = sc->sc_chbase[CH_SR];
1420 sr = sc->sc_chbase[CH_SR];
1827 while (sc->sc_chbase[CH_SR] & SR_TX_RDY) {
1920 while ((ch_base[CH_SR] & SR_RX_RDY) == 0)
1950 while ((ch_base[CH_SR] & SR_TX_RDY) == 0)
1953 while ((ch_base[CH_SR] & SR_TX_RDY) == 0)
  /src/sys/arch/vax/uba/
qvareg.h 45 #define CH_SR(x) SCN_REG(1 + 8*(x)) /* ro status register */
qvaux.c 287 sc->sc_qr.qr_ch_regs[0].qr_sr = CH_SR(0);
292 sc->sc_qr.qr_ch_regs[1].qr_sr = CH_SR(1);

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