1 /* $NetBSD: scnreg.h,v 1.1 2009/02/10 06:04:56 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1997 Philip L. Budne. 5 * Copyright (c) 1993 Philip A. Nelson. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Philip A. Nelson. 19 * 4. The name of Philip A. Nelson may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY PHILIP NELSON ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL PHILIP NELSON BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * scnreg.h: definitions for 2681/2692/68681 duart 35 */ 36 37 /* 38 * register offsets 39 */ 40 41 /* per-channel regs (channel B's at SCN_REG(8-11)) */ 42 #define CH_MR SCN_REG(0) /* rw mode register */ 43 #define CH_SR SCN_REG(1) /* ro status register */ 44 #define CH_CSR SCN_REG(1) /* wo clock select reg */ 45 #define CH_CR SCN_REG(2) /* wo command reg */ 46 #define CH_DAT SCN_REG(3) /* rw data reg */ 47 48 /* duart-wide regs */ 49 #define DU_IPCR SCN_REG(4) /* ro input port change reg */ 50 #define DU_ACR SCN_REG(4) /* wo aux control reg */ 51 #define DU_ISR SCN_REG(5) /* ro interrupt stat reg */ 52 #define DU_IMR SCN_REG(5) /* wo interrupt mask reg */ 53 #define DU_CTUR SCN_REG(6) /* rw counter timer upper reg */ 54 #define DU_CTLR SCN_REG(7) /* rw counter timer lower reg */ 55 /* SCN_REG(8-11) channel b (see above) */ 56 /* SCN_REG(12): reserved */ 57 #define DU_IP SCN_REG(13) /* ro input port */ 58 #define DU_OPCR SCN_REG(13) /* wo output port cfg reg */ 59 #define DU_CSTRT SCN_REG(14) /* ro start C/T cmd */ 60 #define DU_OPSET SCN_REG(14) /* wo output port set */ 61 #define DU_CSTOP SCN_REG(15) /* ro stop C/T cmd */ 62 #define DU_OPCLR SCN_REG(15) /* wo output port reset */ 63 64 /* 65 * Data Values 66 */ 67 68 /* 69 * MR (mode register) -- per channel 70 */ 71 72 /* MR0 (scn26c92 only) need to use CR_CMD_MR0 before access */ 73 #define MR0_MODE 0x07 /* extended baud rate mode (MR0A only) */ 74 #define MR0_TXINT 0x30 /* Tx int threshold */ 75 #define MR0_RXINT 0x40 /* Rx int threshold (along with MR1_FFULL) */ 76 #define MR0_RXWD 0x80 /* Rx watchdog (8 byte-times after last rx) */ 77 78 #define MR0_MODE_0 0x00 /* Normal mode */ 79 #define MR0_MODE_1 0x01 /* Extended mode 1 */ 80 #define MR0_MODE_2 0x04 /* Extended mode 2 */ 81 82 #define MR0_TXINT_EMPTY 0x00 /* TxInt when 8 FIFO bytes empty (default) */ 83 #define MR0_TXINT_4 0x10 /* TxInt when 4 or more FIFO bytes empty */ 84 #define MR0_TXINT_6 0x20 /* TxInt when 6 or more FIFO bytes empty */ 85 #define MR0_TXINT_TXRDY 0x30 /* TxInt when 1 or more FIFO bytes empty */ 86 87 /* MR1 (need to use CR_CMD_MR1 before each access) */ 88 #define MR1_CS5 0x00 89 #define MR1_CS6 0x01 90 #define MR1_CS7 0x02 91 #define MR1_CS8 0x03 92 93 #define MR1_PEVEN 0x00 94 #define MR1_PODD 0x04 95 #define MR1_PNONE 0x10 96 97 #define MR1_RXBLK 0x20 /* "block" error mode */ 98 #define MR1_FFULL 0x40 /* wait until FIFO full for rxint (cf MR0) */ 99 #define MR1_RXRTS 0x80 /* auto RTS input flow ctrl */ 100 101 /* MR2 (any access to MR after MR1) */ 102 #define MR2_STOP 0x0f /* mask for stop bits */ 103 #define MR2_STOP1 0x07 104 #define MR2_STOP2 0x0f 105 106 #define MR2_TXCTS 0x10 /* transmitter follows CTS */ 107 #define MR2_TXRTS 0x20 /* RTS follows transmitter */ 108 #define MR2_MODE 0xc0 /* mode mask */ 109 110 /* 111 * IP (input port) 112 */ 113 #define IP_IP0 0x01 114 #define IP_IP1 0x02 115 #define IP_IP2 0x04 116 #define IP_IP3 0x08 117 #define IP_IP4 0x10 118 #define IP_IP5 0x20 119 #define IP_IP6 0x40 120 /* D7 is always 1 */ 121 122 /* 123 * ACR (Aux Control Register) 124 */ 125 126 #define ACR_DELTA_IP0 0x01 /* enable IP0 delta interrupt */ 127 #define ACR_DELTA_IP1 0x02 /* enable IP1 delta interrupt */ 128 #define ACR_DELTA_IP2 0x04 /* enable IP2 delta interrupt */ 129 #define ACR_DELTA_IP3 0x08 /* enable IP3 delta interrupt */ 130 #define ACR_CT 0x70 /* counter/timer mode (ACT_CT_xxx) */ 131 #define ACR_BRG 0x80 /* baud rate generator speed set */ 132 133 /* counter/timer mode */ 134 #define ACR_CT_CEXT 0x00 /* counter: external (IP2) */ 135 #define ACR_CT_CTXA 0x10 /* counter: TxCA x 1 */ 136 #define ACR_CT_CTXB 0x20 /* counter: TxCB x 1 */ 137 #define ACR_CT_CCLK 0x30 /* counter: X1/CLK div 16 */ 138 #define ACR_CT_TEXT1 0x40 /* timer: external (IP2) */ 139 #define ACR_CT_TEXT16 0x50 /* timer: external (IP2) div 16 */ 140 #define ACR_CT_TCLK1 0x60 /* timer: X1/CLK */ 141 #define ACR_CT_TCLK16 0x70 /* timer: X1/CLK div 16 */ 142 143 /* 144 * IPCR (Input Port Change Register) -- per channel 145 */ 146 #define IPCR_IP0 0x01 147 #define IPCR_IP1 0x02 148 #define IPCR_IP2 0x04 149 #define IPCR_IP3 0x08 150 #define IPCR_DELTA_IP0 0x10 151 #define IPCR_DELTA_IP1 0x20 152 #define IPCR_DELTA_IP2 0x40 153 #define IPCR_DELTA_IP3 0x80 154 155 /* 156 * output port config register 157 * if bit(s) clear OP line follows OP register OPn bit 158 */ 159 160 #define OPCR_OP7_TXRDYB 0x80 /* OP7: TxRDYB */ 161 #define OPCR_OP6_TXRDYA 0x40 /* OP6: TxRDYA */ 162 #define OPCR_OP5_RXRDYB 0x20 /* OP5: ch B RxRDY/FFULL */ 163 #define OPCR_OP4_RXRDYA 0x10 /* OP4: ch A RxRDY/FFULL */ 164 165 #define OPCR_OP3 0xC0 /* OP3: mask */ 166 #define OPCR_OP2 0x03 /* OP2: mask */ 167 168 /* 169 * output port 170 */ 171 #define OP_OP0 0x01 172 #define OP_OP1 0x02 173 #define OP_OP2 0x04 174 #define OP_OP3 0x08 175 #define OP_OP4 0x10 176 #define OP_OP5 0x20 177 #define OP_OP6 0x40 178 #define OP_OP7 0x80 179 180 /* 181 * CR (command register) -- per channel 182 */ 183 184 /* bits (may be or'ed together, with a command) */ 185 #define CR_ENA_RX 0x01 186 #define CR_DIS_RX 0x02 187 #define CR_ENA_TX 0x04 188 #define CR_DIS_TX 0x08 189 190 /* commands */ 191 #define CR_CMD_NOP 0x00 192 #define CR_CMD_MR1 0x10 193 #define CR_CMD_RESET_RX 0x20 194 #define CR_CMD_RESET_TX 0x30 195 #define CR_CMD_RESET_ERR 0x40 196 #define CR_CMD_RESET_BRK 0x50 197 #define CR_CMD_START_BRK 0x60 198 #define CR_CMD_STOP_BRK 0x70 199 200 /* 2692-only commands */ 201 #define CR_CMD_RTS_ON 0x80 /* raise RTS */ 202 #define CR_CMD_RTS_OFF 0x90 /* lower RTS */ 203 #define CR_CMD_TIM_ON 0xa0 /* enable timeout mode */ 204 #define CR_CMD_TIM_OFF 0xc0 /* reset timeout mode */ 205 #define CR_CMD_PDN_ON 0xe0 /* power down mode on */ 206 #define CR_CMD_PDN_RUN 0xf0 /* power down mode off (normal run) */ 207 208 /* 26C92-only commands */ 209 #define CR_CMD_MR0 0xb0 /* MR0 select */ 210 211 212 /* 213 * SR (status register) -- per channel 214 */ 215 #define SR_RX_RDY 0x01 216 #define SR_RX_FFULL 0x02 /* rx fifo full */ 217 #define SR_TX_RDY 0x04 /* tx room for more */ 218 #define SR_TX_EMPTY 0x08 /* tx dry */ 219 220 #define SR_OVERRUN 0x10 221 222 /* bits cleared by reset error (see MR1 error mode bit) */ 223 #define SR_PARITY 0x20 /* received parity error */ 224 #define SR_FRAME 0x40 /* received framing error */ 225 #define SR_BREAK 0x80 /* received break */ 226 227 /* 228 * Interrupt Mask Register (IMR) and ISR (Interrupt Status Register) 229 */ 230 #define INT_TXA 0x01 /* Tx Ready A */ 231 #define INT_RXA 0x02 /* Rx Ready/FIFO Full A */ 232 #define INT_BRKA 0x04 /* Delta Break A */ 233 #define INT_CTR 0x08 /* counter ready */ 234 #define INT_TXB 0x10 /* Tx Ready B */ 235 #define INT_RXB 0x20 /* Rx Ready/FIFO Full B */ 236 #define INT_BRKB 0x40 /* Delta Break B */ 237 #define INT_IP 0x80 /* input port change */ 238
Indexes created Sat Sep 20 22:09:52 GMT 2025