Searched refs:CLK_MM_DISP_SPLIT0 (Results 1 - 5 of 5) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dmt8173-clk.h277 #define CLK_MM_DISP_SPLIT0 28 macro
H A Dmediatek,mt6795-clk.h249 #define CLK_MM_DISP_SPLIT0 28 macro
H A Dmt2712-clk.h331 #define CLK_MM_DISP_SPLIT0 28 macro
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
H A Dmt6795.dtsi849 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
H A Dmt8173.dtsi1191 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;

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