1 /* $NetBSD: mt2712-clk.h,v 1.1.1.4 2020/01/03 14:33:04 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2017 MediaTek Inc. 6 * Author: Weiyi Lu <weiyi.lu (at) mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_MT2712_H 10 #define _DT_BINDINGS_CLK_MT2712_H 11 12 /* APMIXEDSYS */ 13 14 #define CLK_APMIXED_MAINPLL 0 15 #define CLK_APMIXED_UNIVPLL 1 16 #define CLK_APMIXED_VCODECPLL 2 17 #define CLK_APMIXED_VENCPLL 3 18 #define CLK_APMIXED_APLL1 4 19 #define CLK_APMIXED_APLL2 5 20 #define CLK_APMIXED_LVDSPLL 6 21 #define CLK_APMIXED_LVDSPLL2 7 22 #define CLK_APMIXED_MSDCPLL 8 23 #define CLK_APMIXED_MSDCPLL2 9 24 #define CLK_APMIXED_TVDPLL 10 25 #define CLK_APMIXED_MMPLL 11 26 #define CLK_APMIXED_ARMCA35PLL 12 27 #define CLK_APMIXED_ARMCA72PLL 13 28 #define CLK_APMIXED_ETHERPLL 14 29 #define CLK_APMIXED_NR_CLK 15 30 31 /* TOPCKGEN */ 32 33 #define CLK_TOP_ARMCA35PLL 0 34 #define CLK_TOP_ARMCA35PLL_600M 1 35 #define CLK_TOP_ARMCA35PLL_400M 2 36 #define CLK_TOP_ARMCA72PLL 3 37 #define CLK_TOP_SYSPLL 4 38 #define CLK_TOP_SYSPLL_D2 5 39 #define CLK_TOP_SYSPLL1_D2 6 40 #define CLK_TOP_SYSPLL1_D4 7 41 #define CLK_TOP_SYSPLL1_D8 8 42 #define CLK_TOP_SYSPLL1_D16 9 43 #define CLK_TOP_SYSPLL_D3 10 44 #define CLK_TOP_SYSPLL2_D2 11 45 #define CLK_TOP_SYSPLL2_D4 12 46 #define CLK_TOP_SYSPLL_D5 13 47 #define CLK_TOP_SYSPLL3_D2 14 48 #define CLK_TOP_SYSPLL3_D4 15 49 #define CLK_TOP_SYSPLL_D7 16 50 #define CLK_TOP_SYSPLL4_D2 17 51 #define CLK_TOP_SYSPLL4_D4 18 52 #define CLK_TOP_UNIVPLL 19 53 #define CLK_TOP_UNIVPLL_D7 20 54 #define CLK_TOP_UNIVPLL_D26 21 55 #define CLK_TOP_UNIVPLL_D52 22 56 #define CLK_TOP_UNIVPLL_D104 23 57 #define CLK_TOP_UNIVPLL_D208 24 58 #define CLK_TOP_UNIVPLL_D2 25 59 #define CLK_TOP_UNIVPLL1_D2 26 60 #define CLK_TOP_UNIVPLL1_D4 27 61 #define CLK_TOP_UNIVPLL1_D8 28 62 #define CLK_TOP_UNIVPLL_D3 29 63 #define CLK_TOP_UNIVPLL2_D2 30 64 #define CLK_TOP_UNIVPLL2_D4 31 65 #define CLK_TOP_UNIVPLL2_D8 32 66 #define CLK_TOP_UNIVPLL_D5 33 67 #define CLK_TOP_UNIVPLL3_D2 34 68 #define CLK_TOP_UNIVPLL3_D4 35 69 #define CLK_TOP_UNIVPLL3_D8 36 70 #define CLK_TOP_F_MP0_PLL1 37 71 #define CLK_TOP_F_MP0_PLL2 38 72 #define CLK_TOP_F_BIG_PLL1 39 73 #define CLK_TOP_F_BIG_PLL2 40 74 #define CLK_TOP_F_BUS_PLL1 41 75 #define CLK_TOP_F_BUS_PLL2 42 76 #define CLK_TOP_APLL1 43 77 #define CLK_TOP_APLL1_D2 44 78 #define CLK_TOP_APLL1_D4 45 79 #define CLK_TOP_APLL1_D8 46 80 #define CLK_TOP_APLL1_D16 47 81 #define CLK_TOP_APLL2 48 82 #define CLK_TOP_APLL2_D2 49 83 #define CLK_TOP_APLL2_D4 50 84 #define CLK_TOP_APLL2_D8 51 85 #define CLK_TOP_APLL2_D16 52 86 #define CLK_TOP_LVDSPLL 53 87 #define CLK_TOP_LVDSPLL_D2 54 88 #define CLK_TOP_LVDSPLL_D4 55 89 #define CLK_TOP_LVDSPLL_D8 56 90 #define CLK_TOP_LVDSPLL2 57 91 #define CLK_TOP_LVDSPLL2_D2 58 92 #define CLK_TOP_LVDSPLL2_D4 59 93 #define CLK_TOP_LVDSPLL2_D8 60 94 #define CLK_TOP_ETHERPLL_125M 61 95 #define CLK_TOP_ETHERPLL_50M 62 96 #define CLK_TOP_CVBS 63 97 #define CLK_TOP_CVBS_D2 64 98 #define CLK_TOP_SYS_26M 65 99 #define CLK_TOP_MMPLL 66 100 #define CLK_TOP_MMPLL_D2 67 101 #define CLK_TOP_VENCPLL 68 102 #define CLK_TOP_VENCPLL_D2 69 103 #define CLK_TOP_VCODECPLL 70 104 #define CLK_TOP_VCODECPLL_D2 71 105 #define CLK_TOP_TVDPLL 72 106 #define CLK_TOP_TVDPLL_D2 73 107 #define CLK_TOP_TVDPLL_D4 74 108 #define CLK_TOP_TVDPLL_D8 75 109 #define CLK_TOP_TVDPLL_429M 76 110 #define CLK_TOP_TVDPLL_429M_D2 77 111 #define CLK_TOP_TVDPLL_429M_D4 78 112 #define CLK_TOP_MSDCPLL 79 113 #define CLK_TOP_MSDCPLL_D2 80 114 #define CLK_TOP_MSDCPLL_D4 81 115 #define CLK_TOP_MSDCPLL2 82 116 #define CLK_TOP_MSDCPLL2_D2 83 117 #define CLK_TOP_MSDCPLL2_D4 84 118 #define CLK_TOP_CLK26M_D2 85 119 #define CLK_TOP_D2A_ULCLK_6P5M 86 120 #define CLK_TOP_VPLL3_DPIX 87 121 #define CLK_TOP_VPLL_DPIX 88 122 #define CLK_TOP_LTEPLL_FS26M 89 123 #define CLK_TOP_DMPLL 90 124 #define CLK_TOP_DSI0_LNTC 91 125 #define CLK_TOP_DSI1_LNTC 92 126 #define CLK_TOP_LVDSTX3_CLKDIG_CTS 93 127 #define CLK_TOP_LVDSTX_CLKDIG_CTS 94 128 #define CLK_TOP_CLKRTC_EXT 95 129 #define CLK_TOP_CLKRTC_INT 96 130 #define CLK_TOP_CSI0 97 131 #define CLK_TOP_CVBSPLL 98 132 #define CLK_TOP_AXI_SEL 99 133 #define CLK_TOP_MEM_SEL 100 134 #define CLK_TOP_MM_SEL 101 135 #define CLK_TOP_PWM_SEL 102 136 #define CLK_TOP_VDEC_SEL 103 137 #define CLK_TOP_VENC_SEL 104 138 #define CLK_TOP_MFG_SEL 105 139 #define CLK_TOP_CAMTG_SEL 106 140 #define CLK_TOP_UART_SEL 107 141 #define CLK_TOP_SPI_SEL 108 142 #define CLK_TOP_USB20_SEL 109 143 #define CLK_TOP_USB30_SEL 110 144 #define CLK_TOP_MSDC50_0_HCLK_SEL 111 145 #define CLK_TOP_MSDC50_0_SEL 112 146 #define CLK_TOP_MSDC30_1_SEL 113 147 #define CLK_TOP_MSDC30_2_SEL 114 148 #define CLK_TOP_MSDC30_3_SEL 115 149 #define CLK_TOP_AUDIO_SEL 116 150 #define CLK_TOP_AUD_INTBUS_SEL 117 151 #define CLK_TOP_PMICSPI_SEL 118 152 #define CLK_TOP_DPILVDS1_SEL 119 153 #define CLK_TOP_ATB_SEL 120 154 #define CLK_TOP_NR_SEL 121 155 #define CLK_TOP_NFI2X_SEL 122 156 #define CLK_TOP_IRDA_SEL 123 157 #define CLK_TOP_CCI400_SEL 124 158 #define CLK_TOP_AUD_1_SEL 125 159 #define CLK_TOP_AUD_2_SEL 126 160 #define CLK_TOP_MEM_MFG_IN_AS_SEL 127 161 #define CLK_TOP_AXI_MFG_IN_AS_SEL 128 162 #define CLK_TOP_SCAM_SEL 129 163 #define CLK_TOP_NFIECC_SEL 130 164 #define CLK_TOP_PE2_MAC_P0_SEL 131 165 #define CLK_TOP_PE2_MAC_P1_SEL 132 166 #define CLK_TOP_DPILVDS_SEL 133 167 #define CLK_TOP_MSDC50_3_HCLK_SEL 134 168 #define CLK_TOP_HDCP_SEL 135 169 #define CLK_TOP_HDCP_24M_SEL 136 170 #define CLK_TOP_RTC_SEL 137 171 #define CLK_TOP_SPINOR_SEL 138 172 #define CLK_TOP_APLL_SEL 139 173 #define CLK_TOP_APLL2_SEL 140 174 #define CLK_TOP_A1SYS_HP_SEL 141 175 #define CLK_TOP_A2SYS_HP_SEL 142 176 #define CLK_TOP_ASM_L_SEL 143 177 #define CLK_TOP_ASM_M_SEL 144 178 #define CLK_TOP_ASM_H_SEL 145 179 #define CLK_TOP_I2SO1_SEL 146 180 #define CLK_TOP_I2SO2_SEL 147 181 #define CLK_TOP_I2SO3_SEL 148 182 #define CLK_TOP_TDMO0_SEL 149 183 #define CLK_TOP_TDMO1_SEL 150 184 #define CLK_TOP_I2SI1_SEL 151 185 #define CLK_TOP_I2SI2_SEL 152 186 #define CLK_TOP_I2SI3_SEL 153 187 #define CLK_TOP_ETHER_125M_SEL 154 188 #define CLK_TOP_ETHER_50M_SEL 155 189 #define CLK_TOP_JPGDEC_SEL 156 190 #define CLK_TOP_SPISLV_SEL 157 191 #define CLK_TOP_ETHER_50M_RMII_SEL 158 192 #define CLK_TOP_CAM2TG_SEL 159 193 #define CLK_TOP_DI_SEL 160 194 #define CLK_TOP_TVD_SEL 161 195 #define CLK_TOP_I2C_SEL 162 196 #define CLK_TOP_PWM_INFRA_SEL 163 197 #define CLK_TOP_MSDC0P_AES_SEL 164 198 #define CLK_TOP_CMSYS_SEL 165 199 #define CLK_TOP_GCPU_SEL 166 200 #define CLK_TOP_AUD_APLL1_SEL 167 201 #define CLK_TOP_AUD_APLL2_SEL 168 202 #define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169 203 #define CLK_TOP_APLL_DIV0 170 204 #define CLK_TOP_APLL_DIV1 171 205 #define CLK_TOP_APLL_DIV2 172 206 #define CLK_TOP_APLL_DIV3 173 207 #define CLK_TOP_APLL_DIV4 174 208 #define CLK_TOP_APLL_DIV5 175 209 #define CLK_TOP_APLL_DIV6 176 210 #define CLK_TOP_APLL_DIV7 177 211 #define CLK_TOP_APLL_DIV_PDN0 178 212 #define CLK_TOP_APLL_DIV_PDN1 179 213 #define CLK_TOP_APLL_DIV_PDN2 180 214 #define CLK_TOP_APLL_DIV_PDN3 181 215 #define CLK_TOP_APLL_DIV_PDN4 182 216 #define CLK_TOP_APLL_DIV_PDN5 183 217 #define CLK_TOP_APLL_DIV_PDN6 184 218 #define CLK_TOP_APLL_DIV_PDN7 185 219 #define CLK_TOP_APLL1_D3 186 220 #define CLK_TOP_APLL1_REF_SEL 187 221 #define CLK_TOP_APLL2_REF_SEL 188 222 #define CLK_TOP_NFI2X_EN 189 223 #define CLK_TOP_NFIECC_EN 190 224 #define CLK_TOP_NFI1X_CK_EN 191 225 #define CLK_TOP_APLL2_D3 192 226 #define CLK_TOP_NR_CLK 193 227 228 /* INFRACFG */ 229 230 #define CLK_INFRA_DBGCLK 0 231 #define CLK_INFRA_GCE 1 232 #define CLK_INFRA_M4U 2 233 #define CLK_INFRA_KP 3 234 #define CLK_INFRA_AO_SPI0 4 235 #define CLK_INFRA_AO_SPI1 5 236 #define CLK_INFRA_AO_UART5 6 237 #define CLK_INFRA_NR_CLK 7 238 239 /* PERICFG */ 240 241 #define CLK_PERI_NFI 0 242 #define CLK_PERI_THERM 1 243 #define CLK_PERI_PWM0 2 244 #define CLK_PERI_PWM1 3 245 #define CLK_PERI_PWM2 4 246 #define CLK_PERI_PWM3 5 247 #define CLK_PERI_PWM4 6 248 #define CLK_PERI_PWM5 7 249 #define CLK_PERI_PWM6 8 250 #define CLK_PERI_PWM7 9 251 #define CLK_PERI_PWM 10 252 #define CLK_PERI_AP_DMA 11 253 #define CLK_PERI_MSDC30_0 12 254 #define CLK_PERI_MSDC30_1 13 255 #define CLK_PERI_MSDC30_2 14 256 #define CLK_PERI_MSDC30_3 15 257 #define CLK_PERI_UART0 16 258 #define CLK_PERI_UART1 17 259 #define CLK_PERI_UART2 18 260 #define CLK_PERI_UART3 19 261 #define CLK_PERI_I2C0 20 262 #define CLK_PERI_I2C1 21 263 #define CLK_PERI_I2C2 22 264 #define CLK_PERI_I2C3 23 265 #define CLK_PERI_I2C4 24 266 #define CLK_PERI_AUXADC 25 267 #define CLK_PERI_SPI0 26 268 #define CLK_PERI_SPI 27 269 #define CLK_PERI_I2C5 28 270 #define CLK_PERI_SPI2 29 271 #define CLK_PERI_SPI3 30 272 #define CLK_PERI_SPI5 31 273 #define CLK_PERI_UART4 32 274 #define CLK_PERI_SFLASH 33 275 #define CLK_PERI_GMAC 34 276 #define CLK_PERI_PCIE0 35 277 #define CLK_PERI_PCIE1 36 278 #define CLK_PERI_GMAC_PCLK 37 279 #define CLK_PERI_MSDC50_0_EN 38 280 #define CLK_PERI_MSDC30_1_EN 39 281 #define CLK_PERI_MSDC30_2_EN 40 282 #define CLK_PERI_MSDC30_3_EN 41 283 #define CLK_PERI_MSDC50_0_HCLK_EN 42 284 #define CLK_PERI_MSDC50_3_HCLK_EN 43 285 #define CLK_PERI_MSDC30_0_QTR_EN 44 286 #define CLK_PERI_MSDC30_3_QTR_EN 45 287 #define CLK_PERI_NR_CLK 46 288 289 /* MCUCFG */ 290 291 #define CLK_MCU_MP0_SEL 0 292 #define CLK_MCU_MP2_SEL 1 293 #define CLK_MCU_BUS_SEL 2 294 #define CLK_MCU_NR_CLK 3 295 296 /* MFGCFG */ 297 298 #define CLK_MFG_BG3D 0 299 #define CLK_MFG_NR_CLK 1 300 301 /* MMSYS */ 302 303 #define CLK_MM_SMI_COMMON 0 304 #define CLK_MM_SMI_LARB0 1 305 #define CLK_MM_CAM_MDP 2 306 #define CLK_MM_MDP_RDMA0 3 307 #define CLK_MM_MDP_RDMA1 4 308 #define CLK_MM_MDP_RSZ0 5 309 #define CLK_MM_MDP_RSZ1 6 310 #define CLK_MM_MDP_RSZ2 7 311 #define CLK_MM_MDP_TDSHP0 8 312 #define CLK_MM_MDP_TDSHP1 9 313 #define CLK_MM_MDP_CROP 10 314 #define CLK_MM_MDP_WDMA 11 315 #define CLK_MM_MDP_WROT0 12 316 #define CLK_MM_MDP_WROT1 13 317 #define CLK_MM_FAKE_ENG 14 318 #define CLK_MM_MUTEX_32K 15 319 #define CLK_MM_DISP_OVL0 16 320 #define CLK_MM_DISP_OVL1 17 321 #define CLK_MM_DISP_RDMA0 18 322 #define CLK_MM_DISP_RDMA1 19 323 #define CLK_MM_DISP_RDMA2 20 324 #define CLK_MM_DISP_WDMA0 21 325 #define CLK_MM_DISP_WDMA1 22 326 #define CLK_MM_DISP_COLOR0 23 327 #define CLK_MM_DISP_COLOR1 24 328 #define CLK_MM_DISP_AAL 25 329 #define CLK_MM_DISP_GAMMA 26 330 #define CLK_MM_DISP_UFOE 27 331 #define CLK_MM_DISP_SPLIT0 28 332 #define CLK_MM_DISP_OD 29 333 #define CLK_MM_DISP_PWM0_MM 30 334 #define CLK_MM_DISP_PWM0_26M 31 335 #define CLK_MM_DISP_PWM1_MM 32 336 #define CLK_MM_DISP_PWM1_26M 33 337 #define CLK_MM_DSI0_ENGINE 34 338 #define CLK_MM_DSI0_DIGITAL 35 339 #define CLK_MM_DSI1_ENGINE 36 340 #define CLK_MM_DSI1_DIGITAL 37 341 #define CLK_MM_DPI_PIXEL 38 342 #define CLK_MM_DPI_ENGINE 39 343 #define CLK_MM_DPI1_PIXEL 40 344 #define CLK_MM_DPI1_ENGINE 41 345 #define CLK_MM_LVDS_PIXEL 42 346 #define CLK_MM_LVDS_CTS 43 347 #define CLK_MM_SMI_LARB4 44 348 #define CLK_MM_SMI_COMMON1 45 349 #define CLK_MM_SMI_LARB5 46 350 #define CLK_MM_MDP_RDMA2 47 351 #define CLK_MM_MDP_TDSHP2 48 352 #define CLK_MM_DISP_OVL2 49 353 #define CLK_MM_DISP_WDMA2 50 354 #define CLK_MM_DISP_COLOR2 51 355 #define CLK_MM_DISP_AAL1 52 356 #define CLK_MM_DISP_OD1 53 357 #define CLK_MM_LVDS1_PIXEL 54 358 #define CLK_MM_LVDS1_CTS 55 359 #define CLK_MM_SMI_LARB7 56 360 #define CLK_MM_MDP_RDMA3 57 361 #define CLK_MM_MDP_WROT2 58 362 #define CLK_MM_DSI2 59 363 #define CLK_MM_DSI2_DIGITAL 60 364 #define CLK_MM_DSI3 61 365 #define CLK_MM_DSI3_DIGITAL 62 366 #define CLK_MM_NR_CLK 63 367 368 /* IMGSYS */ 369 370 #define CLK_IMG_SMI_LARB2 0 371 #define CLK_IMG_SENINF_SCAM_EN 1 372 #define CLK_IMG_SENINF_CAM_EN 2 373 #define CLK_IMG_CAM_SV_EN 3 374 #define CLK_IMG_CAM_SV1_EN 4 375 #define CLK_IMG_CAM_SV2_EN 5 376 #define CLK_IMG_NR_CLK 6 377 378 /* BDPSYS */ 379 380 #define CLK_BDP_BRIDGE_B 0 381 #define CLK_BDP_BRIDGE_DRAM 1 382 #define CLK_BDP_LARB_DRAM 2 383 #define CLK_BDP_WR_CHANNEL_VDI_PXL 3 384 #define CLK_BDP_WR_CHANNEL_VDI_DRAM 4 385 #define CLK_BDP_WR_CHANNEL_VDI_B 5 386 #define CLK_BDP_MT_B 6 387 #define CLK_BDP_DISPFMT_27M 7 388 #define CLK_BDP_DISPFMT_27M_VDOUT 8 389 #define CLK_BDP_DISPFMT_27_74_74 9 390 #define CLK_BDP_DISPFMT_2FS 10 391 #define CLK_BDP_DISPFMT_2FS_2FS74_148 11 392 #define CLK_BDP_DISPFMT_B 12 393 #define CLK_BDP_VDO_DRAM 13 394 #define CLK_BDP_VDO_2FS 14 395 #define CLK_BDP_VDO_B 15 396 #define CLK_BDP_WR_CHANNEL_DI_PXL 16 397 #define CLK_BDP_WR_CHANNEL_DI_DRAM 17 398 #define CLK_BDP_WR_CHANNEL_DI_B 18 399 #define CLK_BDP_NR_AGENT 19 400 #define CLK_BDP_NR_DRAM 20 401 #define CLK_BDP_NR_B 21 402 #define CLK_BDP_BRIDGE_RT_B 22 403 #define CLK_BDP_BRIDGE_RT_DRAM 23 404 #define CLK_BDP_LARB_RT_DRAM 24 405 #define CLK_BDP_TVD_TDC 25 406 #define CLK_BDP_TVD_54 26 407 #define CLK_BDP_TVD_CBUS 27 408 #define CLK_BDP_NR_CLK 28 409 410 /* VDECSYS */ 411 412 #define CLK_VDEC_CKEN 0 413 #define CLK_VDEC_LARB1_CKEN 1 414 #define CLK_VDEC_IMGRZ_CKEN 2 415 #define CLK_VDEC_NR_CLK 3 416 417 /* VENCSYS */ 418 419 #define CLK_VENC_SMI_COMMON_CON 0 420 #define CLK_VENC_VENC 1 421 #define CLK_VENC_SMI_LARB6 2 422 #define CLK_VENC_NR_CLK 3 423 424 /* JPGDECSYS */ 425 426 #define CLK_JPGDEC_JPGDEC1 0 427 #define CLK_JPGDEC_JPGDEC 1 428 #define CLK_JPGDEC_NR_CLK 2 429 430 #endif /* _DT_BINDINGS_CLK_MT2712_H */ 431
Indexes created Mon Sep 29 21:09:56 GMT 2025