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    Searched refs:CLK_TOP_F_MP0_PLL1 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
mt2712-clk.h	70 #define CLK_TOP_F_MP0_PLL1 37
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
mt2712e.dtsi	90 <&topckgen CLK_TOP_F_MP0_PLL1>; 103 <&topckgen CLK_TOP_F_MP0_PLL1>;

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