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    Searched refs:CONVERT_FROM_HOST_TO_SMC_UL (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
pp_endian.h 35 #define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X))
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_iceland_smumgr.c 643 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
668 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
693 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
756 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
757 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
950 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);
951 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
953 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
954 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
955 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum)
    [all...]
amdgpu_fiji_smumgr.c 820 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
821 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
993 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
994 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
996 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
997 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
998 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
999 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
1000 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1001 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1)
    [all...]
amdgpu_ci_smumgr.c 461 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVddcPhases);
462 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
464 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
465 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
466 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
467 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
468 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
469 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
868 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
896 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount)
    [all...]
amdgpu_tonga_smumgr.c 319 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
336 CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
366 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
390 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
499 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
500 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
676 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
677 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
678 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
680 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3)
    [all...]
amdgpu_vegam_smumgr.c 559 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
560 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
849 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
850 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
851 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
853 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1025 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1026 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1030 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1147 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags)
    [all...]
amdgpu_polaris10_smumgr.c 758 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
759 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
965 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
966 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
967 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
969 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1121 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1122 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1124 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1236 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags)
    [all...]

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