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    Searched refs:CPU_CONTROL_DC_ENABLE (Results 1 - 18 of 18) sorted by relevancy

  /src/sys/arch/arm/arm/
cpufunc.c 2641 { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2642 { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2643 { "arm9.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2645 { "arm9.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
2658 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
2662 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
2694 { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2695 { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2696 { "arm10.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2698 { "arm10.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
    [all...]
armv6_start.S 667 tst r0, #CPU_CONTROL_DC_ENABLE
674 CPU_CONTROL_DC_ENABLE | \
994 ldr r2, =(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
  /src/sys/arch/evbarm/armadaxp/
armadaxp_start.S 73 movw r1, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
120 | CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
  /src/sys/arch/hpcarm/hpcarm/
kloader_pxa2x0.S 56 bic r2, r2, #CPU_CONTROL_DC_ENABLE
  /src/sys/arch/evbarm/gemini/
gemini_start.S 316 CPU_CONTROL_DC_ENABLE | \
323 CPU_CONTROL_DC_ENABLE | \
338 .word ~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
  /src/sys/arch/evbarm/gumstix/
gumstix_start.S 106 bic ip, ip, #CPU_CONTROL_DC_ENABLE
  /src/sys/arch/evbarm/imx23_olinuxino/
imx23_olinuxino_start.S 132 ldr r1, =(CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE \
  /src/sys/arch/evbarm/ixm1200/
ixm1200_start.S 65 orr r0, r0, #CPU_CONTROL_DC_ENABLE
  /src/sys/arch/evbarm/stand/board/
s3c2410_vector.S 73 ldr r0, =(CPU_CONTROL_MMU_ENABLE|CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE)
s3c2800_vector.S 105 ldr r0, =(CPU_CONTROL_MMU_ENABLE|CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE)
  /src/sys/arch/zaurus/zaurus/
kloader_zaurus.S 69 bic r2, r2, #CPU_CONTROL_DC_ENABLE
  /src/sys/arch/arm/arm32/
locore.S 185 bic r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
cpu.c 739 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0)
  /src/sys/arch/epoc32/epoc32/
epoc32_start.S 237 CPU_CONTROL_DC_ENABLE | \
  /src/sys/arch/evbarm/marvell/
marvell_start.S 244 biceq r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE)
  /src/sys/arch/acorn32/stand/boot32/
start.S 152 orr r0, r0, #CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_MMU_ENABLE
  /src/sys/arch/evbarm/armadillo/
armadillo9_start.S 62 bic r2, r2, #CPU_CONTROL_DC_ENABLE
  /src/sys/arch/arm/include/
armreg.h 188 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
216 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE

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