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      1 /*	$NetBSD: s3c2410_vector.S,v 1.2 2005/12/11 12:17:09 christos Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2003 By Noon Software, Inc.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. The names of the authors may not be used to endorse or promote products
     15  *    derived from this software without specific prior written permission.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 /*
     30  * Vector and initialize for S3C2410 based systems.
     31  */
     32 
     33 #include <machine/asm.h>
     34 #include <arm/armreg.h>
     35 #include <arm/s3c2xx0/s3c2410reg.h>
     36 
     37 
     38 #define TEMP_STACK_SIZE	(4*1024)
     39 
     40 	.code 32
     41 	.section ".vectors"
     42 
     43 reset_vector:
     44 	b	__reset_entry
     45 undef:
     46 	b	.
     47 swi:
     48 	b	.
     49 abrtp:
     50 	b	.
     51 abrtd:
     52 	b	.
     53 resv:
     54 	b	.
     55 irq:
     56 	b	.
     57 fiq:
     58 	b	.
     59 
     60 /*
     61  * Normally this code lives on ROM and runs immediately after reset, but
     62  * it may run on RAM and/or be called after system has been initialized.
     63  */
     64 __reset_entry:
     65 	mrs	r0, cpsr
     66 	/* SVC mode, Disable interrupts */
     67 	bic	r0, r0, #PSR_MODE
     68 	orr	r0, r0, #(I32_bit|F32_bit|PSR_SVC32_MODE)
     69 	msr	cpsr, r0
     70 
     71 	/* Disable MMU, Disable cache */
     72 	mrc	p15, 0, r10, c1, c0, 0
     73 	ldr	r0, =(CPU_CONTROL_MMU_ENABLE|CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE)
     74 	bic	r10, r10, r0
     75 	mcr	p15, 0, r10, c1, c0, 0
     76 	nop
     77 	nop
     78 	nop
     79 
     80 	/* invalidate I-cache */
     81 	mcr	p15, 0, r2, c7, c5, 0
     82 	nop
     83 	nop
     84 	nop
     85 
     86 	/* Enable I-cache */
     87 	orr	r10, r10, #CPU_CONTROL_IC_ENABLE
     88 	mcr	p15, 0, r10, c1, c0, 0
     89 	nop
     90 	nop
     91 	nop
     92 
     93 	/* Stop WDT */
     94 	ldr	r0, Lwdt_wtcon_addr
     95 	mov	r1, #WTCON_WDTSTOP
     96 	str	r1, [r0]
     97 
     98 	/* Disable all interrupts */
     99 	ldr	r0, Lintctl_intmsk_addr
    100 	mov	r1, #0x0
    101 	str	r1, [r0]
    102 
    103 	ldr	r9, =S3C2410_GPIO_BASE
    104 	/* LEDs on SMDK2410 */
    105 	mov	r1, #0x5500
    106 	str	r1, [r9, #GPIO_PFCON]
    107 	mov	r1, #0xe0
    108 	str	r1, [r9, #GPIO_PFDAT]
    109 
    110 	mov	r0, pc
    111 	cmp	r0, #S3C2410_SDRAM_START
    112 	bhs	running_on_ram
    113 
    114 	ldr	r8, =S3C2410_CLKMAN_BASE
    115 	ldr	r1, [r8,#CLKMAN_CLKDIVN]
    116 	orr	r1, r1, #CLKDIVN_HDIVN|CLKDIVN_PDIVN
    117 	str	r1, [r8,#CLKMAN_CLKDIVN]
    118 
    119 	ldr	r1, Lclkman_locktime_data
    120 	str	r1, [r8,#CLKMAN_LOCKTIME]
    121 
    122 	/* Initialize PLL */
    123 	ldr	r1, Lclkman_mpllcon_data
    124 	str	r1, [r8,#CLKMAN_MPLLCON]
    125 	ldr	r1, Lclkman_upllcon_data
    126 	str	r1, [r8,#CLKMAN_UPLLCON]
    127 
    128 	ldr	r9, =S3C2410_GPIO_BASE
    129 	mov	r1, #0xd0
    130 	str	r1, [r9, #GPIO_PFDAT]
    131 
    132 #ifdef RAM_INIT_HOOK
    133 	bl	RAM_INIT_HOOK
    134 #endif
    135 
    136 running_on_ram:
    137 	/* Change Bus mode to Sync */
    138 	mrc	p15, 0, r0, c1, c0, 0
    139 	bic	r0, r0, #(1<<31)		/* unset iA bit */
    140 	orr	r0, r0, #(1<<30)		/* set nF bit */
    141 	mcr	p15, 0, r0, c1, c0, 0
    142 	nop
    143 	nop
    144 	nop
    145 
    146 	ldr	r9, =S3C2410_GPIO_BASE
    147 	mov	r1, #0xb0
    148 	str	r1, [r9, #GPIO_PFDAT]
    149 
    150 	/* set temporary stack */
    151 	adr	sp, reset_vector
    152 	/* do we have a room below? */
    153 	ldr	r1, =(S3C2410_SDRAM_START+TEMP_STACK_SIZE)
    154 	cmp	sp, r1
    155 	/* otherwise use top area of RAM */
    156 	ldrlo	sp, =(S3C2410_SDRAM_START+SDRAM_SIZE)
    157 
    158 #ifdef IO_INIT_HOOK
    159 	bl	IO_INIT_HOOK
    160 #endif
    161 
    162 	ldr	r9, =S3C2410_GPIO_BASE
    163 	mov	r1, #0x70
    164 	str	r1, [r9, #GPIO_PFDAT]
    165 
    166 	b	start
    167 
    168 Lwdt_wtcon_addr:
    169 	.word	(S3C2410_WDT_BASE + WDT_WTCON)
    170 
    171 Lintctl_intmsk_addr:
    172 	.word	(S3C2410_INTCTL_BASE + INTCTL_INTMSK)
    173 
    174 	.ltorg
    175 
    176 Lclkman_locktime_data:
    177 	.word	(0xffffff)
    178 
    179 Lclkman_mpllcon_data:
    180 #if XTAL_CLK == 12000000 && FCLK == 180000000
    181 	.word	0x00052011	/* M=82, P=1, S=1 */
    182 #else
    183 #error	illegal XTAL_CLK/FCLK combination
    184 #endif
    185 Lclkman_upllcon_data:
    186 	.word	0x00078023	/* M=120, P=2, S=3 */
    187