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    Searched refs:CPU_CONTROL_IC_ENABLE (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/arch/arm/arm/
cpufunc.c 2641 { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2642 { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2643 { "arm9.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2644 { "arm9.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
2658 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
2662 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
2694 { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2695 { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2696 { "arm10.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2697 { "arm10.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
    [all...]
armv6_start.S 673 CPU_CONTROL_IC_ENABLE | \
994 ldr r2, =(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
  /src/sys/arch/evbarm/armadaxp/
armadaxp_start.S 74 CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_IC_ENABLE |\
119 #define CPU_CONTROL_SET (CPU_CONTROL_XP_ENABLE | CPU_CONTROL_IC_ENABLE \
  /src/sys/arch/evbarm/stand/board/
s3c2410_vector.S 73 ldr r0, =(CPU_CONTROL_MMU_ENABLE|CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE)
87 orr r10, r10, #CPU_CONTROL_IC_ENABLE
s3c2800_vector.S 105 ldr r0, =(CPU_CONTROL_MMU_ENABLE|CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE)
119 orr r10, r10, #CPU_CONTROL_IC_ENABLE
  /src/sys/arch/hpcarm/hpcarm/
kloader_pxa2x0.S 57 bic r2, r2, #CPU_CONTROL_IC_ENABLE
  /src/sys/arch/evbarm/imx23_olinuxino/
imx23_olinuxino_start.S 132 ldr r1, =(CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE \
  /src/sys/arch/evbarm/ixm1200/
ixm1200_start.S 70 orr r0, r0, #CPU_CONTROL_IC_ENABLE
  /src/sys/arch/zaurus/zaurus/
kloader_zaurus.S 70 bic r2, r2, #CPU_CONTROL_IC_ENABLE
  /src/sys/arch/evbarm/gemini/
gemini_start.S 322 CPU_CONTROL_IC_ENABLE | \
338 .word ~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
  /src/sys/arch/arm/arm32/
locore.S 186 bic r0, r0, #(CPU_CONTROL_IC_ENABLE)
cpu.c 743 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0)
  /src/sys/arch/epoc32/epoc32/
epoc32_start.S 241 CPU_CONTROL_IC_ENABLE
  /src/sys/arch/evbarm/marvell/
marvell_start.S 245 biceq r0, r0, #(CPU_CONTROL_IC_ENABLE)
  /src/sys/arch/evbarm/armadillo/
armadillo9_start.S 63 bic r2, r2, #CPU_CONTROL_IC_ENABLE
  /src/sys/arch/arm/include/
armreg.h 199 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */

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