| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| smu72_discrete.h | 501 uint32_t CP_INT_CNTL;
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| smu73_discrete.h | 497 uint32_t CP_INT_CNTL;
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| smu74_discrete.h | 491 uint32_t CP_INT_CNTL;
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| smu75_discrete.h | 503 uint32_t CP_INT_CNTL;
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| nid.h | 496 #define CP_INT_CNTL 0xC124
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| evergreend.h | 1248 #define CP_INT_CNTL 0xc124
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| r600d.h | 716 #define CP_INT_CNTL 0xc124
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| radeon_ni.c | 1400 int ring, u32 cp_int_cntl)
1403 WREG32(CP_INT_CNTL, cp_int_cntl);
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| radeon_r600.c | 3658 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3799 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; local in function:r600_irq_set
3857 cp_int_cntl |= RB_INT_ENABLE;
3858 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3909 WREG32(CP_INT_CNTL, cp_int_cntl);
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| radeon_evergreen.c | 222 int ring, u32 cp_int_cntl);
4476 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
4499 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; local in function:evergreen_irq_set
4530 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
4543 cp_int_cntl |= RB_INT_ENABLE;
4544 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
4567 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
4571 WREG32(CP_INT_CNTL, cp_int_cntl);
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gfx_v8_0.c | 6649 WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
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