1 /* $NetBSD: smu75_discrete.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef SMU75_DISCRETE_H 27 #define SMU75_DISCRETE_H 28 29 #include "smu75.h" 30 31 #pragma pack(push, 1) 32 33 #define NUM_SCLK_RANGE 8 34 35 #define VCO_3_6 1 36 #define VCO_2_4 3 37 38 #define POSTDIV_DIV_BY_1 0 39 #define POSTDIV_DIV_BY_2 1 40 #define POSTDIV_DIV_BY_4 2 41 #define POSTDIV_DIV_BY_8 3 42 #define POSTDIV_DIV_BY_16 4 43 44 struct sclkFcwRange_t { 45 uint8_t vco_setting; /* 1: 3-6GHz, 3: 2-4GHz */ 46 uint8_t postdiv; /* divide by 2^n */ 47 uint16_t fcw_pcc; 48 uint16_t fcw_trans_upper; 49 uint16_t fcw_trans_lower; 50 }; 51 typedef struct sclkFcwRange_t sclkFcwRange_t; 52 53 struct SMIO_Pattern { 54 uint16_t Voltage; 55 uint8_t Smio; 56 uint8_t padding; 57 }; 58 59 typedef struct SMIO_Pattern SMIO_Pattern; 60 61 struct SMIO_Table { 62 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; 63 }; 64 65 typedef struct SMIO_Table SMIO_Table; 66 67 struct SMU_SclkSetting { 68 uint32_t SclkFrequency; 69 uint16_t Fcw_int; 70 uint16_t Fcw_frac; 71 uint16_t Pcc_fcw_int; 72 uint8_t PllRange; 73 uint8_t SSc_En; 74 uint16_t Sclk_slew_rate; 75 uint16_t Pcc_up_slew_rate; 76 uint16_t Pcc_down_slew_rate; 77 uint16_t Fcw1_int; 78 uint16_t Fcw1_frac; 79 uint16_t Sclk_ss_slew_rate; 80 }; 81 typedef struct SMU_SclkSetting SMU_SclkSetting; 82 83 struct SMU75_Discrete_GraphicsLevel { 84 SMU_VoltageLevel MinVoltage; 85 86 uint8_t pcieDpmLevel; 87 uint8_t DeepSleepDivId; 88 uint16_t ActivityLevel; 89 90 uint32_t CgSpllFuncCntl3; 91 uint32_t CgSpllFuncCntl4; 92 uint32_t CcPwrDynRm; 93 uint32_t CcPwrDynRm1; 94 95 uint8_t SclkDid; 96 uint8_t padding; 97 uint8_t EnabledForActivity; 98 uint8_t EnabledForThrottle; 99 uint8_t UpHyst; 100 uint8_t DownHyst; 101 uint8_t VoltageDownHyst; 102 uint8_t PowerThrottle; 103 104 SMU_SclkSetting SclkSetting; 105 106 uint8_t ScksStretchThreshVid[NUM_SCKS_STATE_TYPES]; 107 uint16_t Padding; 108 }; 109 110 typedef struct SMU75_Discrete_GraphicsLevel SMU75_Discrete_GraphicsLevel; 111 112 struct SMU75_Discrete_ACPILevel { 113 uint32_t Flags; 114 SMU_VoltageLevel MinVoltage; 115 uint32_t SclkFrequency; 116 uint8_t SclkDid; 117 uint8_t DisplayWatermark; 118 uint8_t DeepSleepDivId; 119 uint8_t padding; 120 uint32_t CcPwrDynRm; 121 uint32_t CcPwrDynRm1; 122 123 SMU_SclkSetting SclkSetting; 124 }; 125 126 typedef struct SMU75_Discrete_ACPILevel SMU75_Discrete_ACPILevel; 127 128 struct SMU75_Discrete_Ulv { 129 uint32_t CcPwrDynRm; 130 uint32_t CcPwrDynRm1; 131 uint16_t VddcOffset; 132 uint8_t VddcOffsetVid; 133 uint8_t VddcPhase; 134 uint16_t BifSclkDfs; 135 uint16_t Reserved; 136 }; 137 138 typedef struct SMU75_Discrete_Ulv SMU75_Discrete_Ulv; 139 140 struct SMU75_Discrete_MemoryLevel { 141 SMU_VoltageLevel MinVoltage; 142 uint32_t MinMvdd; 143 144 uint32_t MclkFrequency; 145 146 uint8_t StutterEnable; 147 uint8_t EnabledForThrottle; 148 uint8_t EnabledForActivity; 149 uint8_t padding_0; 150 151 uint8_t UpHyst; 152 uint8_t DownHyst; 153 uint8_t VoltageDownHyst; 154 uint8_t padding_1; 155 156 uint16_t ActivityLevel; 157 uint8_t DisplayWatermark; 158 uint8_t padding_2; 159 160 uint16_t Fcw_int; 161 uint16_t Fcw_frac; 162 uint8_t Postdiv; 163 uint8_t padding_3[3]; 164 }; 165 166 typedef struct SMU75_Discrete_MemoryLevel SMU75_Discrete_MemoryLevel; 167 168 struct SMU75_Discrete_LinkLevel { 169 uint8_t PcieGenSpeed; 170 uint8_t PcieLaneCount; 171 uint8_t EnabledForActivity; 172 uint8_t SPC; 173 uint32_t DownThreshold; 174 uint32_t UpThreshold; 175 uint16_t BifSclkDfs; 176 uint16_t Reserved; 177 }; 178 179 typedef struct SMU75_Discrete_LinkLevel SMU75_Discrete_LinkLevel; 180 181 182 /* MC ARB DRAM Timing registers. */ 183 struct SMU75_Discrete_MCArbDramTimingTableEntry { 184 uint32_t McArbDramTiming; 185 uint32_t McArbDramTiming2; 186 uint32_t McArbBurstTime; 187 uint32_t McArbRfshRate; 188 uint32_t McArbMisc3; 189 }; 190 191 typedef struct SMU75_Discrete_MCArbDramTimingTableEntry SMU75_Discrete_MCArbDramTimingTableEntry; 192 193 struct SMU75_Discrete_MCArbDramTimingTable { 194 SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 195 }; 196 197 typedef struct SMU75_Discrete_MCArbDramTimingTable SMU75_Discrete_MCArbDramTimingTable; 198 199 /* UVD VCLK/DCLK state (level) definition. */ 200 struct SMU75_Discrete_UvdLevel { 201 uint32_t VclkFrequency; 202 uint32_t DclkFrequency; 203 SMU_VoltageLevel MinVoltage; 204 uint8_t VclkDivider; 205 uint8_t DclkDivider; 206 uint8_t padding[2]; 207 }; 208 209 typedef struct SMU75_Discrete_UvdLevel SMU75_Discrete_UvdLevel; 210 211 /* Clocks for other external blocks (VCE, ACP, SAMU). */ 212 struct SMU75_Discrete_ExtClkLevel { 213 uint32_t Frequency; 214 SMU_VoltageLevel MinVoltage; 215 uint8_t Divider; 216 uint8_t padding[3]; 217 }; 218 219 typedef struct SMU75_Discrete_ExtClkLevel SMU75_Discrete_ExtClkLevel; 220 221 struct SMU75_Discrete_StateInfo { 222 uint32_t SclkFrequency; 223 uint32_t MclkFrequency; 224 uint32_t VclkFrequency; 225 uint32_t DclkFrequency; 226 uint32_t SamclkFrequency; 227 uint32_t AclkFrequency; 228 uint32_t EclkFrequency; 229 uint16_t MvddVoltage; 230 uint16_t padding16; 231 uint8_t DisplayWatermark; 232 uint8_t McArbIndex; 233 uint8_t McRegIndex; 234 uint8_t SeqIndex; 235 uint8_t SclkDid; 236 int8_t SclkIndex; 237 int8_t MclkIndex; 238 uint8_t PCIeGen; 239 }; 240 241 typedef struct SMU75_Discrete_StateInfo SMU75_Discrete_StateInfo; 242 243 struct SMU75_Discrete_DpmTable { 244 SMU75_PIDController GraphicsPIDController; 245 SMU75_PIDController MemoryPIDController; 246 SMU75_PIDController LinkPIDController; 247 248 uint32_t SystemFlags; 249 250 uint32_t VRConfig; 251 uint32_t SmioMask1; 252 uint32_t SmioMask2; 253 SMIO_Table SmioTable1; 254 SMIO_Table SmioTable2; 255 256 uint32_t MvddLevelCount; 257 258 uint8_t BapmVddcVidHiSidd [SMU75_MAX_LEVELS_VDDC]; 259 uint8_t BapmVddcVidLoSidd [SMU75_MAX_LEVELS_VDDC]; 260 uint8_t BapmVddcVidHiSidd2 [SMU75_MAX_LEVELS_VDDC]; 261 262 uint8_t GraphicsDpmLevelCount; 263 uint8_t MemoryDpmLevelCount; 264 uint8_t LinkLevelCount; 265 uint8_t MasterDeepSleepControl; 266 267 uint8_t UvdLevelCount; 268 uint8_t VceLevelCount; 269 uint8_t AcpLevelCount; 270 uint8_t SamuLevelCount; 271 272 uint8_t ThermOutGpio; 273 uint8_t ThermOutPolarity; 274 uint8_t ThermOutMode; 275 uint8_t BootPhases; 276 277 uint8_t VRHotLevel; 278 uint8_t LdoRefSel; 279 280 uint8_t Reserved1[2]; 281 282 uint16_t FanStartTemperature; 283 uint16_t FanStopTemperature; 284 285 uint16_t MaxVoltage; 286 uint16_t Reserved2; 287 uint32_t Reserved; 288 289 SMU75_Discrete_GraphicsLevel GraphicsLevel [SMU75_MAX_LEVELS_GRAPHICS]; 290 SMU75_Discrete_MemoryLevel MemoryACPILevel; 291 SMU75_Discrete_MemoryLevel MemoryLevel [SMU75_MAX_LEVELS_MEMORY]; 292 SMU75_Discrete_LinkLevel LinkLevel [SMU75_MAX_LEVELS_LINK]; 293 SMU75_Discrete_ACPILevel ACPILevel; 294 SMU75_Discrete_UvdLevel UvdLevel [SMU75_MAX_LEVELS_UVD]; 295 SMU75_Discrete_ExtClkLevel VceLevel [SMU75_MAX_LEVELS_VCE]; 296 SMU75_Discrete_ExtClkLevel AcpLevel [SMU75_MAX_LEVELS_ACP]; 297 SMU75_Discrete_ExtClkLevel SamuLevel [SMU75_MAX_LEVELS_SAMU]; 298 SMU75_Discrete_Ulv Ulv; 299 300 uint8_t DisplayWatermark [SMU75_MAX_LEVELS_MEMORY][SMU75_MAX_LEVELS_GRAPHICS]; 301 302 uint32_t SclkStepSize; 303 uint32_t Smio [SMU75_MAX_ENTRIES_SMIO]; 304 305 uint8_t UvdBootLevel; 306 uint8_t VceBootLevel; 307 uint8_t AcpBootLevel; 308 uint8_t SamuBootLevel; 309 310 uint8_t GraphicsBootLevel; 311 uint8_t GraphicsVoltageChangeEnable; 312 uint8_t GraphicsThermThrottleEnable; 313 uint8_t GraphicsInterval; 314 315 uint8_t VoltageInterval; 316 uint8_t ThermalInterval; 317 uint16_t TemperatureLimitHigh; 318 319 uint16_t TemperatureLimitLow; 320 uint8_t MemoryBootLevel; 321 uint8_t MemoryVoltageChangeEnable; 322 323 uint16_t BootMVdd; 324 uint8_t MemoryInterval; 325 uint8_t MemoryThermThrottleEnable; 326 327 uint16_t VoltageResponseTime; 328 uint16_t PhaseResponseTime; 329 330 uint8_t PCIeBootLinkLevel; 331 uint8_t PCIeGenInterval; 332 uint8_t DTEInterval; 333 uint8_t DTEMode; 334 335 uint8_t SVI2Enable; 336 uint8_t VRHotGpio; 337 uint8_t AcDcGpio; 338 uint8_t ThermGpio; 339 340 uint16_t PPM_PkgPwrLimit; 341 uint16_t PPM_TemperatureLimit; 342 343 uint16_t DefaultTdp; 344 uint16_t TargetTdp; 345 346 uint16_t FpsHighThreshold; 347 uint16_t FpsLowThreshold; 348 349 uint16_t BAPMTI_R [SMU75_DTE_ITERATIONS][SMU75_DTE_SOURCES][SMU75_DTE_SINKS]; 350 uint16_t BAPMTI_RC [SMU75_DTE_ITERATIONS][SMU75_DTE_SOURCES][SMU75_DTE_SINKS]; 351 352 uint16_t TemperatureLimitEdge; 353 uint16_t TemperatureLimitHotspot; 354 355 uint16_t BootVddc; 356 uint16_t BootVddci; 357 358 uint16_t FanGainEdge; 359 uint16_t FanGainHotspot; 360 361 uint32_t LowSclkInterruptThreshold; 362 uint32_t VddGfxReChkWait; 363 364 uint8_t ClockStretcherAmount; 365 uint8_t Sclk_CKS_masterEn0_7; 366 uint8_t Sclk_CKS_masterEn8_15; 367 uint8_t DPMFreezeAndForced; 368 369 uint8_t Sclk_voltageOffset[8]; 370 371 SMU_ClockStretcherDataTable ClockStretcherDataTable; 372 SMU_CKS_LOOKUPTable CKS_LOOKUPTable; 373 374 uint32_t CurrSclkPllRange; 375 sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE]; 376 377 GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES]; 378 SMU_QuadraticCoeffs AVFSGB_FUSE_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES]; 379 }; 380 381 typedef struct SMU75_Discrete_DpmTable SMU75_Discrete_DpmTable; 382 383 struct SMU75_Discrete_FanTable { 384 uint16_t FdoMode; 385 int16_t TempMin; 386 int16_t TempMed; 387 int16_t TempMax; 388 int16_t Slope1; 389 int16_t Slope2; 390 int16_t FdoMin; 391 int16_t HystUp; 392 int16_t HystDown; 393 int16_t HystSlope; 394 int16_t TempRespLim; 395 int16_t TempCurr; 396 int16_t SlopeCurr; 397 int16_t PwmCurr; 398 uint32_t RefreshPeriod; 399 int16_t FdoMax; 400 uint8_t TempSrc; 401 int8_t Padding; 402 }; 403 404 typedef struct SMU75_Discrete_FanTable SMU75_Discrete_FanTable; 405 406 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 407 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) 408 409 410 411 struct SMU7_MclkDpmScoreboard { 412 uint32_t PercentageBusy; 413 414 int32_t PIDError; 415 int32_t PIDIntegral; 416 int32_t PIDOutput; 417 418 uint32_t SigmaDeltaAccum; 419 uint32_t SigmaDeltaOutput; 420 uint32_t SigmaDeltaLevel; 421 422 uint32_t UtilizationSetpoint; 423 424 uint8_t TdpClampMode; 425 uint8_t TdcClampMode; 426 uint8_t ThermClampMode; 427 uint8_t VoltageBusy; 428 429 int8_t CurrLevel; 430 int8_t TargLevel; 431 uint8_t LevelChangeInProgress; 432 uint8_t UpHyst; 433 434 uint8_t DownHyst; 435 uint8_t VoltageDownHyst; 436 uint8_t DpmEnable; 437 uint8_t DpmRunning; 438 439 uint8_t DpmForce; 440 uint8_t DpmForceLevel; 441 uint8_t padding2; 442 uint8_t McArbIndex; 443 444 uint32_t MinimumPerfMclk; 445 446 uint8_t AcpiReq; 447 uint8_t AcpiAck; 448 uint8_t MclkSwitchInProgress; 449 uint8_t MclkSwitchCritical; 450 451 uint8_t IgnoreVBlank; 452 uint8_t TargetMclkIndex; 453 uint8_t TargetMvddIndex; 454 uint8_t MclkSwitchResult; 455 456 uint16_t VbiFailureCount; 457 uint8_t VbiWaitCounter; 458 uint8_t EnabledLevelsChange; 459 460 uint16_t LevelResidencyCounters [SMU75_MAX_LEVELS_MEMORY]; 461 uint16_t LevelSwitchCounters [SMU75_MAX_LEVELS_MEMORY]; 462 463 void (*TargetStateCalculator)(uint8_t); 464 void (*SavedTargetStateCalculator)(uint8_t); 465 466 uint16_t AutoDpmInterval; 467 uint16_t AutoDpmRange; 468 469 uint16_t VbiTimeoutCount; 470 uint16_t MclkSwitchingTime; 471 472 uint8_t fastSwitch; 473 uint8_t Save_PIC_VDDGFX_EXIT; 474 uint8_t Save_PIC_VDDGFX_ENTER; 475 uint8_t VbiTimeout; 476 477 uint32_t HbmTempRegBackup; 478 }; 479 480 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; 481 482 struct SMU7_UlvScoreboard { 483 uint8_t EnterUlv; 484 uint8_t ExitUlv; 485 uint8_t UlvActive; 486 uint8_t WaitingForUlv; 487 uint8_t UlvEnable; 488 uint8_t UlvRunning; 489 uint8_t UlvMasterEnable; 490 uint8_t padding; 491 uint32_t UlvAbortedCount; 492 uint32_t UlvTimeStamp; 493 }; 494 495 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; 496 497 struct VddgfxSavedRegisters { 498 uint32_t GPU_DBG[3]; 499 uint32_t MEC_BaseAddress_Hi; 500 uint32_t MEC_BaseAddress_Lo; 501 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; 502 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; 503 uint32_t CP_INT_CNTL; 504 }; 505 506 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; 507 508 struct SMU7_VddGfxScoreboard { 509 uint8_t VddGfxEnable; 510 uint8_t VddGfxActive; 511 uint8_t VPUResetOccured; 512 uint8_t padding; 513 514 uint32_t VddGfxEnteredCount; 515 uint32_t VddGfxAbortedCount; 516 517 uint32_t VddGfxVid; 518 519 VddgfxSavedRegisters SavedRegisters; 520 }; 521 522 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; 523 524 struct SMU7_TdcLimitScoreboard { 525 uint8_t Enable; 526 uint8_t Running; 527 uint16_t Alpha; 528 uint32_t FilteredIddc; 529 uint32_t IddcLimit; 530 uint32_t IddcHyst; 531 SMU7_HystController_Data HystControllerData; 532 }; 533 534 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; 535 536 struct SMU7_PkgPwrLimitScoreboard { 537 uint8_t Enable; 538 uint8_t Running; 539 uint16_t Alpha; 540 uint32_t FilteredPkgPwr; 541 uint32_t Limit; 542 uint32_t Hyst; 543 uint32_t LimitFromDriver; 544 uint8_t PowerSharingEnabled; 545 uint8_t PowerSharingCounter; 546 uint8_t PowerSharingINTEnabled; 547 uint8_t GFXActivityCounterEnabled; 548 uint32_t EnergyCount; 549 uint32_t PSACTCount; 550 uint8_t RollOverRequired; 551 uint8_t RollOverCount; 552 uint8_t padding[2]; 553 SMU7_HystController_Data HystControllerData; 554 }; 555 556 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; 557 558 struct SMU7_BapmScoreboard { 559 uint32_t source_powers[SMU75_DTE_SOURCES]; 560 uint32_t source_powers_last[SMU75_DTE_SOURCES]; 561 int32_t entity_temperatures[SMU75_NUM_GPU_TES]; 562 int32_t initial_entity_temperatures[SMU75_NUM_GPU_TES]; 563 int32_t Limit; 564 int32_t Hyst; 565 int32_t therm_influence_coeff_table[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS * 2]; 566 int32_t therm_node_table[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS]; 567 uint16_t ConfigTDPPowerScalar; 568 uint16_t FanSpeedPowerScalar; 569 uint16_t OverDrivePowerScalar; 570 uint16_t OverDriveLimitScalar; 571 uint16_t FinalPowerScalar; 572 uint8_t VariantID; 573 uint8_t spare997; 574 575 SMU7_HystController_Data HystControllerData; 576 577 int32_t temperature_gradient_slope; 578 int32_t temperature_gradient; 579 uint32_t measured_temperature; 580 }; 581 582 583 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; 584 585 struct SMU7_AcpiScoreboard { 586 uint32_t SavedInterruptMask[2]; 587 uint8_t LastACPIRequest; 588 uint8_t CgBifResp; 589 uint8_t RequestType; 590 uint8_t Padding; 591 SMU75_Discrete_ACPILevel D0Level; 592 }; 593 594 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; 595 596 struct SMU75_Discrete_PmFuses { 597 uint8_t BapmVddCVidHiSidd[8]; 598 599 uint8_t BapmVddCVidLoSidd[8]; 600 601 uint8_t VddCVid[8]; 602 603 uint8_t SviLoadLineEn; 604 uint8_t SviLoadLineVddC; 605 uint8_t SviLoadLineTrimVddC; 606 uint8_t SviLoadLineOffsetVddC; 607 608 uint16_t TDC_VDDC_PkgLimit; 609 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 610 uint8_t TDC_MAWt; 611 612 uint8_t TdcWaterfallCtl; 613 uint8_t LPMLTemperatureMin; 614 uint8_t LPMLTemperatureMax; 615 uint8_t Reserved; 616 617 uint8_t LPMLTemperatureScaler[16]; 618 619 int16_t FuzzyFan_ErrorSetDelta; 620 int16_t FuzzyFan_ErrorRateSetDelta; 621 int16_t FuzzyFan_PwmSetDelta; 622 uint16_t Reserved6; 623 624 uint8_t GnbLPML[16]; 625 626 uint8_t GnbLPMLMaxVid; 627 uint8_t GnbLPMLMinVid; 628 uint8_t Reserved1[2]; 629 630 uint16_t BapmVddCBaseLeakageHiSidd; 631 uint16_t BapmVddCBaseLeakageLoSidd; 632 633 uint16_t VFT_Temp[3]; 634 uint8_t Version; 635 uint8_t padding; 636 637 SMU_QuadraticCoeffs VFT_ATE[3]; 638 639 SMU_QuadraticCoeffs AVFS_GB; 640 SMU_QuadraticCoeffs ATE_ACBTC_GB; 641 642 SMU_QuadraticCoeffs P2V; 643 644 uint32_t PsmCharzFreq; 645 646 uint16_t InversionVoltage; 647 uint16_t PsmCharzTemp; 648 649 uint32_t EnabledAvfsModules; 650 651 SMU_QuadraticCoeffs BtcGbv_CksOff; 652 }; 653 654 typedef struct SMU75_Discrete_PmFuses SMU75_Discrete_PmFuses; 655 656 struct SMU7_Discrete_Log_Header_Table { 657 uint32_t version; 658 uint32_t asic_id; 659 uint16_t flags; 660 uint16_t entry_size; 661 uint32_t total_size; 662 uint32_t num_of_entries; 663 uint8_t type; 664 uint8_t mode; 665 uint8_t filler_0[2]; 666 uint32_t filler_1[2]; 667 }; 668 669 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; 670 671 struct SMU7_Discrete_Log_Cntl { 672 uint8_t Enabled; 673 uint8_t Type; 674 uint8_t padding[2]; 675 uint32_t BufferSize; 676 uint32_t SamplesLogged; 677 uint32_t SampleSize; 678 uint32_t AddrL; 679 uint32_t AddrH; 680 }; 681 682 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; 683 684 #if defined SMU__DGPU_ONLY 685 #define CAC_ACC_NW_NUM_OF_SIGNALS 87 686 #endif 687 688 689 struct SMU7_Discrete_Cac_Collection_Table { 690 uint32_t temperature; 691 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; 692 }; 693 694 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; 695 696 struct SMU7_Discrete_Cac_Verification_Table { 697 uint32_t VddcTotalPower; 698 uint32_t VddcLeakagePower; 699 uint32_t VddcConstantPower; 700 uint32_t VddcGfxDynamicPower; 701 uint32_t VddcUvdDynamicPower; 702 uint32_t VddcVceDynamicPower; 703 uint32_t VddcAcpDynamicPower; 704 uint32_t VddcPcieDynamicPower; 705 uint32_t VddcDceDynamicPower; 706 uint32_t VddcCurrent; 707 uint32_t VddcVoltage; 708 uint32_t VddciTotalPower; 709 uint32_t VddciLeakagePower; 710 uint32_t VddciConstantPower; 711 uint32_t VddciDynamicPower; 712 uint32_t Vddr1TotalPower; 713 uint32_t Vddr1LeakagePower; 714 uint32_t Vddr1ConstantPower; 715 uint32_t Vddr1DynamicPower; 716 uint32_t spare[4]; 717 uint32_t temperature; 718 }; 719 720 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; 721 722 struct SMU7_Discrete_Pm_Status_Table { 723 int32_t T_meas_max[SMU75_THERMAL_INPUT_LOOP_COUNT]; 724 int32_t T_meas_acc[SMU75_THERMAL_INPUT_LOOP_COUNT]; 725 726 uint32_t I_calc_max; 727 uint32_t I_calc_acc; 728 uint32_t P_meas_acc; 729 uint32_t V_meas_load_acc; 730 uint32_t I_meas_acc; 731 uint32_t P_meas_acc_vddci; 732 uint32_t V_meas_load_acc_vddci; 733 uint32_t I_meas_acc_vddci; 734 735 uint16_t Sclk_dpm_residency[8]; 736 uint16_t Uvd_dpm_residency[8]; 737 uint16_t Vce_dpm_residency[8]; 738 uint16_t Mclk_dpm_residency[4]; 739 740 uint32_t P_roc_acc; 741 uint32_t PkgPwr_max; 742 uint32_t PkgPwr_acc; 743 uint32_t MclkSwitchingTime_max; 744 uint32_t MclkSwitchingTime_acc; 745 uint32_t FanPwm_acc; 746 uint32_t FanRpm_acc; 747 uint32_t Gfx_busy_acc; 748 uint32_t Mc_busy_acc; 749 uint32_t Fps_acc; 750 751 uint32_t AccCnt; 752 }; 753 754 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; 755 756 struct SMU7_Discrete_AutoWattMan_Status_Table { 757 int32_t T_meas_acc[SMU75_THERMAL_INPUT_LOOP_COUNT]; 758 uint16_t Sclk_dpm_residency[8]; 759 uint16_t Mclk_dpm_residency[4]; 760 uint32_t TgpPwr_acc; 761 uint32_t Gfx_busy_acc; 762 uint32_t Mc_busy_acc; 763 uint32_t AccCnt; 764 }; 765 766 typedef struct SMU7_Discrete_AutoWattMan_Status_Table SMU7_Discrete_AutoWattMan_Status_Table; 767 768 #define SMU7_MAX_GFX_CU_COUNT 24 769 #define SMU7_MIN_GFX_CU_COUNT 8 770 #define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT 0 771 #define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_MASK (0xFFFF << SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT) 772 #define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT 16 773 #define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_MASK (0xFFFF << SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT) 774 775 struct SMU7_GfxCuPgScoreboard { 776 uint8_t Enabled; 777 uint8_t WaterfallUp; 778 uint8_t WaterfallDown; 779 uint8_t WaterfallLimit; 780 uint8_t CurrMaxCu; 781 uint8_t TargMaxCu; 782 uint8_t ClampMode; 783 uint8_t Active; 784 uint8_t MaxSupportedCu; 785 uint8_t MinSupportedCu; 786 uint8_t PendingGfxCuHostInterrupt; 787 uint8_t LastFilteredMaxCuInteger; 788 uint16_t FilteredMaxCu; 789 uint16_t FilteredMaxCuAlpha; 790 uint16_t FilterResetCount; 791 uint16_t FilterResetCountLimit; 792 uint8_t ForceCu; 793 uint8_t ForceCuCount; 794 uint8_t AcModeMaxCu; 795 uint8_t DcModeMaxCu; 796 }; 797 798 typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard; 799 800 #define SMU7_SCLK_CAC 0x561 801 #define SMU7_MCLK_CAC 0xF9 802 #define SMU7_VCLK_CAC 0x2DE 803 #define SMU7_DCLK_CAC 0x2DE 804 #define SMU7_ECLK_CAC 0x25E 805 #define SMU7_ACLK_CAC 0x25E 806 #define SMU7_SAMCLK_CAC 0x25E 807 #define SMU7_DISPCLK_CAC 0x100 808 #define SMU7_CAC_CONSTANT 0x2EE3430 809 #define SMU7_CAC_CONSTANT_SHIFT 18 810 811 #define SMU7_VDDCI_MCLK_CONST 1765 812 #define SMU7_VDDCI_MCLK_CONST_SHIFT 16 813 #define SMU7_VDDCI_VDDCI_CONST 50958 814 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 815 #define SMU7_VDDCI_CONST 11781 816 #define SMU7_VDDCI_STROBE_PWR 1331 817 818 #define SMU7_VDDR1_CONST 693 819 #define SMU7_VDDR1_CAC_WEIGHT 20 820 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 821 #define SMU7_VDDR1_STROBE_PWR 512 822 823 #define SMU7_AREA_COEFF_UVD 0xA78 824 #define SMU7_AREA_COEFF_VCE 0x190A 825 #define SMU7_AREA_COEFF_ACP 0x22D1 826 #define SMU7_AREA_COEFF_SAMU 0x534 827 828 #define SMU7_THERM_OUT_MODE_DISABLE 0x0 829 #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 830 #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 831 832 #define SQ_Enable_MASK 0x1 833 #define SQ_IR_MASK 0x2 834 #define SQ_PCC_MASK 0x4 835 #define SQ_EDC_MASK 0x8 836 837 #define TCP_Enable_MASK 0x100 838 #define TCP_IR_MASK 0x200 839 #define TCP_PCC_MASK 0x400 840 #define TCP_EDC_MASK 0x800 841 842 #define TD_Enable_MASK 0x10000 843 #define TD_IR_MASK 0x20000 844 #define TD_PCC_MASK 0x40000 845 #define TD_EDC_MASK 0x80000 846 847 #define DB_Enable_MASK 0x1000000 848 #define DB_IR_MASK 0x2000000 849 #define DB_PCC_MASK 0x4000000 850 #define DB_EDC_MASK 0x8000000 851 852 #define SQ_Enable_SHIFT 0 853 #define SQ_IR_SHIFT 1 854 #define SQ_PCC_SHIFT 2 855 #define SQ_EDC_SHIFT 3 856 857 #define TCP_Enable_SHIFT 8 858 #define TCP_IR_SHIFT 9 859 #define TCP_PCC_SHIFT 10 860 #define TCP_EDC_SHIFT 11 861 862 #define TD_Enable_SHIFT 16 863 #define TD_IR_SHIFT 17 864 #define TD_PCC_SHIFT 18 865 #define TD_EDC_SHIFT 19 866 867 #define DB_Enable_SHIFT 24 868 #define DB_IR_SHIFT 25 869 #define DB_PCC_SHIFT 26 870 #define DB_EDC_SHIFT 27 871 872 #define PMFUSES_AVFSSIZE 104 873 874 #define BTCGB0_Vdroop_Enable_MASK 0x1 875 #define BTCGB1_Vdroop_Enable_MASK 0x2 876 #define AVFSGB0_Vdroop_Enable_MASK 0x4 877 #define AVFSGB1_Vdroop_Enable_MASK 0x8 878 879 #define BTCGB0_Vdroop_Enable_SHIFT 0 880 #define BTCGB1_Vdroop_Enable_SHIFT 1 881 #define AVFSGB0_Vdroop_Enable_SHIFT 2 882 #define AVFSGB1_Vdroop_Enable_SHIFT 3 883 884 #pragma pack(pop) 885 886 887 #endif 888 889
Indexes created Tue Sep 30 06:09:59 GMT 2025