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Searched refs:CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v6_0.c	`3336 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3341 cp_int_cntl \|= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;`
sid.h	`2451 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000`
amdgpu_gfx_v7_0.c	`4818 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4823 cp_int_cntl \|= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_sh_mask.h	`2378 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L`
gfx_7_2_sh_mask.h	`1181 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000`
gfx_8_0_sh_mask.h	`1509 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 [all...]`
gfx_8_1_sh_mask.h	`2033 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 [all...]`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_sh_mask.h	`[all...]`
gc_9_1_sh_mask.h	`[all...]`
gc_9_2_1_sh_mask.h	`[all...]`
gc_10_1_0_sh_mask.h	`[all...]`

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