Searched refs:CUR_CONTROL (Results 1 - 4 of 4) sorted by relevance
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| H A D | dce_ipp.h | 38 SRI(CUR_CONTROL, DCP, id), \
71 IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
72 IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
73 IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
74 IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
202 uint32_t CUR_CONTROL; member in struct:dce_ipp_registers
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| H A D | amdgpu_dce_ipp.c | 60 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable);
103 REG_UPDATE_3(CUR_CONTROL,
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_dce_v10_0.c | 2312 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2328 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2329 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
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| H A D | amdgpu_dce_v11_0.c | 2391 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2407 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2408 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
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Completed in 13 milliseconds