| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| avivod.h | 46 #define D1VGA_CONTROL 0x0330
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_hwseq.h | 207 SR(D1VGA_CONTROL), \
272 SR(D1VGA_CONTROL), \
323 SR(D1VGA_CONTROL), \
415 uint32_t D1VGA_CONTROL;
570 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_timing_generator.c | 423 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE);
424 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT);
426 value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT);
427 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_timing_generator.c | 1839 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE);
1840 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT);
1842 value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT);
1843 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gmc_v10_0.c | 743 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); local in function:gmc_v10_0_get_vbios_fb_size
746 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
|
| amdgpu_gmc_v6_0.c | 824 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); local in function:gmc_v6_0_get_vbios_fb_size
827 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
|
| amdgpu_gmc_v7_0.c | 982 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); local in function:gmc_v7_0_get_vbios_fb_size
985 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
|
| amdgpu_gmc_v9_0.c | 1035 u32 d1vga_control; local in function:gmc_v9_0_get_vbios_fb_size
1045 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1046 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
|
| amdgpu_gmc_v8_0.c | 1094 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); local in function:gmc_v8_0_get_vbios_fb_size
1097 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer.c | 513 REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
522 REG_WRITE(D1VGA_CONTROL, 0);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hwseq.c | 255 REG_WRITE(D1VGA_CONTROL, 0);
|
