1 /* $NetBSD: amdgpu_gmc_v6_0.c,v 1.4 2021/12/19 12:21:29 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_gmc_v6_0.c,v 1.4 2021/12/19 12:21:29 riastradh Exp $"); 28 29 #include <linux/firmware.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 33 #include <drm/drm_cache.h> 34 #include "amdgpu.h" 35 #include "gmc_v6_0.h" 36 #include "amdgpu_ucode.h" 37 #include "amdgpu_gem.h" 38 39 #include "bif/bif_3_0_d.h" 40 #include "bif/bif_3_0_sh_mask.h" 41 #include "oss/oss_1_0_d.h" 42 #include "oss/oss_1_0_sh_mask.h" 43 #include "gmc/gmc_6_0_d.h" 44 #include "gmc/gmc_6_0_sh_mask.h" 45 #include "dce/dce_6_0_d.h" 46 #include "dce/dce_6_0_sh_mask.h" 47 #include "si_enums.h" 48 49 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev); 50 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); 51 static int gmc_v6_0_wait_for_idle(void *handle); 52 53 MODULE_FIRMWARE("amdgpu/tahiti_mc.bin"); 54 MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin"); 55 MODULE_FIRMWARE("amdgpu/verde_mc.bin"); 56 MODULE_FIRMWARE("amdgpu/oland_mc.bin"); 57 MODULE_FIRMWARE("amdgpu/hainan_mc.bin"); 58 MODULE_FIRMWARE("amdgpu/si58_mc.bin"); 59 60 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 61 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 62 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 63 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 64 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 65 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 66 #define MC_SEQ_MISC0__MT__HBM 0x60000000 67 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 68 69 70 static const u32 crtc_offsets[6] __unused = 71 { 72 SI_CRTC0_REGISTER_OFFSET, 73 SI_CRTC1_REGISTER_OFFSET, 74 SI_CRTC2_REGISTER_OFFSET, 75 SI_CRTC3_REGISTER_OFFSET, 76 SI_CRTC4_REGISTER_OFFSET, 77 SI_CRTC5_REGISTER_OFFSET 78 }; 79 80 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) 81 { 82 u32 blackout; 83 84 gmc_v6_0_wait_for_idle((void *)adev); 85 86 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 87 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 88 /* Block CPU access */ 89 WREG32(mmBIF_FB_EN, 0); 90 /* blackout the MC */ 91 blackout = REG_SET_FIELD(blackout, 92 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 93 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 94 } 95 /* wait for the MC to settle */ 96 udelay(100); 97 98 } 99 100 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) 101 { 102 u32 tmp; 103 104 /* unblackout the MC */ 105 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 106 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 107 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 108 /* allow CPU access */ 109 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 110 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 111 WREG32(mmBIF_FB_EN, tmp); 112 } 113 114 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) 115 { 116 const char *chip_name; 117 char fw_name[30]; 118 int err; 119 bool is_58_fw = false; 120 121 DRM_DEBUG("\n"); 122 123 switch (adev->asic_type) { 124 case CHIP_TAHITI: 125 chip_name = "tahiti"; 126 break; 127 case CHIP_PITCAIRN: 128 chip_name = "pitcairn"; 129 break; 130 case CHIP_VERDE: 131 chip_name = "verde"; 132 break; 133 case CHIP_OLAND: 134 chip_name = "oland"; 135 break; 136 case CHIP_HAINAN: 137 chip_name = "hainan"; 138 break; 139 default: BUG(); 140 } 141 142 /* this memory configuration requires special firmware */ 143 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) 144 is_58_fw = true; 145 146 if (is_58_fw) 147 snprintf(fw_name, sizeof(fw_name), "amdgpu/si58_mc.bin"); 148 else 149 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 150 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 151 if (err) 152 goto out; 153 154 err = amdgpu_ucode_validate(adev->gmc.fw); 155 156 out: 157 if (err) { 158 dev_err(adev->dev, 159 "si_mc: Failed to load firmware \"%s\"\n", 160 fw_name); 161 release_firmware(adev->gmc.fw); 162 adev->gmc.fw = NULL; 163 } 164 return err; 165 } 166 167 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) 168 { 169 const __le32 *new_fw_data = NULL; 170 u32 running; 171 const __le32 *new_io_mc_regs = NULL; 172 int i, regs_size, ucode_size; 173 const struct mc_firmware_header_v1_0 *hdr; 174 175 if (!adev->gmc.fw) 176 return -EINVAL; 177 178 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 179 180 amdgpu_ucode_print_mc_hdr(&hdr->header); 181 182 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 183 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 184 new_io_mc_regs = (const __le32 *) 185 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 186 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 187 new_fw_data = (const __le32 *) 188 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 189 190 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; 191 192 if (running == 0) { 193 194 /* reset the engine and set to writable */ 195 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 196 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 197 198 /* load mc io regs */ 199 for (i = 0; i < regs_size; i++) { 200 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); 201 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); 202 } 203 /* load the MC ucode */ 204 for (i = 0; i < ucode_size; i++) { 205 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); 206 } 207 208 /* put the engine back into the active state */ 209 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 210 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 211 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 212 213 /* wait for training to complete */ 214 for (i = 0; i < adev->usec_timeout; i++) { 215 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) 216 break; 217 udelay(1); 218 } 219 for (i = 0; i < adev->usec_timeout; i++) { 220 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) 221 break; 222 udelay(1); 223 } 224 225 } 226 227 return 0; 228 } 229 230 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, 231 struct amdgpu_gmc *mc) 232 { 233 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 234 base <<= 24; 235 236 amdgpu_gmc_vram_location(adev, mc, base); 237 amdgpu_gmc_gart_location(adev, mc); 238 } 239 240 static void gmc_v6_0_mc_program(struct amdgpu_device *adev) 241 { 242 int i, j; 243 244 /* Initialize HDP */ 245 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 246 WREG32((0xb05 + j), 0x00000000); 247 WREG32((0xb06 + j), 0x00000000); 248 WREG32((0xb07 + j), 0x00000000); 249 WREG32((0xb08 + j), 0x00000000); 250 WREG32((0xb09 + j), 0x00000000); 251 } 252 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 253 254 if (gmc_v6_0_wait_for_idle((void *)adev)) { 255 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 256 } 257 258 if (adev->mode_info.num_crtc) { 259 u32 tmp; 260 261 /* Lockout access through VGA aperture*/ 262 tmp = RREG32(mmVGA_HDP_CONTROL); 263 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK; 264 WREG32(mmVGA_HDP_CONTROL, tmp); 265 266 /* disable VGA render */ 267 tmp = RREG32(mmVGA_RENDER_CONTROL); 268 tmp &= ~VGA_VSTATUS_CNTL; 269 WREG32(mmVGA_RENDER_CONTROL, tmp); 270 } 271 /* Update configuration */ 272 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 273 adev->gmc.vram_start >> 12); 274 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 275 adev->gmc.vram_end >> 12); 276 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 277 adev->vram_scratch.gpu_addr >> 12); 278 WREG32(mmMC_VM_AGP_BASE, 0); 279 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 280 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 281 282 if (gmc_v6_0_wait_for_idle((void *)adev)) { 283 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 284 } 285 } 286 287 static int gmc_v6_0_mc_init(struct amdgpu_device *adev) 288 { 289 290 u32 tmp; 291 int chansize, numchan; 292 int r; 293 294 tmp = RREG32(mmMC_ARB_RAMCFG); 295 if (tmp & (1 << 11)) { 296 chansize = 16; 297 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) { 298 chansize = 64; 299 } else { 300 chansize = 32; 301 } 302 tmp = RREG32(mmMC_SHARED_CHMAP); 303 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 304 case 0: 305 default: 306 numchan = 1; 307 break; 308 case 1: 309 numchan = 2; 310 break; 311 case 2: 312 numchan = 4; 313 break; 314 case 3: 315 numchan = 8; 316 break; 317 case 4: 318 numchan = 3; 319 break; 320 case 5: 321 numchan = 6; 322 break; 323 case 6: 324 numchan = 10; 325 break; 326 case 7: 327 numchan = 12; 328 break; 329 case 8: 330 numchan = 16; 331 break; 332 } 333 adev->gmc.vram_width = numchan * chansize; 334 /* size in MB on si */ 335 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 336 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 337 338 if (!(adev->flags & AMD_IS_APU)) { 339 r = amdgpu_device_resize_fb_bar(adev); 340 if (r) 341 return r; 342 } 343 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 344 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 345 adev->gmc.visible_vram_size = adev->gmc.aper_size; 346 347 #ifdef __NetBSD__ 348 adev->gmc.aper_tag = adev->pdev->pd_pa.pa_memt; 349 #endif 350 351 /* set the gart size */ 352 if (amdgpu_gart_size == -1) { 353 switch (adev->asic_type) { 354 case CHIP_HAINAN: /* no MM engines */ 355 default: 356 adev->gmc.gart_size = 256ULL << 20; 357 break; 358 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ 359 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ 360 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ 361 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ 362 adev->gmc.gart_size = 1024ULL << 20; 363 break; 364 } 365 } else { 366 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 367 } 368 369 gmc_v6_0_vram_gtt_location(adev, &adev->gmc); 370 371 return 0; 372 } 373 374 static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 375 uint32_t vmhub, uint32_t flush_type) 376 { 377 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 378 } 379 380 static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 381 unsigned vmid, uint64_t pd_addr) 382 { 383 uint32_t reg; 384 385 /* write new base address */ 386 if (vmid < 8) 387 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 388 else 389 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8); 390 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 391 392 /* bits 0-15 are the VM contexts0-15 */ 393 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 394 395 return pd_addr; 396 } 397 398 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level, 399 uint64_t *addr, uint64_t *flags) 400 { 401 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 402 } 403 404 static void gmc_v6_0_get_vm_pte(struct amdgpu_device *adev, 405 struct amdgpu_bo_va_mapping *mapping, 406 uint64_t *flags) 407 { 408 *flags &= ~AMDGPU_PTE_EXECUTABLE; 409 *flags &= ~AMDGPU_PTE_PRT; 410 } 411 412 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, 413 bool value) 414 { 415 u32 tmp; 416 417 tmp = RREG32(mmVM_CONTEXT1_CNTL); 418 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 419 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 420 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 421 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 422 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 423 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 424 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 425 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 426 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 427 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 428 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 429 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 430 WREG32(mmVM_CONTEXT1_CNTL, tmp); 431 } 432 433 /** 434 + * gmc_v8_0_set_prt - set PRT VM fault 435 + * 436 + * @adev: amdgpu_device pointer 437 + * @enable: enable/disable VM fault handling for PRT 438 +*/ 439 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) 440 { 441 u32 tmp; 442 443 if (enable && !adev->gmc.prt_warning) { 444 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 445 adev->gmc.prt_warning = true; 446 } 447 448 tmp = RREG32(mmVM_PRT_CNTL); 449 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 450 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS, 451 enable); 452 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 453 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS, 454 enable); 455 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 456 L2_CACHE_STORE_INVALID_ENTRIES, 457 enable); 458 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 459 L1_TLB_STORE_INVALID_ENTRIES, 460 enable); 461 WREG32(mmVM_PRT_CNTL, tmp); 462 463 if (enable) { 464 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 465 uint32_t high = adev->vm_manager.max_pfn - 466 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 467 468 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 469 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 470 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 471 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 472 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 473 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 474 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 475 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 476 } else { 477 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 478 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 479 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 480 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 481 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 482 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 483 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 484 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 485 } 486 } 487 488 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) 489 { 490 uint64_t table_addr; 491 int r, i; 492 u32 field; 493 494 if (adev->gart.bo == NULL) { 495 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 496 return -EINVAL; 497 } 498 r = amdgpu_gart_table_vram_pin(adev); 499 if (r) 500 return r; 501 502 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 503 504 /* Setup TLB control */ 505 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 506 (0xA << 7) | 507 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK | 508 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK | 509 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 510 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK | 511 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 512 /* Setup L2 cache */ 513 WREG32(mmVM_L2_CNTL, 514 VM_L2_CNTL__ENABLE_L2_CACHE_MASK | 515 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK | 516 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 517 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 518 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 519 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 520 WREG32(mmVM_L2_CNTL2, 521 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | 522 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); 523 524 field = adev->vm_manager.fragment_size; 525 WREG32(mmVM_L2_CNTL3, 526 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 527 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) | 528 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 529 /* setup context0 */ 530 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 531 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 532 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 533 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 534 (u32)(adev->dummy_page_addr >> 12)); 535 WREG32(mmVM_CONTEXT0_CNTL2, 0); 536 WREG32(mmVM_CONTEXT0_CNTL, 537 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK | 538 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 539 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); 540 541 WREG32(0x575, 0); 542 WREG32(0x576, 0); 543 WREG32(0x577, 0); 544 545 /* empty context1-15 */ 546 /* set vm size, must be a multiple of 4 */ 547 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 548 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 549 /* Assign the pt base to something valid for now; the pts used for 550 * the VMs are determined by the application and setup and assigned 551 * on the fly in the vm part of radeon_gart.c 552 */ 553 for (i = 1; i < 16; i++) { 554 if (i < 8) 555 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 556 table_addr >> 12); 557 else 558 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 559 table_addr >> 12); 560 } 561 562 /* enable context1-15 */ 563 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 564 (u32)(adev->dummy_page_addr >> 12)); 565 WREG32(mmVM_CONTEXT1_CNTL2, 4); 566 WREG32(mmVM_CONTEXT1_CNTL, 567 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | 568 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 569 ((adev->vm_manager.block_size - 9) 570 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT)); 571 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 572 gmc_v6_0_set_fault_enable_default(adev, false); 573 else 574 gmc_v6_0_set_fault_enable_default(adev, true); 575 576 gmc_v6_0_flush_gpu_tlb(adev, 0, 0, 0); 577 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 578 (unsigned)(adev->gmc.gart_size >> 20), 579 (unsigned long long)table_addr); 580 adev->gart.ready = true; 581 return 0; 582 } 583 584 static int gmc_v6_0_gart_init(struct amdgpu_device *adev) 585 { 586 int r; 587 588 if (adev->gart.bo) { 589 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); 590 return 0; 591 } 592 r = amdgpu_gart_init(adev); 593 if (r) 594 return r; 595 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 596 adev->gart.gart_pte_flags = 0; 597 return amdgpu_gart_table_vram_alloc(adev); 598 } 599 600 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) 601 { 602 /*unsigned i; 603 604 for (i = 1; i < 16; ++i) { 605 uint32_t reg; 606 if (i < 8) 607 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ; 608 else 609 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8); 610 adev->vm_manager.saved_table_addr[i] = RREG32(reg); 611 }*/ 612 613 /* Disable all tables */ 614 WREG32(mmVM_CONTEXT0_CNTL, 0); 615 WREG32(mmVM_CONTEXT1_CNTL, 0); 616 /* Setup TLB control */ 617 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 618 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 619 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 620 /* Setup L2 cache */ 621 WREG32(mmVM_L2_CNTL, 622 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 623 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 624 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 625 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 626 WREG32(mmVM_L2_CNTL2, 0); 627 WREG32(mmVM_L2_CNTL3, 628 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 629 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 630 amdgpu_gart_table_vram_unpin(adev); 631 } 632 633 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, 634 u32 status, u32 addr, u32 mc_client) 635 { 636 u32 mc_id; 637 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 638 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 639 PROTECTIONS); 640 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 641 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 642 643 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 644 MEMORY_CLIENT_ID); 645 646 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 647 protections, vmid, addr, 648 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 649 MEMORY_CLIENT_RW) ? 650 "write" : "read", block, mc_client, mc_id); 651 } 652 653 /* 654 static const u32 mc_cg_registers[] = { 655 MC_HUB_MISC_HUB_CG, 656 MC_HUB_MISC_SIP_CG, 657 MC_HUB_MISC_VM_CG, 658 MC_XPB_CLK_GAT, 659 ATC_MISC_CG, 660 MC_CITF_MISC_WR_CG, 661 MC_CITF_MISC_RD_CG, 662 MC_CITF_MISC_VM_CG, 663 VM_L2_CG, 664 }; 665 666 static const u32 mc_cg_ls_en[] = { 667 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 668 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 669 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 670 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 671 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 672 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 673 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 674 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 675 VM_L2_CG__MEM_LS_ENABLE_MASK, 676 }; 677 678 static const u32 mc_cg_en[] = { 679 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 680 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 681 MC_HUB_MISC_VM_CG__ENABLE_MASK, 682 MC_XPB_CLK_GAT__ENABLE_MASK, 683 ATC_MISC_CG__ENABLE_MASK, 684 MC_CITF_MISC_WR_CG__ENABLE_MASK, 685 MC_CITF_MISC_RD_CG__ENABLE_MASK, 686 MC_CITF_MISC_VM_CG__ENABLE_MASK, 687 VM_L2_CG__ENABLE_MASK, 688 }; 689 690 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev, 691 bool enable) 692 { 693 int i; 694 u32 orig, data; 695 696 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 697 orig = data = RREG32(mc_cg_registers[i]); 698 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS)) 699 data |= mc_cg_ls_en[i]; 700 else 701 data &= ~mc_cg_ls_en[i]; 702 if (data != orig) 703 WREG32(mc_cg_registers[i], data); 704 } 705 } 706 707 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev, 708 bool enable) 709 { 710 int i; 711 u32 orig, data; 712 713 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 714 orig = data = RREG32(mc_cg_registers[i]); 715 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG)) 716 data |= mc_cg_en[i]; 717 else 718 data &= ~mc_cg_en[i]; 719 if (data != orig) 720 WREG32(mc_cg_registers[i], data); 721 } 722 } 723 724 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev, 725 bool enable) 726 { 727 u32 orig, data; 728 729 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 730 731 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) { 732 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 733 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 734 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 735 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 736 } else { 737 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 738 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 739 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 740 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 741 } 742 743 if (orig != data) 744 WREG32_PCIE(ixPCIE_CNTL2, data); 745 } 746 747 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, 748 bool enable) 749 { 750 u32 orig, data; 751 752 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 753 754 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) 755 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 756 else 757 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 758 759 if (orig != data) 760 WREG32(mmHDP_HOST_PATH_CNTL, data); 761 } 762 763 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, 764 bool enable) 765 { 766 u32 orig, data; 767 768 orig = data = RREG32(mmHDP_MEM_POWER_LS); 769 770 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) 771 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 772 else 773 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 774 775 if (orig != data) 776 WREG32(mmHDP_MEM_POWER_LS, data); 777 } 778 */ 779 780 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type) 781 { 782 switch (mc_seq_vram_type) { 783 case MC_SEQ_MISC0__MT__GDDR1: 784 return AMDGPU_VRAM_TYPE_GDDR1; 785 case MC_SEQ_MISC0__MT__DDR2: 786 return AMDGPU_VRAM_TYPE_DDR2; 787 case MC_SEQ_MISC0__MT__GDDR3: 788 return AMDGPU_VRAM_TYPE_GDDR3; 789 case MC_SEQ_MISC0__MT__GDDR4: 790 return AMDGPU_VRAM_TYPE_GDDR4; 791 case MC_SEQ_MISC0__MT__GDDR5: 792 return AMDGPU_VRAM_TYPE_GDDR5; 793 case MC_SEQ_MISC0__MT__DDR3: 794 return AMDGPU_VRAM_TYPE_DDR3; 795 default: 796 return AMDGPU_VRAM_TYPE_UNKNOWN; 797 } 798 } 799 800 static int gmc_v6_0_early_init(void *handle) 801 { 802 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 803 804 gmc_v6_0_set_gmc_funcs(adev); 805 gmc_v6_0_set_irq_funcs(adev); 806 807 return 0; 808 } 809 810 static int gmc_v6_0_late_init(void *handle) 811 { 812 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 813 814 amdgpu_bo_late_init(adev); 815 816 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 817 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 818 else 819 return 0; 820 } 821 822 static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev) 823 { 824 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 825 unsigned size; 826 827 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 828 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 829 } else { 830 u32 viewport = RREG32(mmVIEWPORT_SIZE); 831 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 832 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 833 4); 834 } 835 /* return 0 if the pre-OS buffer uses up most of vram */ 836 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 837 return 0; 838 return size; 839 } 840 841 static int gmc_v6_0_sw_init(void *handle) 842 { 843 int r; 844 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 845 846 adev->num_vmhubs = 1; 847 848 if (adev->flags & AMD_IS_APU) { 849 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 850 } else { 851 u32 tmp = RREG32(mmMC_SEQ_MISC0); 852 tmp &= MC_SEQ_MISC0__MT__MASK; 853 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp); 854 } 855 856 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault); 857 if (r) 858 return r; 859 860 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault); 861 if (r) 862 return r; 863 864 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 865 866 adev->gmc.mc_mask = 0xffffffffffULL; 867 868 #ifdef __NetBSD__ 869 r = drm_limit_dma_space(adev->ddev, 0, DMA_BIT_MASK(44)); 870 #else 871 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 872 #endif 873 if (r) { 874 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 875 return r; 876 } 877 adev->need_swiotlb = drm_need_swiotlb(44); 878 879 r = gmc_v6_0_init_microcode(adev); 880 if (r) { 881 dev_err(adev->dev, "Failed to load mc firmware!\n"); 882 return r; 883 } 884 885 r = gmc_v6_0_mc_init(adev); 886 if (r) 887 return r; 888 889 adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev); 890 891 r = amdgpu_bo_init(adev); 892 if (r) 893 return r; 894 895 r = gmc_v6_0_gart_init(adev); 896 if (r) 897 return r; 898 899 /* 900 * number of VMs 901 * VMID 0 is reserved for System 902 * amdgpu graphics/compute will use VMIDs 1-7 903 * amdkfd will use VMIDs 8-15 904 */ 905 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 906 amdgpu_vm_manager_init(adev); 907 908 /* base offset of vram pages */ 909 if (adev->flags & AMD_IS_APU) { 910 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 911 912 tmp <<= 22; 913 adev->vm_manager.vram_base_offset = tmp; 914 } else { 915 adev->vm_manager.vram_base_offset = 0; 916 } 917 918 return 0; 919 } 920 921 static int gmc_v6_0_sw_fini(void *handle) 922 { 923 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 924 925 amdgpu_gem_force_release(adev); 926 amdgpu_vm_manager_fini(adev); 927 amdgpu_gart_table_vram_free(adev); 928 amdgpu_bo_fini(adev); 929 amdgpu_gart_fini(adev); 930 release_firmware(adev->gmc.fw); 931 adev->gmc.fw = NULL; 932 933 return 0; 934 } 935 936 static int gmc_v6_0_hw_init(void *handle) 937 { 938 int r; 939 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 940 941 gmc_v6_0_mc_program(adev); 942 943 if (!(adev->flags & AMD_IS_APU)) { 944 r = gmc_v6_0_mc_load_microcode(adev); 945 if (r) { 946 dev_err(adev->dev, "Failed to load MC firmware!\n"); 947 return r; 948 } 949 } 950 951 r = gmc_v6_0_gart_enable(adev); 952 if (r) 953 return r; 954 955 return r; 956 } 957 958 static int gmc_v6_0_hw_fini(void *handle) 959 { 960 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 961 962 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 963 gmc_v6_0_gart_disable(adev); 964 965 return 0; 966 } 967 968 static int gmc_v6_0_suspend(void *handle) 969 { 970 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 971 972 gmc_v6_0_hw_fini(adev); 973 974 return 0; 975 } 976 977 static int gmc_v6_0_resume(void *handle) 978 { 979 int r; 980 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 981 982 r = gmc_v6_0_hw_init(adev); 983 if (r) 984 return r; 985 986 amdgpu_vmid_reset_all(adev); 987 988 return 0; 989 } 990 991 static bool gmc_v6_0_is_idle(void *handle) 992 { 993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 994 u32 tmp = RREG32(mmSRBM_STATUS); 995 996 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 997 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 998 return false; 999 1000 return true; 1001 } 1002 1003 static int gmc_v6_0_wait_for_idle(void *handle) 1004 { 1005 unsigned i; 1006 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1007 1008 for (i = 0; i < adev->usec_timeout; i++) { 1009 if (gmc_v6_0_is_idle(handle)) 1010 return 0; 1011 udelay(1); 1012 } 1013 return -ETIMEDOUT; 1014 1015 } 1016 1017 static int gmc_v6_0_soft_reset(void *handle) 1018 { 1019 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1020 u32 srbm_soft_reset = 0; 1021 u32 tmp = RREG32(mmSRBM_STATUS); 1022 1023 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1024 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1025 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1026 1027 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1028 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1029 if (!(adev->flags & AMD_IS_APU)) 1030 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1031 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1032 } 1033 1034 if (srbm_soft_reset) { 1035 gmc_v6_0_mc_stop(adev); 1036 if (gmc_v6_0_wait_for_idle(adev)) { 1037 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1038 } 1039 1040 1041 tmp = RREG32(mmSRBM_SOFT_RESET); 1042 tmp |= srbm_soft_reset; 1043 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1044 WREG32(mmSRBM_SOFT_RESET, tmp); 1045 tmp = RREG32(mmSRBM_SOFT_RESET); 1046 1047 udelay(50); 1048 1049 tmp &= ~srbm_soft_reset; 1050 WREG32(mmSRBM_SOFT_RESET, tmp); 1051 tmp = RREG32(mmSRBM_SOFT_RESET); 1052 1053 udelay(50); 1054 1055 gmc_v6_0_mc_resume(adev); 1056 udelay(50); 1057 } 1058 1059 return 0; 1060 } 1061 1062 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1063 struct amdgpu_irq_src *src, 1064 unsigned type, 1065 enum amdgpu_interrupt_state state) 1066 { 1067 u32 tmp; 1068 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1069 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1070 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1071 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1072 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1073 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1074 1075 switch (state) { 1076 case AMDGPU_IRQ_STATE_DISABLE: 1077 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1078 tmp &= ~bits; 1079 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1080 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1081 tmp &= ~bits; 1082 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1083 break; 1084 case AMDGPU_IRQ_STATE_ENABLE: 1085 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1086 tmp |= bits; 1087 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1088 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1089 tmp |= bits; 1090 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1091 break; 1092 default: 1093 break; 1094 } 1095 1096 return 0; 1097 } 1098 1099 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, 1100 struct amdgpu_irq_src *source, 1101 struct amdgpu_iv_entry *entry) 1102 { 1103 u32 addr, status; 1104 1105 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1106 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1107 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1108 1109 if (!addr && !status) 1110 return 0; 1111 1112 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1113 gmc_v6_0_set_fault_enable_default(adev, false); 1114 1115 if (printk_ratelimit()) { 1116 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1117 entry->src_id, entry->src_data[0]); 1118 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1119 addr); 1120 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1121 status); 1122 gmc_v6_0_vm_decode_fault(adev, status, addr, 0); 1123 } 1124 1125 return 0; 1126 } 1127 1128 static int gmc_v6_0_set_clockgating_state(void *handle, 1129 enum amd_clockgating_state state) 1130 { 1131 return 0; 1132 } 1133 1134 static int gmc_v6_0_set_powergating_state(void *handle, 1135 enum amd_powergating_state state) 1136 { 1137 return 0; 1138 } 1139 1140 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { 1141 .name = "gmc_v6_0", 1142 .early_init = gmc_v6_0_early_init, 1143 .late_init = gmc_v6_0_late_init, 1144 .sw_init = gmc_v6_0_sw_init, 1145 .sw_fini = gmc_v6_0_sw_fini, 1146 .hw_init = gmc_v6_0_hw_init, 1147 .hw_fini = gmc_v6_0_hw_fini, 1148 .suspend = gmc_v6_0_suspend, 1149 .resume = gmc_v6_0_resume, 1150 .is_idle = gmc_v6_0_is_idle, 1151 .wait_for_idle = gmc_v6_0_wait_for_idle, 1152 .soft_reset = gmc_v6_0_soft_reset, 1153 .set_clockgating_state = gmc_v6_0_set_clockgating_state, 1154 .set_powergating_state = gmc_v6_0_set_powergating_state, 1155 }; 1156 1157 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = { 1158 .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb, 1159 .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb, 1160 .set_prt = gmc_v6_0_set_prt, 1161 .get_vm_pde = gmc_v6_0_get_vm_pde, 1162 .get_vm_pte = gmc_v6_0_get_vm_pte, 1163 }; 1164 1165 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { 1166 .set = gmc_v6_0_vm_fault_interrupt_state, 1167 .process = gmc_v6_0_process_interrupt, 1168 }; 1169 1170 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev) 1171 { 1172 adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs; 1173 } 1174 1175 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1176 { 1177 adev->gmc.vm_fault.num_types = 1; 1178 adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs; 1179 } 1180 1181 const struct amdgpu_ip_block_version gmc_v6_0_ip_block = 1182 { 1183 .type = AMD_IP_BLOCK_TYPE_GMC, 1184 .major = 6, 1185 .minor = 0, 1186 .rev = 0, 1187 .funcs = &gmc_v6_0_ip_funcs, 1188 }; 1189
Indexes created Sat Sep 20 22:09:52 GMT 2025