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Searched refs:DCE3_HDMI_OFFSET1 (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
r600_reg.h	`201 #define DCE3_HDMI_OFFSET1 (0x7800 - 0x7400)`
radeon_r600.c	3683 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3684 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3828 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3924 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3958 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 4040 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 4042 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
radeon_display.c	`1544 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;`

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